coreboot

Please attach the coreboot console messages from a normal boot, and from resuming from suspend to RAM.

In GNU/Linux you should be able to do it using cbmem -1, or, if available, loading the module memconsole-coreboot with sudo modprobe memconsole-coreboot, and looking at /sys/firmware/log.

Paul Menzel wrote in #note-1:

Please attach the coreboot console messages from a normal boot, and from resuming from suspend to RAM.

In GNU/Linux you should be able to do it using cbmem -1, or, if available, loading the module memconsole-coreboot with sudo modprobe memconsole-coreboot, and looking at /sys/firmware/log.

Ok, I've attached the logs; one for booting normally and the other rebooting from suspend.

[ERROR]  SF size 0xc00000 does not correspond to CONFIG_ROM_SIZE 0x400000!!

CONFIG_ROM_SIZE needs to cover both chips. It's a known issue that coreboot will write the MRC cache at the wrong offset otherwise. As reading happens memory-mapped (not with manual SPI flash commands) it will use a different offset then. The cache is needed to bring DRAM up without destroying memory contents (would be bad during resume).

I concur with Nico's assessment. I imagine you changed the "ROM chip size" option to get a 4 MiB file to flash to the second flash chip (4 MiB).

Instead of doing that, https://doc.coreboot.org/mainboard/lenovo/Ivy_Bridge_series.html#splitting-the-coreboot-rom provides the commands to split a 12 MiB image into 8 MiB and 4 MiB parts. You'd want to use dd of=top.rom bs=1M if=build/coreboot.rom skip=8 to obtain a 4 MiB image.

As you've already installed coreboot, you can also flash internally with sudo flashrom -p internal --ifd -i bios -w build/coreboot.rom --noverify-all. This tells flashrom to write build/coreboot.rom to the flash chip(s) using the internal programmer, but only the "bios" region as described by the IFD of the system. The --noverify-all option tells flashrom to not verify the entire flash chip (to make sure other regions did not change), but only the written regions. This is needed when flashrom cannot read the entire flash chip, and the ME region is not readable by default.

Angel Pons wrote in #note-5:

I concur with Nico's assessment. I imagine you changed the "ROM chip size" option to get a 4 MiB file to flash to the second flash chip (4 MiB).

Instead of doing that, https://doc.coreboot.org/mainboard/lenovo/Ivy_Bridge_series.html#splitting-the-coreboot-rom provides the commands to split a 12 MiB image into 8 MiB and 4 MiB parts. You'd want to use dd of=top.rom bs=1M if=build/coreboot.rom skip=8 to obtain a 4 MiB image.

As you've already installed coreboot, you can also flash internally with sudo flashrom -p internal --ifd -i bios -w build/coreboot.rom --noverify-all. This tells flashrom to write build/coreboot.rom to the flash chip(s) using the internal programmer, but only the "bios" region as described by the IFD of the system. The --noverify-all option tells flashrom to not verify the entire flash chip (to make sure other regions did not change), but only the written regions. This is needed when flashrom cannot read the entire flash chip, and the ME region is not readable by default.

Yep, that worked, suspend works now. I've been having this issue for so long but didn't know exactly why. Thanks everyone for your help!

Edit: well it worked in linux, at least. Resuming S3 in windows flashes the power and mic LEDs, indicating a fatal error. I've attached the boot log (12mb_boot.txt) in case anyone has any ideas.

Edit 2: Nevermind, I figured it out. Just had to uncheck "rerun VGA option roms on S3 resume".

Josh, could you please open a separate issue? Thanks.

Angel Pons wrote in #note-10:

Josh, could you please open a separate issue? Thanks.

Sure thing, added here: https://ticket.coreboot.org/issues/432