It is likely that the PCIe root port on the southbridge (`device pci 1c.X` in the devicetree/overridetree, where X is a number between 0 and 5) used for LAN on your board is disabled. You could try enabling all 6 PCIe root ports and see ...Angel Pons
Rahul Arasikere wrote in #note-5: > I managed to get it to build by patching `util/crossgcc/buildgcc` and adding `-fno-char8_t` to `CXX_FOR_BUILD` variables in the script. > ... Did you mean `CXXFLAGS_FOR_BUILD`?Angel Pons
Avraham Hollander wrote in #note-2: > Angel Pons wrote in #note-1: > ... I completely missed that, apologies. I see that `CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"` is set to the correct value so I wonder why Windows is not seeing the AC...Angel Pons
Okay, false alarm: Nicholas Chin just let me know that the size reporting on Haswell / Lynx Point boards with 2 flash chips is consistently wrong. Looks like both coreboot and ifdtool decode the size wrongly.Angel Pons
Thanks for the logs. Margins look absolutely fine (yes, read timings have a bit of a positive offset, but I have seen this behaviour on all Haswell boards I've tried NRI on). I'm pretty sure this is a hardware limitation so the only thin...Angel Pons
Upon looking further into things, I think Haswell ULT only supports 11-bit column addresses for LPDDR3, not DDR3. However, Broadwell ULT might actually support 11-bit column addresses for DDR3. Broadwell Trad is out of the question for n...Angel Pons