AP Angel Pons
- Login: th3fanbus
- Registered on: 04/12/2019
- Last sign in: 08/23/2026
Issues
| open | closed | Total | |
|---|---|---|---|
| Assigned issues | 2 | 6 | 8 |
| Reported issues | 2 | 0 | 2 |
Projects
| Project | Roles | Registered on |
|---|---|---|
| coreboot | Manager, Developer | 05/08/2019 |
| flashrom | Manager | 02/12/2022 |
Activity
08/23/2026
- AP 09:31 AM coreboot Bug #655 (In Progress): m920q fails to do_global_reset() after 25.06
- CNL/CFL reference code always falls back to PCH reset after requesting a global reset via CSE. If the global reset request was successful, the code waits for 1 second to give CSE time to actually perform the reset.
https://review.core...
08/17/2026
- AP 07:50 AM coreboot Bug #658: asus p5g41c-m-lx pcie discovery of realtek 10ec:8168
- Nicholas Chin wrote in #note-19:
> Keith Hui wrote in #note-15:
> ...
For now I would just introduce a Kconfig symbol in the mainboard to select between DDR2 and DDR3.
08/15/2026
- AP 11:43 PM coreboot Bug #658: asus p5g41c-m-lx pcie discovery of realtek 10ec:8168
- Keith Hui wrote in #note-15:
> Out of curiosity I downloaded the boardview for this board. This is a board released in a time as we transition from DDR2 to DDR3, so it has slots for BOTH. The slots, counting outwards from the CPU socket...
07/21/2026
- AP 10:25 AM coreboot Bug #658: asus p5g41c-m-lx pcie discovery of realtek 10ec:8168
- Hi Gabriel,
You may want to check the Super I/O datasheet to see what the registers do. Each GPIO bank has a set of registers, with one bit per GPIO:
- I/O register: controls whether GPIOs are inputs or outputs
- Data register: show...
07/20/2026
- AP 01:12 PM coreboot Bug #658: asus p5g41c-m-lx pcie discovery of realtek 10ec:8168
- It is likely that the PCIe root port on the southbridge (`device pci 1c.X` in the devicetree/overridetree, where X is a number between 0 and 5) used for LAN on your board is disabled. You could try enabling all 6 PCIe root ports and see ...
05/26/2026
- AP 08:06 PM coreboot Other #649 (Closed (locked)): yes again support for ideapad but im not needing help i just want contribuition and contribuition means help
- A bug tracker is not meant to be used as a development scratchpad. Please refrain from creating any more issues.
05/23/2026
- AP 11:54 AM coreboot Support #636: Building GCC v14.2.0 for target ... failed. Check 'build-i386-elf-GCC/build.log'.
- Rahul Arasikere wrote in #note-5:
> I managed to get it to build by patching `util/crossgcc/buildgcc` and adding `-fno-char8_t` to `CXX_FOR_BUILD` variables in the script.
> ...
Did you mean `CXXFLAGS_FOR_BUILD`?
04/19/2026
- AP 03:27 PM coreboot Bug #638: ACPI\LEN0068 (ThinkPad Extra Buttons) not detected by Windows 11 on ThinkPad T430
- Avraham Hollander wrote in #note-2:
> Angel Pons wrote in #note-1:
> ...
I completely missed that, apologies. I see that `CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"` is set to the correct value so I wonder why Windows is not seeing the AC... - AP 10:46 AM coreboot Bug #638: ACPI\LEN0068 (ThinkPad Extra Buttons) not detected by Windows 11 on ThinkPad T430
- Can you please post your coreboot config file?
- AP 10:52 AM coreboot Bug #637: Sandybridge: C-States and Turbo not working in coreboot
- I wonder if it has to do with when `BIOS_RESET_CPL` MCHBAR register gets set.