Okay, false alarm: Nicholas Chin just let me know that the size reporting on Haswell / Lynx Point boards with 2 flash chips is consistently wrong. Looks like both coreboot and ifdtool decode the size wrongly.Angel Pons
Thanks for the logs. Margins look absolutely fine (yes, read timings have a bit of a positive offset, but I have seen this behaviour on all Haswell boards I've tried NRI on). I'm pretty sure this is a hardware limitation so the only thin...Angel Pons
Upon looking further into things, I think Haswell ULT only supports 11-bit column addresses for LPDDR3, not DDR3. However, Broadwell ULT might actually support 11-bit column addresses for DDR3. Broadwell Trad is out of the question for n...Angel Pons
First of all, I feel I have to address the elephant in the room: are there any success reports of people using 16 GiB DIMMs on a Haswell Trad (traditional, i.e. not ULT) computer? For the record, I cannot magically work around hardware l...Angel Pons
Looking at https://review.coreboot.org/89598 again, it seems that the bug already existed in the Haswell MRC codepath. The Broadwell MRC codepath did not have this issue, and NRI was N/A since it did not set up memory info until https://...Angel Pons
Looking back at that code, I should also check if forcing a 100 MHz ref clock results in the wrong speed being reported. Also, "related links" having such a giant text box tricked me.Angel Pons
1. I think the looping "resource didn't fit" thing should not be happening, as that's probably why coreboot hangs. 2. On the "old" logs, you seem to be using flashconsole with SMM. I think that can cause issues so it might be a good ide...Angel Pons