|
Looking for coreboot table at 0 4096 bytes.
|
|
Mapping 4096B of physical memory at 0x0 (requested 0x0).
|
|
Mapping 1320B of physical memory at 0x0 (requested 0x518).
|
|
... padding virtual address with 0x518 bytes.
|
|
Found!
|
|
coreboot table entry 0x11
|
|
Found forwarding entry.
|
|
Looking for coreboot table at 7ff5f000 4096 bytes.
|
|
Mapping 4096B of physical memory at 0x7ff5f000 (requested 0x7ff5f000).
|
|
Mapping 976B of physical memory at 0x7ff5f000 (requested 0x7ff5f018).
|
|
... padding virtual address with 0x18 bytes.
|
|
Found!
|
|
coreboot table entry 0x01
|
|
Found memory map.
|
|
LB_MEM_TABLE found.
|
|
LB_MEM_TABLE found.
|
|
coreboot table entry 0x03
|
|
coreboot table entry 0x04
|
|
coreboot table entry 0x05
|
|
coreboot table entry 0x06
|
|
coreboot table entry 0x07
|
|
coreboot table entry 0x26
|
|
coreboot table entry 0x29
|
|
coreboot table entry 0x16
|
|
Found timestamp table.
|
|
cbmem_addr = 7ffdc000
|
|
coreboot table entry 0x17
|
|
Found cbmem console.
|
|
cbmem_addr = 7ffde000
|
|
coreboot table entry 0x24
|
|
coreboot table entry 0x37
|
|
coreboot table entry 0x30
|
|
coreboot table entry 0x40
|
|
coreboot table entry 0x32
|
|
Found TSC info.
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x31
|
|
coreboot table entry 0x43
|
|
Mapping 8B of physical memory at 0x7ffde000 (requested 0x7ffde000).
|
|
Mapping 40015B of physical memory at 0x7ffde000 (requested 0x7ffde000).
|
|
*** Pre-CBMEM romstage console overflowed, log truncated! ***
|
|
aphics...
|
|
[DEBUG] Back from systemagent_early_init()
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Requested 0MB UMA
|
|
[DEBUG] Starting native Platform init
|
|
[DEBUG] DMI: Running at X4 @ 5000MT/s
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
|
|
[DEBUG] Trying stored timings.
|
|
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
|
|
[DEBUG] 100MHz reference clock support: yes
|
|
[DEBUG] PLL_REF100_CFG value: 0x7
|
|
[DEBUG] Trying CAS 11, tCK 320.
|
|
[DEBUG] Trying CAS 10, tCK 365.
|
|
[DEBUG] Trying CAS 9, tCK 384.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 666 MHz
|
|
[DEBUG] Selected CAS latency : 9T
|
|
[DEBUG] MPLL busy... done in 40 us
|
|
[DEBUG] MPLL frequency is set at : 666 MHz
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 2
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 7d600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 2
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] t123: 1912, 6000, 7620
|
|
[NOTE ] ME: Wrong mode : 2
|
|
[NOTE ] ME: FWS2: 0x110a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x1
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: ME is reporting as disabled, so not waiting for a response.
|
|
[NOTE ] ME: FWS2: 0x110a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x1
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: No DID Ack received
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Moff->Mx wake after an error
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1330 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00620010):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 4096 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] memcfg channel[1] config (00620010):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 4096 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] FMAP: area COREBOOT found @ 810200 (4128256 bytes)
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ffdb000
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 1: 0x80300000 0x100000
|
|
[DEBUG] Subregion 2: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x47700 size 0x4f14 in mcache @0xfeff1048
|
|
[DEBUG] Loading module at 0x7ffd0000 with entry 0x7ffd0031. filesize: 0x4b60 memsize: 0xae98
|
|
[DEBUG] Processing 221 relocs. Offset value of 0x7dfd0000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
|
|
|
|
|
|
[NOTE ] coreboot-4.17-1192-g47fee08fc3 Sat Aug 27 02:44:46 UTC 2022 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] FMAP: area COREBOOT found @ 810200 (4128256 bytes)
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x19780 size 0x19063 in mcache @0x7ffdd0dc
|
|
[DEBUG] Loading module at 0x7ff7c000 with entry 0x7ff7c000. filesize: 0x320f8 memsize: 0x52030
|
|
[DEBUG] Processing 3709 relocs. Offset value of 0x7bf7c000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
|
|
|
|
|
|
[NOTE ] coreboot-4.17-1192-g47fee08fc3 Sat Aug 27 02:44:46 UTC 2022 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 0000 enabled
|
|
[DEBUG] DOMAIN: 0000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 00
|
|
[DEBUG] PCI: 00:00.0 [8086/0154] enabled
|
|
[DEBUG] PCI: 00:01.0 [8086/0151] disabled
|
|
[DEBUG] PCI: 00:02.0 [8086/0166] enabled
|
|
[DEBUG] PCI: 00:04.0 [8086/0153] enabled
|
|
[DEBUG] PCI: 00:14.0 [8086/1e31] enabled
|
|
[DEBUG] PCI: 00:16.0 [8086/1e3a] enabled
|
|
[DEBUG] PCI: 00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:16.3: Disabling device
|
|
[DEBUG] PCI: 00:19.0 [8086/1502] enabled
|
|
[DEBUG] PCI: 00:1a.0 [8086/1e2d] enabled
|
|
[DEBUG] PCI: 00:1b.0 [8086/1e20] enabled
|
|
[INFO ] PCH: PCIe Root Port coalescing is enabled
|
|
[DEBUG] PCI: 00:1c.0 [8086/1e10] enabled
|
|
[DEBUG] PCI: 00:1c.1 [8086/1e12] enabled
|
|
[DEBUG] PCI: 00:1c.2 [8086/1e14] enabled
|
|
[DEBUG] PCI: 00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:1c.3 [8086/1e16] disabled
|
|
[DEBUG] PCI: 00:1c.4: Disabling device
|
|
[DEBUG] PCI: 00:1c.4: check set enabled
|
|
[DEBUG] PCI: 00:1c.5: Disabling device
|
|
[DEBUG] PCI: 00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:1c.7: Disabling device
|
|
[DEBUG] PCI: 00:1d.0 [8086/1e26] enabled
|
|
[DEBUG] PCI: 00:1e.0: Disabling device
|
|
[DEBUG] PCI: 00:1e.0 [8086/2448] disabled
|
|
[DEBUG] PCI: 00:1f.0 [8086/1e55] enabled
|
|
[DEBUG] PCI: 00:1f.2 [8086/1e01] enabled
|
|
[DEBUG] PCI: 00:1f.3 [8086/1e22] enabled
|
|
[DEBUG] PCI: 00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:1f.5 [8086/1e09] disabled No operations
|
|
[DEBUG] PCI: 00:1f.6 [8086/1e24] enabled
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:16.1
|
|
[WARN ] PCI: 00:16.2
|
|
[WARN ] PCI: 00:16.3
|
|
[WARN ] PCI: 00:1c.4
|
|
[WARN ] PCI: 00:1c.5
|
|
[WARN ] PCI: 00:1c.6
|
|
[WARN ] PCI: 00:1c.7
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 01
|
|
[DEBUG] PCI: 01:00.0 [1180/e823] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L0s and L1
|
|
[INFO ] PCIe: Max_Payload_Size adjusted to 128
|
|
[DEBUG] PCI: 01:00.0: No LTR support
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 02
|
|
[DEBUG] PCI: 02:00.0 [8086/2723] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L1
|
|
[INFO ] PCIe: Max_Payload_Size adjusted to 128
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.2 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 03
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.0 scanning...
|
|
[INFO ] PMH7: ID 05 Revision 12
|
|
[DEBUG] PNP: 00ff.1 enabled
|
|
[DEBUG] PNP: 0c31.0 enabled
|
|
[INFO ] H8: EC Firmware ID G2HT35WW-3.22, Version 4.01B
|
|
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
|
|
[INFO ] H8: WWAN not installed
|
|
[DEBUG] PNP: 00ff.2 enabled
|
|
[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 3 msecs
|
|
[DEBUG] PCI: 00:1f.3 scanning...
|
|
[DEBUG] I2C: 01:54 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 3 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 3 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 0 ms
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
|
|
[INFO ] MRC: No data in cbmem for 'RW_MRC_CACHE'.
|
|
[DEBUG] found VGA at PCI: 00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x27d600000 TOLUD 0x82a00000 TOM 0x200000000
|
|
[DEBUG] MEBASE 0x7ffff00000
|
|
[DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 6102M
|
|
[ERROR] PNP: 00ff.1 missing read_resources
|
|
[ERROR] PNP: 00ff.2 missing read_resources
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
|
|
[DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 01:00.0 10 * [0x0 - 0xff] mem
|
|
[DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 02:00.0 10 * [0x0 - 0x3fff] mem
|
|
[DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] NONE 18 * [0x0 - 0x1fff] io
|
|
[DEBUG] PCI: 00:1c.2 io: size: 2000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] NONE 10 * [0x0 - 0x7fffff] mem
|
|
[DEBUG] PCI: 00:1c.2 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem
|
|
[DEBUG] PCI: 00:1c.2 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed)
|
|
[DEBUG] update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: 5e0, Tag: 100
|
|
[INFO ] * Base: 15f0, Size: 10, Tag: 100
|
|
[INFO ] * Base: 167c, Size: e984, Tag: 100
|
|
[DEBUG] PCI: 00:1c.2 1c * [0x2000 - 0x3fff] limit: 3fff io
|
|
[DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
|
|
[DEBUG] PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io
|
|
[DEBUG] PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io
|
|
[DEBUG] PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io
|
|
[DEBUG] PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io
|
|
[DEBUG] PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io
|
|
[DEBUG] PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 05 base 100000000 limit 27d5fffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 09 base fed90000 limit fed90fff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0a base fed91000 limit fed91fff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200
|
|
[INFO ] * Base: f4000000, Size: ac00000, Tag: 200
|
|
[INFO ] * Base: fec01000, Size: 13f000, Tag: 200
|
|
[INFO ] * Base: fed45000, Size: 4b000, Tag: 200
|
|
[INFO ] * Base: fed92000, Size: 26e000, Tag: 200
|
|
[INFO ] * Base: 27d600000, Size: d82a00000, Tag: 100200
|
|
[DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
|
|
[DEBUG] PCI: 00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem
|
|
[DEBUG] PCI: 00:1c.2 20 * [0x83000000 - 0x837fffff] limit: 837fffff mem
|
|
[DEBUG] PCI: 00:1c.0 20 * [0x82a00000 - 0x82afffff] limit: 82afffff mem
|
|
[DEBUG] PCI: 00:1c.1 20 * [0x82b00000 - 0x82bfffff] limit: 82bfffff mem
|
|
[DEBUG] PCI: 00:19.0 10 * [0x83800000 - 0x8381ffff] limit: 8381ffff mem
|
|
[DEBUG] PCI: 00:14.0 10 * [0x83820000 - 0x8382ffff] limit: 8382ffff mem
|
|
[DEBUG] PCI: 00:04.0 10 * [0x83830000 - 0x83837fff] limit: 83837fff mem
|
|
[DEBUG] PCI: 00:1b.0 10 * [0x83838000 - 0x8383bfff] limit: 8383bfff mem
|
|
[DEBUG] PCI: 00:19.0 14 * [0x8383c000 - 0x8383cfff] limit: 8383cfff mem
|
|
[DEBUG] PCI: 00:1f.6 10 * [0x8383d000 - 0x8383dfff] limit: 8383dfff mem
|
|
[DEBUG] PCI: 00:1f.2 24 * [0x8383e000 - 0x8383e7ff] limit: 8383e7ff mem
|
|
[DEBUG] PCI: 00:1a.0 10 * [0x8383f000 - 0x8383f3ff] limit: 8383f3ff mem
|
|
[DEBUG] PCI: 00:1d.0 10 * [0x83840000 - 0x838403ff] limit: 838403ff mem
|
|
[DEBUG] PCI: 00:1f.3 10 * [0x83841000 - 0x838410ff] limit: 838410ff mem
|
|
[DEBUG] PCI: 00:16.0 10 * [0x83842000 - 0x8384200f] limit: 8384200f mem
|
|
[DEBUG] PCI: 00:1c.2 24 * [0x27d600000 - 0x28d5fffff] limit: 28d5fffff prefmem
|
|
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 00:1c.0 mem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff
|
|
[INFO ] PCI: 00:1c.0: Resource ranges:
|
|
[INFO ] * Base: 82a00000, Size: 100000, Tag: 200
|
|
[DEBUG] PCI: 01:00.0 10 * [0x82a00000 - 0x82a000ff] limit: 82a000ff mem
|
|
[DEBUG] PCI: 00:1c.0 mem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff done
|
|
[DEBUG] PCI: 00:1c.1 mem: base: 82b00000 size: 100000 align: 20 gran: 20 limit: 82bfffff
|
|
[INFO ] PCI: 00:1c.1: Resource ranges:
|
|
[INFO ] * Base: 82b00000, Size: 100000, Tag: 200
|
|
[DEBUG] PCI: 02:00.0 10 * [0x82b00000 - 0x82b03fff] limit: 82b03fff mem
|
|
[DEBUG] PCI: 00:1c.1 mem: base: 82b00000 size: 100000 align: 20 gran: 20 limit: 82bfffff done
|
|
[DEBUG] PCI: 00:1c.2 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
|
|
[INFO ] PCI: 00:1c.2: Resource ranges:
|
|
[INFO ] * Base: 2000, Size: 2000, Tag: 100
|
|
[DEBUG] NONE 18 * [0x2000 - 0x3fff] limit: 3fff io
|
|
[DEBUG] PCI: 00:1c.2 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
|
|
[DEBUG] PCI: 00:1c.2 prefmem: base: 27d600000 size: 10000000 align: 20 gran: 20 limit: 28d5fffff
|
|
[INFO ] PCI: 00:1c.2: Resource ranges:
|
|
[INFO ] * Base: 27d600000, Size: 10000000, Tag: 1200
|
|
[DEBUG] NONE 14 * [0x27d600000 - 0x28d5fffff] limit: 28d5fffff prefmem
|
|
[DEBUG] PCI: 00:1c.2 prefmem: base: 27d600000 size: 10000000 align: 20 gran: 20 limit: 28d5fffff done
|
|
[DEBUG] PCI: 00:1c.2 mem: base: 83000000 size: 800000 align: 20 gran: 20 limit: 837fffff
|
|
[INFO ] PCI: 00:1c.2: Resource ranges:
|
|
[INFO ] * Base: 83000000, Size: 800000, Tag: 200
|
|
[DEBUG] NONE 10 * [0x83000000 - 0x837fffff] limit: 837fffff mem
|
|
[DEBUG] PCI: 00:1c.2 mem: base: 83000000 size: 800000 align: 20 gran: 20 limit: 837fffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:02.0 10 <- [0x0000000082c00000 - 0x0000000082ffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:04.0 10 <- [0x0000000083830000 - 0x0000000083837fff] size 0x00008000 gran 0x0f mem64
|
|
[DEBUG] PCI: 00:14.0 10 <- [0x0000000083820000 - 0x000000008382ffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:16.0 10 <- [0x0000000083842000 - 0x000000008384200f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:19.0 10 <- [0x0000000083800000 - 0x000000008381ffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:19.0 14 <- [0x000000008383c000 - 0x000000008383cfff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:19.0 18 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1a.0 10 <- [0x000000008383f000 - 0x000000008383f3ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:1b.0 10 <- [0x0000000083838000 - 0x000000008383bfff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
|
[DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
[DEBUG] PCI: 00:1c.0 20 <- [0x0000000082a00000 - 0x0000000082afffff] size 0x00100000 gran 0x14 bus 01 mem
|
|
[DEBUG] PCI: 01:00.0 10 <- [0x0000000082a00000 - 0x0000000082a000ff] size 0x00000100 gran 0x08 mem
|
|
[DEBUG] PCI: 00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
|
[DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
|
[DEBUG] PCI: 00:1c.1 20 <- [0x0000000082b00000 - 0x0000000082bfffff] size 0x00100000 gran 0x14 bus 02 mem
|
|
[DEBUG] PCI: 02:00.0 10 <- [0x0000000082b00000 - 0x0000000082b03fff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:1c.2 1c <- [0x0000000000002000 - 0x0000000000003fff] size 0x00002000 gran 0x0c bus 03 io
|
|
[DEBUG] PCI: 00:1c.2 24 <- [0x000000027d600000 - 0x000000028d5fffff] size 0x10000000 gran 0x14 bus 03 prefmem
|
|
[DEBUG] PCI: 00:1c.2 20 <- [0x0000000083000000 - 0x00000000837fffff] size 0x00800000 gran 0x14 bus 03 mem
|
|
[DEBUG] PCI: 00:1d.0 10 <- [0x0000000083840000 - 0x00000000838403ff] size 0x00000400 gran 0x0a mem
|
|
[ERROR] PNP: 00ff.1 missing set_resources
|
|
[ERROR] PNP: 00ff.2 missing set_resources
|
|
[DEBUG] PCI: 00:1f.2 10 <- [0x0000000000001080 - 0x0000000000001087] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:1f.2 14 <- [0x0000000000001090 - 0x0000000000001093] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:1f.2 18 <- [0x0000000000001088 - 0x000000000000108f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:1f.2 1c <- [0x0000000000001094 - 0x0000000000001097] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:1f.2 20 <- [0x0000000000001060 - 0x000000000000107f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1f.2 24 <- [0x000000008383e000 - 0x000000008383e7ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:1f.3 10 <- [0x0000000083841000 - 0x00000000838410ff] size 0x00000100 gran 0x08 mem64
|
|
[DEBUG] PCI: 00:1f.6 10 <- [0x000000008383d000 - 0x000000008383dfff] size 0x00001000 gran 0x0c mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00.0 subsystem <- 8086/0154
|
|
[DEBUG] PCI: 00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:02.0 subsystem <- 8086/0166
|
|
[DEBUG] PCI: 00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:04.0 cmd <- 02
|
|
[DEBUG] PCI: 00:14.0 subsystem <- 8086/1e31
|
|
[DEBUG] PCI: 00:14.0 cmd <- 102
|
|
[DEBUG] PCI: 00:16.0 subsystem <- 8086/1e3a
|
|
[DEBUG] PCI: 00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:19.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:1a.0 subsystem <- 8086/1e2d
|
|
[DEBUG] PCI: 00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1b.0 subsystem <- 8086/1e20
|
|
[DEBUG] PCI: 00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.0 subsystem <- 8086/1e10
|
|
[DEBUG] PCI: 00:1c.0 cmd <- 106
|
|
[DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.1 subsystem <- 8086/1e12
|
|
[DEBUG] PCI: 00:1c.1 cmd <- 106
|
|
[DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.2 subsystem <- 8086/1e14
|
|
[DEBUG] PCI: 00:1c.2 cmd <- 107
|
|
[DEBUG] PCI: 00:1d.0 subsystem <- 8086/1e26
|
|
[DEBUG] PCI: 00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1f.0 subsystem <- 8086/1e55
|
|
[DEBUG] PCI: 00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:1f.2 subsystem <- 8086/1e03
|
|
[DEBUG] PCI: 00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:1f.3 subsystem <- 8086/1e22
|
|
[DEBUG] PCI: 00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 00:1f.6 subsystem <- 8086/1e24
|
|
[DEBUG] PCI: 00:1f.6 cmd <- 02
|
|
[DEBUG] PCI: 01:00.0 subsystem <- 1180/e823
|
|
[DEBUG] PCI: 01:00.0 cmd <- 06
|
|
[DEBUG] PCI: 02:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[INFO ] Found TPM ST33ZP24 by ST Microelectronics
|
|
[DEBUG] TPM: Startup
|
|
[DEBUG] TPM: command 0x99 returned 0x0
|
|
[DEBUG] TPM: Asserting physical presence
|
|
[DEBUG] TPM: command 0x4000000a returned 0x0
|
|
[DEBUG] TPM: command 0x65 returned 0x0
|
|
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
|
|
[INFO ] TPM: setup succeeded
|
|
[DEBUG] BS: BS_DEV_INIT entry times (exec / console): 48 / 0 ms
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000027d5fffff size 0x17d600000 type 6
|
|
[DEBUG] 0x000000027d600000 - 0x000000028d5fffff size 0x10000000 type 0
|
|
[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 12/7.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
|
|
[DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 4 base 0x000000027d600000 mask 0x0000000fffe00000 type 0
|
|
[DEBUG] MTRR: 5 base 0x000000027d800000 mask 0x0000000fff800000 type 0
|
|
[DEBUG] MTRR: 6 base 0x000000027e000000 mask 0x0000000ffe000000 type 0
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 2 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[DEBUG] FMAP: area COREBOOT found @ 810200 (4128256 bytes)
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x12f40 size 0x6800 in mcache @0x7ffdd0ac
|
|
[DEBUG] microcode: sig=0x306a9 pf=0x10 revision=0x21
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 18 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[DEBUG] done.
|
|
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x3 in XAPIC mode.
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[INFO ] AP: slot 2 apic_id 3, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000021
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8
|
|
[DEBUG] Processing 11 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ff94225
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] FX_SAVE [0x802ff800-0x80300000]
|
|
[DEBUG] HANDLER [0x802fe000-0x802ff568]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fdc00-0x802fe000]
|
|
[DEBUG] stub0 [0x802f6000-0x802f61e8]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fd800-0x802fdc00]
|
|
[DEBUG] stub1 [0x802f5c00-0x802f5de8]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fd400-0x802fd800]
|
|
[DEBUG] stub2 [0x802f5800-0x802f59e8]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fd000-0x802fd400]
|
|
[DEBUG] stub3 [0x802f5400-0x802f55e8]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80001000]
|
|
[DEBUG] Loading module at 0x802fe000 with entry 0x802fe34c. filesize: 0x1550 memsize: 0x1568
|
|
[DEBUG] Processing 68 relocs. Offset value of 0x802fe000
|
|
[DEBUG] Loading module at 0x802f6000 with entry 0x802f6000. filesize: 0x1e8 memsize: 0x1e8
|
|
[DEBUG] Processing 11 relocs. Offset value of 0x802f6000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 802f6000. Will call 0x802fe34c
|
|
[DEBUG] Initializing southbridge SMI...
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ee000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802ee000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802edc00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802edc00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed800, cpu = 2
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ed800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ed400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] CPU: platform id 4
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #2
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] CPU: platform id 4
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: platform id 4
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] CPU: platform id 4
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #2 initialized
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[INFO ] CPU #3 initialized
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 9 msecs.
|
|
[DEBUG] Initializing southbridge SMI...
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 22 msecs
|
|
[DEBUG] PCI: 00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling PEG10.
|
|
[DEBUG] Disabling PEG60.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Disabling PEG IO clock.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 35 Watts
|
|
[DEBUG] PCI: 00:00.0 init finished in 1 msecs
|
|
[DEBUG] PCI: 00:02.0 init
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x36880 size 0x599 in mcache @0x7ffdd1c4
|
|
[INFO ] Found a VBT of 4281 bytes after decompression
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[DEBUG] IVB GT2 25W-35W Power Meter Weights
|
|
[INFO ] CBFS: Found 'pci8086,0166.rom' @0x376c0 size 0x10000 in mcache @0x7ffdd21c
|
|
[DEBUG] In CBFS, ROM address for PCI: 00:02.0 = 0xffc478ec
|
|
[DEBUG] Copying VGA ROM Image from 0xffc478ec to 0xc0000, 0x10000 bytes
|
|
[ERROR] Null dereference at eip: 0x7ff8c769
|
|
[ERROR] Null dereference at eip: 0x7ff8c783
|
|
[DEBUG] Calling Option ROM...
|
|
[DEBUG] intel_vga_int15_handler: AX=5fac BX=0190 CX=0000 DX=00c0
|
|
[DEBUG] Unknown INT15 function 5fac!
|
|
[DEBUG] int15 call returned error.
|
|
[DEBUG] intel_vga_int15_handler: AX=5f40 BX=0000 CX=0004 DX=0001
|
|
[DEBUG] DISPLAY=0
|
|
[DEBUG] intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da
|
|
[DEBUG] ... Option ROM returned.
|
|
[DEBUG] VGA Option ROM was run
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[DEBUG] PCI: 00:02.0 init finished in 441 msecs
|
|
[DEBUG] PCI: 00:04.0 init
|
|
[DEBUG] PCI: 00:04.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:14.0 init
|
|
[DEBUG] XHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:14.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Moff->Mx wake after an error
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[CRIT ] intel_me_path: mbp is not ready!
|
|
[NOTE ] ME: BIOS path: Error
|
|
[DEBUG] ME: me_state=0, me_state_prev=0
|
|
[DEBUG] PCI: 00:16.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:19.0 init
|
|
[DEBUG] PCI: 00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:1a.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1b.0 init
|
|
[DEBUG] Azalia: base = 0x83838000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: Initializing codec #3
|
|
[DEBUG] azalia_audio: codec viddid: 80862806
|
|
[DEBUG] azalia_audio: verb_size: 16
|
|
[DEBUG] azalia_audio: verb loaded.
|
|
[DEBUG] azalia_audio: Initializing codec #0
|
|
[DEBUG] azalia_audio: codec viddid: 10ec0269
|
|
[DEBUG] azalia_audio: verb_size: 76
|
|
[DEBUG] azalia_audio: verb loaded.
|
|
[DEBUG] PCI: 00:1b.0 init finished in 5 msecs
|
|
[DEBUG] PCI: 00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:1c.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.1 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:1c.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.2 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:1c.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:1d.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected QM77, device id: 0x1e55, rev id 0x4
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000
|
|
[DEBUG] IOAPIC: ID = 0x02
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] PantherPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:1f.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0x8383e000
|
|
[DEBUG] PCI: 00:1f.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.3 init
|
|
[DEBUG] PCI: 00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.6 init
|
|
[DEBUG] PCI: 00:1f.6 init finished in 0 msecs
|
|
[DEBUG] PCI: 01:00.0 init
|
|
[DEBUG] PCI: 01:00.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 02:00.0 init
|
|
[DEBUG] PCI: 02:00.0 init finished in 0 msecs
|
|
[DEBUG] PNP: 00ff.2 init
|
|
[DEBUG] Keyboard init...
|
|
[INFO ] Keyboard controller output buffer result timeout
|
|
[INFO ] Keyboard controller output buffer result timeout
|
|
[INFO ] Keyboard controller output buffer result timeout
|
|
[INFO ] Keyboard controller output buffer result timeout
|
|
[ERROR] Keyboard reset failed ACK: 0xaa
|
|
[DEBUG] PNP: 00ff.2 init finished in 1830 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
|
[DEBUG] I2C: 01:54 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
|
[DEBUG] I2C: 01:55 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
|
[DEBUG] I2C: 01:56 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
|
[DEBUG] I2C: 01:57 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
|
[DEBUG] Locking EEPROM RFID
|
|
[DEBUG] init EEPROM done
|
|
[DEBUG] I2C: 01:5c init finished in 23 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
|
[DEBUG] I2C: 01:5d init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
|
[DEBUG] I2C: 01:5e init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
|
[DEBUG] I2C: 01:5f init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 2324 / 1 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:1f.0 final
|
|
[DEBUG] flash size 0xc00000 bytes
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0xc00000
|
|
[DEBUG] apm_control: Finalizing SMM.
|
|
[DEBUG] APMC done.
|
|
[INFO ] Devices finalized
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x32f40 size 0x390a in mcache @0x7ffdd198
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7ff3b000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * DSDT
|
|
[DEBUG] ACPI: * FADT
|
|
[DEBUG] ACPI: added table 1/32, length now 40
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x27d600000, len = 0xd82a00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
|
|
[INFO ] ACPI: * H8
|
|
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
|
|
[INFO ] H8: WWAN not installed
|
|
[INFO ] \_SB.PCI0.RP02.WF00: PCI: 02:00.0
|
|
[DEBUG] ACPI: added table 2/32, length now 44
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 48
|
|
[DEBUG] ACPI: * TCPA
|
|
[DEBUG] TCPA log created at 0x7ff2b000
|
|
[DEBUG] ACPI: added table 4/32, length now 52
|
|
[DEBUG] ACPI: * MADT
|
|
[DEBUG] ACPI: added table 5/32, length now 56
|
|
[DEBUG] current = 7ff40790
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 6/32, length now 60
|
|
[DEBUG] current = 7ff40850
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 7/32, length now 64
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 22672 bytes.
|
|
[DEBUG] smbios_write_tables: 7ff23000
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[INFO ] PCI: 02:00.0 (unknown)
|
|
[DEBUG] SMBIOS tables: 1134 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 8fe8
|
|
[DEBUG] Writing coreboot table at 0x7ff5f000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
|
|
[DEBUG] 3. 0000000000100000-000000007ff22fff: RAM
|
|
[DEBUG] 4. 000000007ff23000-000000007ff7bfff: CONFIGURATION TABLES
|
|
[DEBUG] 5. 000000007ff7c000-000000007ffcefff: RAMSTAGE
|
|
[DEBUG] 6. 000000007ffcf000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 0000000080000000-00000000829fffff: RESERVED
|
|
[DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 9. 00000000fed40000-00000000fed44fff: RESERVED
|
|
[DEBUG] 10. 00000000fed90000-00000000fed91fff: RESERVED
|
|
[DEBUG] 11. 0000000100000000-000000027d5fffff: RAM
|
|
[DEBUG] Wrote coreboot table at: 0x7ff5f000, 0x3b8 bytes, checksum f84d
|
|
[DEBUG] coreboot table: 976 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
|
|
[DEBUG] RO MCACHE 3. 0x7ffdd000 0x000003d0
|
|
[DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910
|
|
[DEBUG] MEM INFO 5. 0x7ffdb000 0x00000768
|
|
[DEBUG] AFTER CAR 6. 0x7ffcf000 0x0000c000
|
|
[DEBUG] RAMSTAGE 7. 0x7ff7b000 0x00054000
|
|
[DEBUG] SMM BACKUP 8. 0x7ff6b000 0x00010000
|
|
[DEBUG] IGD OPREGION 9. 0x7ff67000 0x000030b8
|
|
[DEBUG] COREBOOT 10. 0x7ff5f000 0x00008000
|
|
[DEBUG] ACPI 11. 0x7ff3b000 0x00024000
|
|
[DEBUG] TCPA TCGLOG12. 0x7ff2b000 0x00010000
|
|
[DEBUG] SMBIOS 13. 0x7ff23000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7fffeb20 0x000000e0
|
|
[DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004
|
|
[DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8
|
|
[DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 25 / 0 ms
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x63600 size 0x1187b in mcache @0x7ffdd2dc
|
|
[DEBUG] Checking segment from ROM address 0xffc7382c
|
|
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
|
|
[DEBUG] Checking segment from ROM address 0xffc73848
|
|
[DEBUG] Loading segment from ROM address 0xffc7382c
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x000dede0 memsize 0x21220 srcaddr 0xffc73864 filesize 0x11843
|
|
[DEBUG] Loading Segment: addr: 0x000dede0 memsz: 0x0000000000021220 filesz: 0x0000000000011843
|
|
[DEBUG] using LZMA
|
|
[DEBUG] Loading segment from ROM address 0xffc73848
|
|
[DEBUG] Entry Point 0x000fd25b
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 26 / 0 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x000fd25b(0x7ff5f000)
|
|
SeaBIOS (version rel-1.16.0-0-gd239552)
|
|
BUILD: gcc: (coreboot toolchain v2022-08-22_88ffed3df8) 11.2.0 binutils: (GNU Binutils) 2.37
|
|
Found coreboot cbmem console @ 7ffde000
|
|
Found mainboard LENOVO ThinkPad X230
|
|
Relocating init from 0x000e0540 to 0x7fed5ac0 (size 54432)
|
|
Found CBFS header at 0xffc1022c
|
|
multiboot: eax=7ffad598, ebx=7ffad564
|
|
Found 18 PCI devices (max PCI bus is 03)
|
|
Copying SMBIOS from 0x7ff23000 to 0x000f67c0
|
|
Copying SMBIOS 3.0 from 0x7ff23020 to 0x000f67a0
|
|
Copying ACPI RSDP from 0x7ff3b000 to 0x000f6770
|
|
table(50434146)=0x7ff3eba0 (via xsdt)
|
|
Using pmtimer, ioport 0x508
|
|
table(41504354)=0x7ff406e0 (via xsdt)
|
|
Scan for VGA option rom
|
|
Running option rom at c000:0003
|
|
Turning on vga text mode console
|
|
SeaBIOS (version rel-1.16.0-0-gd239552)
|
|
Machine UUID ddf76e01-5251-11cb-b3cf-aaae51e6a824
|
|
PCI: XHCI at 00:14.0 (mmio 0x83820000)
|
|
XHCI init: regs @ 0x83820000, 8 ports, 32 slots, 32 byte contexts
|
|
XHCI protocol USB 2.00, 4 ports (offset 1), def 3001
|
|
XHCI protocol USB 3.00, 4 ports (offset 5), def 1000
|
|
XHCI extcap 0xc1 @ 0x83828040
|
|
XHCI extcap 0xc0 @ 0x83828070
|
|
XHCI extcap 0x1 @ 0x83828330
|
|
EHCI init on dev 00:1a.0 (regs=0x8383f020)
|
|
EHCI init on dev 00:1d.0 (regs=0x83840020)
|
|
AHCI controller at 00:1f.2, iobase 0x8383e000, irq 11
|
|
Searching bootorder for: /pci@i0cf8/pci-bridge@1c/*@0
|
|
Discarding ps2 data 0f (status=11)
|
|
Searching bootorder for: HALT
|
|
Found 0 lpt ports
|
|
Found 0 serial ports
|
|
Searching bootorder for: /rom@img/nvramcui
|
|
Searching bootorder for: /rom@img/coreinfo
|
|
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@2/disk@0
|
|
AHCI/2: Set transfer mode to UDMA-6
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Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@2/disk@0
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AHCI/2: registering: "AHCI/2: INTEL SSDMAEMC080G2L ATA-7 Hard-Disk (74 GiBytes)"
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Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
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AHCI/0: Set transfer mode to UDMA-6
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Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
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AHCI/0: registering: "AHCI/0: TEAM T253X1480G ATA-9 Hard-Disk (447 GiBytes)"
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XHCI no devices found
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Initialized USB HUB (0 ports used)
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PS2 keyboard initialized
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WARNING - Timeout at ehci_wait_td:517!
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ehci pipe=0x7fecf500 cur=7fec8dc0 tok=80080d80 next=7fec8e00 td=0x7fec8dc0 status=80080d80
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Initialized USB HUB (0 ports used)
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All threads complete.
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Scan for option roms
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Press ESC for boot menu.
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Searching bootorder for: HALT
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drive 0x000f66b0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=937703088
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drive 0x000f6700: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=156301488
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Space available for UMB: d0000-ec800, f5fe0-f66b0
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Returned 180224 bytes of ZoneHigh
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e820 map has 9 items:
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0: 0000000000000000 - 000000000009fc00 = 1 RAM
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1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
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2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
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3: 0000000000100000 - 000000007ff0f000 = 1 RAM
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4: 000000007ff0f000 - 0000000082a00000 = 2 RESERVED
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5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
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6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
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7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
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8: 0000000100000000 - 000000027d600000 = 1 RAM
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enter handle_19:
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NULL
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Booting from Hard Disk...
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Booting from 0000:7c00
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