Arthur Heymans


Reported issues: 1


03:15 PM coreboot Bug #321: NVME in X16 port issue
Can you provide a coreboot log: either capture it from serial or try to boot from a different port and use util/cbmem...


09:47 AM coreboot Feature #307: Support FMAP in SeaBIOS
Patrick Georgi wrote:
> SeaBIOS requires the CBFS master header to find the start address of the CBFS structure. It ...


01:49 PM coreboot Bug #176: src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspapi.h has a proprietary license
This code was dropped from the master branch so this can be closed.


11:29 AM coreboot Bug #169: `cbfstool coreboot.rom compact` moves bootblock
Some cbfsfiles need to be at a fixed offset, others need a certain alignment. `compact` could have some specific use ...


07:56 PM coreboot Bug #167: X201 restarts rather than waking up
SeaBIOS 1.11 with CONFIG_SERCONN is known to break S3.
Could you paste a coreboot log of when coreboot rebooted in...


09:49 AM coreboot Feature #115: Consolidate Intel ICH7..PCH9 PIRQ configuration
Is implemented. Just has to be hooked up: and https://review.corebo...


11:07 PM coreboot Feature #38: tp_smapi support on ThinkPads
Implemented the acpi functions tpacpi-bat uses in This can easily ...
10:43 PM coreboot Bug #150: payloads/external/SeaBIOS/seabios/.config:3:warning: symbol value '' invalid for DEBUG_... should fix it


11:24 AM coreboot Bug #100: romstage only transferred with baud rate 1200 independent from configuration
I think this is fixed now in ?


08:49 AM coreboot Feature #39: Enable OS-level flashing of coreboot for ThinkPad T410/X201
Sometimes whitelist removed modified vendor BIOS don't write protect their bootblock (it is the case on Thinkpad x200...

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