Bug #628
openmb/asus/h61-series: variant p8h61-i_r2_0 won't POST on recent coreboot version mmio / tpm range ?
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Description
Variant Asus h61-series p8h61-i_r2_0 WIP code under review:
https://review.coreboot.org/c/coreboot/+/91337
Possible issue commit sb/intel/bd82x6x/lpc: Advertise all fixed MMIO ranges:
https://review.coreboot.org/c/coreboot/+/91040
If this patch is applied to old coreboot codebase 25.06-77-g812d0e2f626d as a whole or on current codebase, boot will stall before POST/BOOT so no screen but machine stays powered on and hangs forever, on old codebase you seen USB poweron on current codebase you don't!
SPI console log snippet loops here from old coreboot codebase, see diff at line ~470 and ~550:
Resource didn't fit!!!
PNP: 002e.a 60 * size: 0x8 limit: fff io
Uploaded 3 SPI logs from old coreboot base, mmio123456 means whole patch CB:91040 applied and mmio12346 means skipped the TPM part (5th block) of that patch, the shortest named file is the one with original unpatched lpc.c file!
Files
PR Updated by Patrick Rudolph 3 days ago
I still don't see why the mentioned commit should make any difference. Your log shows issues with I/O resources on the Super I/O.
Try disabling unused SIO LDNs:
Add this to your devicetree:
device pnp 2e.0 off end # FDC
device pnp 2e.a off end # IR
When you do not disable them they'll get automatically enabled, but have no valid resource assigned.
WS Updated by Walter Sonius 3 days ago
- File p8h61ir2-21-old-edk2-spilogdb-mmio123456-siooff-cbmem.rom.log p8h61ir2-21-old-edk2-spilogdb-mmio123456-siooff-cbmem.rom.log added
Still have to test without SPI log and on current coreboot codebase but looking at this latest SPI log with superio devices disabled in devicetree.cb as you hinted I see it progress beyond that point like the other 2 logs (normal lpc.c and the one without TPM region).
Spinning another current coreboot image with TPM region restored and devicetree.cb superio edits and without the SPI log and report back.
Thanks for the input sofar.
WS Updated by Walter Sonius 3 days ago
- File p8h61ir2-21-cur-edk2-spilogdb-mmio123456-siooff-cbmem.rom.log p8h61ir2-21-cur-edk2-spilogdb-mmio123456-siooff-cbmem.rom.log added
- File p8h61ir2-21-cur-edk2-spilogdb-mmio123456-siooff-dmesg.log p8h61ir2-21-cur-edk2-spilogdb-mmio123456-siooff-dmesg.log added
Fixed it works on current unaltered coreboot codebase!
Although these current logs aren't exactly the same, since not all debug options are enabled otherwise some debug options conflict with edk2 smm store and blocks POST. So I also uploaded a dmesg log from the system running with your unaltered CB:91040 patch and the superio devices disabled as proof.
AP Updated by Angel Pons 3 days ago
- Related links updated (diff)
- I think the looping "resource didn't fit" thing should not be happening, as that's probably why coreboot hangs.
- On the "old" logs, you seem to be using flashconsole with SMM. I think that can cause issues so it might be a good idea to disable flashconsole in SMM.
- I see it seems to be working now. What was the actual issue?
WS Updated by Walter Sonius 3 days ago
Adding these to overridetree.cb as suggested by Patrick fixed it.
device pnp 2e.0 off end # FDC
device pnp 2e.a off end # IR