Issue Tracker

04/14/2026

PR 08:15 AM coreboot Bug #637: Sandybridge: C-States and Turbo not working in coreboot

Tests show that turbo fully works after 2 seconds. After 1 second it partly works and LZMA is 10msec faster. Patrick Rudolph

04/12/2026

PR 07:55 AM coreboot Bug #637: Sandybridge: C-States and Turbo not working in coreboot

"mwait" is working when you execute the monitor instruction first. It doesn't work without monitor, even when you not want to use it and just want the core to enter C-state.
Tested C1 and C3, but turbo is still not working within coreboot. Patrick Rudolph

04/06/2026

PR 08:02 AM coreboot Bug #637 (New): Sandybridge: C-States and Turbo not working in coreboot

Observations showed that in coreboot:
- C-States are not working (asm("mwait"); has no effect)
- Turbo states (core above P0 frequency) aren't working
The P-state can be changed after BIOS_RESET_CPL, but it never goes into turbo mod... Patrick Rudolph

PR 07:57 AM coreboot Bug #627 (Resolved): Lenovo ThinkPad X280 (20KE) only shows 4GB of RAM out of 16GB

Patrick Rudolph

PR 07:57 AM coreboot Bug #624 (Resolved): Memory speed in SMBIOS is incorrectly doubled on Haswell

Patrick Rudolph

PR 07:55 AM coreboot Feature #219 (Resolved): MMIO fw_cfg for qemu-arm

Implemented in https://review.coreboot.org/c/coreboot/+/89339 Patrick Rudolph

02/21/2026

PR 05:31 PM coreboot Bug #628: mb/asus/h61-series: variant p8h61-i_r2_0 won't POST on recent coreboot version mmio / tpm range ?

I still don't see why the mentioned commit should make any difference. Your log shows issues with I/O resources on the Super I/O.
Try disabling unused SIO LDNs:
Add this to your devicetree:
```
device pnp 2e.0 off end # FDC
devi... Patrick Rudolph

02/12/2026

PR 06:53 AM coreboot Bug #623: On T480/S, missing P-state data from ACPI tables prevents Xen from performing frequency scaling

Should be fixed by https://review.coreboot.org/c/coreboot/+/91173 Patrick Rudolph

PR 06:48 AM coreboot Bug #627: Lenovo ThinkPad X280 (20KE) only shows 4GB of RAM out of 16GB

According to the log it detects 2x "K4AAG165WB-MCRC". Maybe the capacity in the SPD file is incorrect? I don't see SPD files checked into the mainboard dir, so I cannot verify. Patrick Rudolph

02/03/2026

PR 07:14 PM coreboot Bug #623: On T480/S, missing P-state data from ACPI tables prevents Xen from performing frequency scaling

Set register "eist_enable" = "true" in devicetree.cb? Patrick Rudolph