|
*** Pre-CBMEM romstage console overflowed, log truncated! ***
|
|
|
|
[DEBUG] ECC is disabled
|
|
[DEBUG] Starting Ivy Bridge RAM training (full initialization).
|
|
[DEBUG] 100MHz reference clock support: yes
|
|
[DEBUG] PLL_REF100_CFG value: 0x2
|
|
[DEBUG] Trying CAS 11, tCK 320.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 800 MHz
|
|
[DEBUG] Selected CAS latency : 11T
|
|
[DEBUG] MPLL busy... done in 70 us
|
|
[DEBUG] MPLL frequency is set at : 800 MHz
|
|
[DEBUG] Selected CWL latency : 8T
|
|
[DEBUG] Selected tRCD : 11T
|
|
[DEBUG] Selected tRP : 11T
|
|
[DEBUG] Selected tRAS : 28T
|
|
[DEBUG] Selected tWR : 12T
|
|
[DEBUG] Selected tFAW : 24T
|
|
[DEBUG] Selected tRRD : 5T
|
|
[DEBUG] Selected tRTP : 6T
|
|
[DEBUG] Selected tWTR : 6T
|
|
[DEBUG] Selected tRFC : 208T
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 2
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 2
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] PCI(0, 0, 0)[7c] = 7f
|
|
[DEBUG] PCI(0, 0, 0)[70] = ff000000
|
|
[DEBUG] PCI(0, 0, 0)[74] = 1
|
|
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] Done jedec reset
|
|
[DEBUG] Done MRS commands
|
|
[DEBUG] t123: 1767, 6000, 6120
|
|
[NOTE ] ME: FWS2: 0x121f0172
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x1
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x1
|
|
[NOTE ] ME: MBP ready : 0x1
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x1f
|
|
[NOTE ] ME: Current PM event: 0x2
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: FWS2: 0x122c0172
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x1
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x1
|
|
[NOTE ] ME: MBP ready : 0x1
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x2c
|
|
[NOTE ] ME: Current PM event: 0x2
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: Continue to boot
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : NO
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Recovery
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean global reset
|
|
[DEBUG] ME: Progress Phase State : 0x2c
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1596 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00600010):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 4096 MB width x8 single rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] memcfg channel[1] config (00600010):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 4096 MB width x8 single rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 400000 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[INFO ] Manufacturer: ef
|
|
[INFO ] SF: Detected ef 4017 with sector size 0x1000, total 0x800000
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ffda000
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 1: 0x80300000 0x100000
|
|
[DEBUG] Subregion 2: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x3fc80 size 0x60f4 in mcache @0xfeff1060
|
|
[DEBUG] Loading module at 0x7ffcd000 with entry 0x7ffcd031. filesize: 0x5d08 memsize: 0xc058
|
|
[DEBUG] Processing 235 relocs. Offset value of 0x7dfcd000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 4 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.12-537-gc9578eac246f-dirty Thu Feb 19 19:22:37 UTC 2026 x86_32 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x1ddc0 size 0x1dca5 in mcache @0x7ffdd0bc
|
|
[DEBUG] Loading module at 0x7fe80000 with entry 0x7fe80000. filesize: 0x3c260 memsize: 0x14b490
|
|
[DEBUG] Processing 4075 relocs. Offset value of 0x7be80000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.12-537-gc9578eac246f-dirty Thu Feb 19 19:22:37 UTC 2026 x86_32 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[DEBUG] PCI: 00:00:00.0 [8086/0150] enabled
|
|
[DEBUG] PCI: 00:00:01.0 [8086/0151] enabled
|
|
[DEBUG] PCI: 00:00:02.0 [8086/0152] enabled
|
|
[DEBUG] PCI: 00:00:14.0: Disabling device
|
|
[DEBUG] PCI: 00:00:16.0 [8086/1c3a] enabled
|
|
[DEBUG] PCI: 00:00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:00:16.1 [8086/1c3b] disabled No operations
|
|
[DEBUG] PCI: 00:00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:00:16.3: Disabling device
|
|
[DEBUG] PCI: 00:00:19.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1a.0 [8086/1c2d] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/1c20] enabled
|
|
[DEBUG] PCI: 00:00:1c.0: No downstream device
|
|
[INFO ] PCH: PCIe Root Port coalescing is enabled
|
|
[DEBUG] PCI: 00:00:1c.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.0: check set enabled
|
|
[DEBUG] PCI: 00:00:1c.1: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.1: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.2: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.4: Found a downstream device
|
|
[DEBUG] PCH: Remap PCIe function 4 to 0
|
|
[DEBUG] PCI: 00:00:1c.4 [8086/1c18] enabled
|
|
[DEBUG] PCI: 00:00:1c.5: Found a downstream device
|
|
[DEBUG] PCH: Remap PCIe function 5 to 0
|
|
[DEBUG] PCI: 00:00:1c.5 [8086/1c1a] enabled
|
|
[DEBUG] PCI: 00:00:1c.6: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.7: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.7: Disabling device
|
|
[DEBUG] PCH: PCIe map 1c.0 -> 1c.5
|
|
[DEBUG] PCH: PCIe map 1c.4 -> 1c.0
|
|
[DEBUG] PCH: PCIe map 1c.5 -> 1c.4
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/1c26] enabled
|
|
[DEBUG] PCI: 00:00:1e.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.0 [8086/244e] disabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/1c5c] enabled
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/1c00] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/1c22] enabled
|
|
[DEBUG] PCI: 00:00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.5 [8086/1c08] disabled No operations
|
|
[DEBUG] PCI: 00:00:1f.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.6 [8086/1c24] disabled No operations
|
|
[DEBUG] PCI: 00:00:01.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[INFO ] PCI: 00:00:01.0: ASPM enabled L0s and L1 (no endpoint)
|
|
[INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[DEBUG] PCI: 00:02:00.0 [10ec/8168] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L1
|
|
[DEBUG] PCI: 00:02:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.4 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
|
|
[DEBUG] PCI: 00:03:00.0 [1b21/1142] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled None
|
|
[DEBUG] PCI: 00:03:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.4: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.4 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[DEBUG] PNP: 002e.0 disabled
|
|
[DEBUG] PNP: 002e.1 disabled
|
|
[DEBUG] PNP: 002e.4 enabled
|
|
[DEBUG] PNP: 002e.5 enabled
|
|
[DEBUG] PNP: 002e.6 enabled
|
|
[DEBUG] PNP: 002e.7 disabled
|
|
[DEBUG] PNP: 002e.a disabled
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 1 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms
|
|
[DEBUG] found VGA at PCI: 00:00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x27c600000 TOLUD 0x82a00000 TOM 0x200000000
|
|
[DEBUG] MEBASE 0x1ff000000
|
|
[DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 6086M
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0xff] io
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:02:00.0 20 * [0x0 - 0x3fff] prefmem
|
|
[DEBUG] PCI: 00:02:00.0 18 * [0x4000 - 0x4fff] prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:03:00.0 10 * [0x0 - 0x7fff] mem
|
|
[DEBUG] PCI: 00:00:1c.4 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base fed40000 limit fed44fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 000003f8 limit 000003ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.4 60 base 00000290 limit 00000297 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.4 62 base 00000a20 limit 00000a23 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.7 60 base 00000a00 limit 00000a00 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.7 62 base 00000a00 limit 00000a07 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: f000, Tag: 100
|
|
[DEBUG] PCI: 00:00:1c.0 1c * [0xf000 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:00:02.0 20 * [0xefc0 - 0xefff] limit: efff io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0xefa0 - 0xefbf] limit: efbf io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0xef98 - 0xef9f] limit: ef9f io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0xef90 - 0xef97] limit: ef97 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0xef8c - 0xef8f] limit: ef8f io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0xef88 - 0xef8b] limit: ef8b io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed10000 limit fed17fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed18000 limit fed18fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed19000 limit fed19fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 27c5fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 80000000 limit 829fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 02 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 04 base fed00000 limit fed00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 05 base fed20000 limit fed3ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 06 base fed45000 limit fed8ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 f0 base fed1c000 limit fed1ffff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200
|
|
[INFO ] * Base: 27c600000, Size: d83a00000, Tag: 200
|
|
[DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem
|
|
[DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem
|
|
[DEBUG] PCI: 00:00:1c.0 24 * [0xdfb00000 - 0xdfbfffff] limit: dfbfffff prefmem
|
|
[DEBUG] PCI: 00:00:1c.4 20 * [0xdfa00000 - 0xdfafffff] limit: dfafffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0xdf9fc000 - 0xdf9fffff] limit: df9fffff mem
|
|
[DEBUG] PCI: 00:00:1f.2 24 * [0xdf9fb000 - 0xdf9fb7ff] limit: df9fb7ff mem
|
|
[DEBUG] PCI: 00:00:1a.0 10 * [0xdf9fa000 - 0xdf9fa3ff] limit: df9fa3ff mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 * [0xdf9f9000 - 0xdf9f93ff] limit: df9f93ff mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 * [0xdf9f8000 - 0xdf9f80ff] limit: df9f80ff mem
|
|
[DEBUG] PCI: 00:00:16.0 10 * [0xdf9f7000 - 0xdf9f700f] limit: df9f700f mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 00:02:00.0 10 * [0xf000 - 0xf0ff] limit: f0ff io
|
|
[DEBUG] PCI: 00:02:00.0 18 * [0xdfb04000 - 0xdfb04fff] limit: dfb04fff prefmem
|
|
[DEBUG] PCI: 00:02:00.0 20 * [0xdfb00000 - 0xdfb03fff] limit: dfb03fff prefmem
|
|
[DEBUG] PCI: 00:03:00.0 10 * [0xdfa00000 - 0xdfa07fff] limit: dfa07fff mem
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000efc0 - 0x000000000000efff] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000df9f7000 - 0x00000000df9f700f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000df9fa000 - 0x00000000df9fa3ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000df9fc000 - 0x00000000df9fffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1c.0 24 <- [0x00000000dfb00000 - 0x00000000dfbfffff] size 0x00100000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PCI: 00:02:00.0 10 <- [0x000000000000f000 - 0x000000000000f0ff] size 0x00000100 gran 0x08 io
|
|
[DEBUG] PCI: 00:02:00.0 18 <- [0x00000000dfb04000 - 0x00000000dfb04fff] size 0x00001000 gran 0x0c prefmem64
|
|
[DEBUG] PCI: 00:02:00.0 20 <- [0x00000000dfb00000 - 0x00000000dfb03fff] size 0x00004000 gran 0x0e prefmem64
|
|
[DEBUG] PCI: 00:00:1c.4 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io
|
|
[DEBUG] PCI: 00:00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
|
|
[DEBUG] PCI: 00:00:1c.4 20 <- [0x00000000dfa00000 - 0x00000000dfafffff] size 0x00100000 gran 0x14 seg 00 bus 03 mem
|
|
[DEBUG] PCI: 00:03:00.0 10 <- [0x00000000dfa00000 - 0x00000000dfa07fff] size 0x00008000 gran 0x0f mem64
|
|
[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000df9f9000 - 0x00000000df9f93ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PNP: 002e.4 60 <- [0x0000000000000290 - 0x0000000000000297] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.4 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.4 62 <- [0x0000000000000a20 - 0x0000000000000a23] size 0x00000004 gran 0x02 io
|
|
[NOTE ] PNP: 002e.4 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.6 70 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ef98 - 0x000000000000ef9f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ef8c - 0x000000000000ef8f] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ef90 - 0x000000000000ef97] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ef88 - 0x000000000000ef8b] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000efa0 - 0x000000000000efbf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000df9fb000 - 0x00000000df9fb7ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000df9f8000 - 0x00000000df9f80ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:01.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:01.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:01.0 cmd <- 00
|
|
[DEBUG] PCI: 00:00:02.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:00:16.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:1a.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 1043/8415
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1c.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1c.4 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.4 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1c.4 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 1043/844d
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 00:02:00.0 cmd <- 103
|
|
[DEBUG] PCI: 00:03:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[DEBUG] microcode: sig=0x306a9 pf=0x2 revision=0x21
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x6800 in mcache @0x7ffdd02c
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0
|
|
[DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000027c5fffff size 0x17c600000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 4/4.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
|
|
[DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 2 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[INFO ] CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[DEBUG] done.
|
|
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x3 in XAPIC mode.
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[INFO ] AP: slot 2 apic_id 3, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000021
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7fea026e
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] HANDLER [0x802fb000-0x802ff847]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fac00-0x802fafff]
|
|
[DEBUG] stub0 [0x802f3000-0x802f319f]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fa800-0x802fabff]
|
|
[DEBUG] stub1 [0x802f2c00-0x802f2d9f]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fa400-0x802fa7ff]
|
|
[DEBUG] stub2 [0x802f2800-0x802f299f]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fa000-0x802fa3ff]
|
|
[DEBUG] stub3 [0x802f2400-0x802f259f]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80000fff]
|
|
[DEBUG] Loading module at 0x802fb000 with entry 0x802fbaf8. filesize: 0x46d0 memsize: 0x4848
|
|
[DEBUG] Processing 273 relocs. Offset value of 0x802fb000
|
|
[DEBUG] FMAP: area SMMSTORE found @ 410000 (262144 bytes)
|
|
[INFO ] Manufacturer: ef
|
|
[INFO ] SF: Detected ef 4017 with sector size 0x1000, total 0x800000
|
|
[DEBUG] smm store: 4 # blocks with size 0x10000
|
|
[DEBUG] Loading module at 0x802f3000 with entry 0x802f3000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x802f3000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f2c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f2800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f2400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 802f3000. Will call 0x802fbaf8
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802eb000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eac00, cpu = 1
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802eac00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ea400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea800, cpu = 2
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ea800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES NOT supported
|
|
[INFO ] CPU: TXT NOT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 00: PP0 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 3300
|
|
[INFO ] Turbo is unavailable
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #2
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES NOT supported
|
|
[INFO ] CPU: TXT NOT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] CPU: AES NOT supported
|
|
[INFO ] CPU: TXT NOT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] APIC: 03: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] APIC: 02: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[DEBUG] model_x06ax: frequency set to 3300
|
|
[INFO ] CPU #2 initialized
|
|
[INFO ] CPU: AES NOT supported
|
|
[INFO ] CPU: TXT NOT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] model_x06ax: frequency set to 3300
|
|
[INFO ] CPU #3 initialized
|
|
[INFO ] APIC: 01: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 3300
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 30 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] MTRR: TEMPORARY Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x00000000ff7fffff size 0x7f800000 type 0
|
|
[DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5
|
|
[DEBUG] 0x0000000100000000 - 0x000000027c5fffff size 0x17c600000 type 6
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 9/4.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x00000000ff800000 mask 0x0000000fff800000 type 5
|
|
[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
|
|
[DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 41 msecs
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling PEG10.
|
|
[DEBUG] Disabling Device 4.
|
|
[DEBUG] Disabling PEG60.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Disabling PEG IO clock.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 55 Watts
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 1 msecs
|
|
[DEBUG] PCI: 00:00:01.0 init
|
|
[DEBUG] PCI: 00:00:01.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:02.0 init
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x3f140 size 0x569 in mcache @0x7ffdd1e0
|
|
[INFO ] Found a VBT of 7168 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[DEBUG] IVB GT1 Power Meter Weights
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
|
|
[INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xe0000000
|
|
[DEBUG] PCI: 00:00:02.0 init finished in 113 msecs
|
|
[DEBUG] PCI: 00:00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Recovery
|
|
[DEBUG] ME: Current Operation State : M0 with UMA
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : Image Failure
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean global reset
|
|
[DEBUG] ME: Progress Phase State : M0 kernel load
|
|
[NOTE ] ME: BIOS path: Error
|
|
[DEBUG] No CMOS option 'me_state'.
|
|
[DEBUG] No CMOS option 'me_state_prev'.
|
|
[DEBUG] ME: me_state=0, me_state_prev=0
|
|
[DEBUG] PCI: 00:00:16.0: Disabling device
|
|
[DEBUG] PCI: 00:00:16.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1a.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: base = 0xdf9fc000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: initializing VIA VT1708S...
|
|
[DEBUG] azalia_audio: - vendor ID: 0x11060397
|
|
[DEBUG] azalia_audio: - subsystem ID: 0x10438415
|
|
[DEBUG] azalia_audio: - address: 0
|
|
[DEBUG] azalia_audio: done
|
|
[DEBUG] azalia_audio: initializing Intel CougarPoint HDMI...
|
|
[DEBUG] azalia_audio: - vendor ID: 0x80862805
|
|
[DEBUG] azalia_audio: - subsystem ID: 0x80860101
|
|
[DEBUG] azalia_audio: - address: 3
|
|
[DEBUG] azalia_audio: done
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.4 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.4 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected H61, device id: 0x1c5c, rev id 0x5
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources enabled.
|
|
[DEBUG] CougarPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0xdf9fb000
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 init
|
|
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:02:00.0 init
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'rt8168-macaddress' @0x3f100 size 0x11 in mcache @0x7ffdd1b4
|
|
[DEBUG] r8168: Resetting NIC...done
|
|
[DEBUG] r8168: Programming MAC Address...done
|
|
[DEBUG] PCI: 00:02:00.0 init finished in 1 msecs
|
|
[DEBUG] PCI: 00:03:00.0 init
|
|
[DEBUG] PCI: 00:03:00.0 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.4 init
|
|
[INFO ] set power 0 after power fail
|
|
[DEBUG] PNP: 002e.4 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.5 init
|
|
[DEBUG] PNP: 002e.5 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.6 init
|
|
[DEBUG] PNP: 002e.6 init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 162 / 1 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[DEBUG] apm_control: Finalizing SMM.
|
|
[DEBUG] APMC done.
|
|
[INFO ] Devices finalized
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3cd80 size 0x2341 in mcache @0x7ffdd188
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7fe2f000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] Supported C-states: C0 C1 C1E C3 C6
|
|
[DEBUG] PSS: 3300MHz power 55000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 35986 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 28563 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 21721 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 3300MHz power 55000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 35986 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 28563 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 21721 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 3300MHz power 55000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 35986 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 28563 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 21721 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 3300MHz power 55000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 35986 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 28563 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 21721 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x27c600000, len = 0xd83a00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[INFO ] \_SB.PCI0.RP01.RLTK.RLTK: Intel Series 6/7 (Cougar Point/Panther Point) Southbridge PCI: 00:02:00.0
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] current = 7fe32a10
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 14928 bytes.
|
|
[DEBUG] smbios_write_tables: 7fe27000
|
|
[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.12-537-gc9578eac246f-dirty'
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[DEBUG] SMBIOS tables: 1004 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 4ff9
|
|
[DEBUG] Writing coreboot table at 0x7fe53000
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'cmos_layout.bin' @0x3f840 size 0x3f0 in mcache @0x7ffdd238
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000007fe26fff: RAM
|
|
[DEBUG] 6. 000000007fe27000-000000007fe7ffff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007fe80000-000000007ffcbfff: RAMSTAGE
|
|
[DEBUG] 8. 000000007ffcc000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 0000000080000000-00000000829fffff: RESERVED
|
|
[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 11. 00000000fec00000-00000000fec00fff: RESERVED
|
|
[DEBUG] 12. 00000000fed00000-00000000fed00fff: RESERVED
|
|
[DEBUG] 13. 00000000fed10000-00000000fed19fff: RESERVED
|
|
[DEBUG] 14. 00000000fed1c000-00000000fed3ffff: RESERVED
|
|
[DEBUG] 15. 00000000fed45000-00000000fed8ffff: RESERVED
|
|
[DEBUG] 16. 00000000ff000000-00000000ffffffff: RESERVED
|
|
[DEBUG] 17. 0000000100000000-000000027c5fffff: RAM
|
|
[DEBUG] FMAP: area SMMSTORE found @ 410000 (262144 bytes)
|
|
[DEBUG] smm store: 4 # blocks with size 0x10000
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] Wrote coreboot table at: 0x7fe53000, 0x880 bytes, checksum b2ab
|
|
[DEBUG] coreboot table: 2200 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
|
|
[DEBUG] RO MCACHE 3. 0x7ffdd000 0x00000314
|
|
[DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910
|
|
[DEBUG] MEM INFO 5. 0x7ffda000 0x000010c8
|
|
[DEBUG] AFTER CAR 6. 0x7ffcc000 0x0000e000
|
|
[DEBUG] RAMSTAGE 7. 0x7fe7f000 0x0014d000
|
|
[DEBUG] SMM BACKUP 8. 0x7fe6f000 0x00010000
|
|
[DEBUG] SMM COMBUFFER 9. 0x7fe5f000 0x00010000
|
|
[DEBUG] IGD OPREGION10. 0x7fe5b000 0x00003200
|
|
[DEBUG] COREBOOT 11. 0x7fe53000 0x00008000
|
|
[DEBUG] ACPI 12. 0x7fe2f000 0x00024000
|
|
[DEBUG] SMBIOS 13. 0x7fe27000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7fffeae0 0x0000010a
|
|
[DEBUG] ROMSTAGE 2. 0x7fffeac0 0x00000004
|
|
[DEBUG] ROMSTG STCK 3. 0x7fffea00 0x000000a8
|
|
[DEBUG] ACPI GNVS 4. 0x7fffe900 0x00000100
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 0 ms
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x45dc0 size 0x1e73e6 in mcache @0x7ffdd2a4
|
|
[DEBUG] Checking segment from ROM address 0xffc96dec
|
|
[DEBUG] Checking segment from ROM address 0xffc96e08
|
|
[DEBUG] Loading segment from ROM address 0xffc96dec
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffc96e24 filesize 0x1e73ae
|
|
[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000001e73ae
|
|
[DEBUG] using LZMA
|
|
[DEBUG] Loading segment from ROM address 0xffc96e08
|
|
[DEBUG] Entry Point 0x008022a7
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 606 / 0 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x008022a7(0x7fe53000)
|