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Bug #565

open

Wifi card not recognized (not enumerated) at all, Lenovo M700 tiny

Added by Vittorio Mori about 2 months ago. Updated about 1 month ago.

Status:
New
Priority:
Normal
Assignee:
-
Category:
board support
Target version:
Start date:
10/03/2024
Due date:
% Done:

0%

Estimated time:
Affected versions:
Needs backport to:
Affected hardware:
Lenovo M700 tiny
Affected OS:
ANY

Description

Hello, I've compiled coreboot for my Lenovo M700 Tiny, to have other processor support (Kaby Lake/Coffee Lake).

The ed2k payload works correctly, I can successfully boot a Kaby Lake and Coffee lake CPU with Coreboot (original Lenovo BIOS is Skylake-only).

I report two annoying issues:

  • wif card pci-e slot is not working, the card is not enumerated at all. ASPM on or off, no difference (with ASPM ON I get continous AER errors in dmesg on Linux). With original OEM BIOS the wifi (Intel 8260 wifi5 chipset) 100% works. On coreboot I get only the bluetooth part working (I know it's on the USB bus, so I think it's normal).

  • I use libgfxinit for graphics part: works correctly at boot, Linux booting always OK, but Windows 11 fails to initialize the displayport output i.e. it gets TURNED OFF for some reason when windows starts. I have to unplug and plug the cable back to have display back ON. This also does not happen with original OEM firmware. Maybe I must use a GOP ? I could not find a clear guide on how to compile/initialize coreboot w GOP into coreboot. Maybe I can run it into an .efi binary (I have all .efi GOPs somewhere..) ?

Here is the cbmem log:

`[NOTE ] coreboot-24.08-272-g735ca7f24ad4 Tue Sep 24 05:19:22 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG] CPU: Intel(R) Core(TM) i3-7100 CPU @ 3.90GHz
[DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f7
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported
[DEBUG] MCH: device id 590f (rev 06) is Kabylake-S
[DEBUG] PCH: device id a148 (rev 31) is B150
[DEBUG] IGD: device id 5912 (rev 04) is Kaby Lake DT GT2
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x850000.
[DEBUG] FMAP: base = 0xff000000 size = 0x1000000 #areas = 8
[DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes)
[INFO ] CBFS: mcache @0xfef04f00 built for 16 files, used 0x364 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x9d1c0 size 0xb9a0 in mcache @0xfef04f8c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 78 ms

[NOTE ] coreboot-24.08-272-g735ca7f24ad4 Tue Sep 24 05:19:22 UTC 2024 x86_32 romstage starting (log level: 7)...
[DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000
[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG] gpe0_sts[3]: 00000002 gpe0_en[3]: 00000000
[DEBUG] TCO_STS: 0000 0001
[DEBUG] GEN_PMCON: e0850200 00001808
[DEBUG] GBLRST_CAUSE: 00000400 00010001
[DEBUG] prev_sleep_state 0 (S0)
[DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes)
[INFO ] CBFS: Found 'fspm.bin' @0xcadc0 size 0x63000 in mcache @0xfef0513c
[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
[DEBUG] SPD @ 0x50
[INFO ] SPD: module type is DDR4
[INFO ] SPD: module part number is 4ATF51264HZ-2G3E2

[INFO ] SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
[INFO ] SPD: device width 16 bits, bus width 64 bits
[INFO ] SPD: module size is 4096 MB (per channel)
[DEBUG] SPD @ 0x52
[INFO ] SPD: module type is DDR4
[INFO ] SPD: module part number is 4ATF51264HZ-2G3E2

[INFO ] SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
[INFO ] SPD: device width 16 bits, bus width 64 bits
[INFO ] SPD: module size is 4096 MB (per channel)
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x7afff000 254 entries.
[DEBUG] IMD: root @ 0x7affec00 62 entries.
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x7b3ff000 254 entries.
[DEBUG] IMD: root @ 0x7b3fec00 62 entries.
[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG] 2 DIMMs found
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x7b000000 0x800000
[DEBUG] Subregion 0: 0x7b000000 0x200000
[DEBUG] Subregion 1: 0x7b200000 0x200000
[DEBUG] Subregion 2: 0x7b400000 0x400000
[DEBUG] top_of_ram = 0x7b000000
[DEBUG] Normal boot
[INFO ] CBFS: Found 'fallback/postcar' @0x151e40 size 0x6808 in mcache @0xfef051b0
[DEBUG] Loading module at 0x7abce000 with entry 0x7abce031. filesize: 0x6208 memsize: 0xc5a0
[DEBUG] Processing 368 relocs. Offset value of 0x78bce000
[DEBUG] BS: romstage times (exec / console): total (unknown) / 226 ms

[NOTE ] coreboot-24.08-272-g735ca7f24ad4 Tue Sep 24 05:19:22 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes)
[INFO ] CBFS: Found 'fallback/ramstage' @0xa8bc0 size 0x1d278 in mcache @0x7abdc0ec
[DEBUG] Loading module at 0x7aa7f000 with entry 0x7aa7f000. filesize: 0x3a428 memsize: 0x14d908
[DEBUG] Processing 4860 relocs. Offset value of 0x76a7f000
[DEBUG] BS: postcar times (exec / console): total (unknown) / 43 ms

[NOTE ] coreboot-24.08-272-g735ca7f24ad4 Tue Sep 24 05:19:22 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] microcode: sig=0x906e9 pf=0x2 revision=0xf7
[DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes)
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x9d000 in mcache @0x7abdc02c
[DEBUG] Skip microcode update
[INFO ] CBFS: Found 'fsps.bin' @0x12de00 size 0x23ff2 in mcache @0x7abdc27c
[DEBUG] Detected 2 core, 4 thread CPU.
[DEBUG] Setting up SMI for CPU
[DEBUG] IED base = 0x7b400000
[DEBUG] IED size = 0x00400000
[INFO ] Will perform SMM setup.
[INFO ] CPU: Intel(R) Core(TM) i3-7100 CPU @ 3.90GHz.
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] CPU: APIC: 00 enabled
[DEBUG] CPU: APIC: 01 enabled
[DEBUG] CPU: APIC: 02 enabled
[DEBUG] CPU: APIC: 03 enabled
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[INFO ] LAPIC 0x1 in XAPIC mode.
[DEBUG] done.
[INFO ] AP: slot 3 apic_id 1, MCU rev: 0x000000f7
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x3 in XAPIC mode.
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] AP: slot 1 apic_id 3, MCU rev: 0x000000f7
[INFO ] AP: slot 2 apic_id 2, MCU rev: 0x000000f7
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b0 memsize: 0x1b0
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
[DEBUG] smm_module_setup_stub: stack_top = 0x7b002000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7aa98de3
[DEBUG] Installing permanent SMM handler to 0x7b000000
[DEBUG] HANDLER [0x7b1fe000-0x7b1ffe8f]

[DEBUG] CPU 0
[DEBUG] ss0 [0x7b1fdc00-0x7b1fdfff]
[DEBUG] stub0 [0x7b1f6000-0x7b1f61af]

[DEBUG] CPU 1
[DEBUG] ss1 [0x7b1fd800-0x7b1fdbff]
[DEBUG] stub1 [0x7b1f5c00-0x7b1f5daf]

[DEBUG] CPU 2
[DEBUG] ss2 [0x7b1fd400-0x7b1fd7ff]
[DEBUG] stub2 [0x7b1f5800-0x7b1f59af]

[DEBUG] CPU 3
[DEBUG] ss3 [0x7b1fd000-0x7b1fd3ff]
[DEBUG] stub3 [0x7b1f5400-0x7b1f55af]

[DEBUG] stacks [0x7b000000-0x7b001fff]
[DEBUG] Loading module at 0x7b1fe000 with entry 0x7b1ff81b. filesize: 0x1db0 memsize: 0x1e90
[DEBUG] Processing 149 relocs. Offset value of 0x7b1fe000
[DEBUG] FMAP: area SMMSTORE found @ 810000 (262144 bytes)
[DEBUG] smm store: 4 # blocks with size 0x10000
[DEBUG] Loading module at 0x7b1f6000 with entry 0x7b1f6000. filesize: 0x1b0 memsize: 0x1b0
[DEBUG] Processing 9 relocs. Offset value of 0x7b1f6000
[DEBUG] smm_module_setup_stub: stack_top = 0x7b002000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG] SMM Module: placing smm entry code at 7b1f5c00, cpu # 0x1
[DEBUG] SMM Module: placing smm entry code at 7b1f5800, cpu # 0x2
[DEBUG] SMM Module: placing smm entry code at 7b1f5400, cpu # 0x3
[DEBUG] SMM Module: stub loaded at 7b1f6000. Will call 0x7b1ff81b
[DEBUG] Clearing SMI status registers
[DEBUG] TCO_STS: INTRD_DET
[DEBUG] GPE0 STD STS: HOTPLUG
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ee000, cpu = 0
[DEBUG] In relocation handler: CPU 0
[DEBUG] New SMBASE=0x7b1ee000 IEDBASE=0x7b400000
[DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ed800, cpu = 2
[DEBUG] In relocation handler: CPU 2
[DEBUG] New SMBASE=0x7b1ed800 IEDBASE=0x7b400000
[DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1edc00, cpu = 1
[DEBUG] In relocation handler: CPU 1
[DEBUG] New SMBASE=0x7b1edc00 IEDBASE=0x7b400000
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ed400, cpu = 3
[DEBUG] In relocation handler: CPU 3
[DEBUG] New SMBASE=0x7b1ed400 IEDBASE=0x7b400000
[DEBUG] Relocation complete.
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[INFO ] Turbo is unavailable
[DEBUG] Skip microcode update
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #3
[INFO ] Initializing CPU #1
[INFO ] Initializing CPU #2
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #1 initialized
[DEBUG] Skip microcode update
[INFO ] CPU #2 initialized
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #3 initialized
[INFO ] bsp_do_flight_plan done after 420 msecs.
[DEBUG] Enabling SMIs.
[DEBUG] Locking SMM.
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 204 / 381 ms
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] WEAK: src/soc/intel/skylake/chip.c/mainboard_silicon_init_params called
[INFO ] FSPS, status=0x00000000
[INFO ] ITSS IRQ Polarities Before:
[INFO ] IPC0: 0x00ff4000
[INFO ] IPC1: 0x00000007
[INFO ] IPC2: 0x00000000
[INFO ] IPC3: 0x00000000
[INFO ] ITSS IRQ Polarities After:
[INFO ] IPC0: 0x00ff4000
[INFO ] IPC1: 0x00000007
[INFO ] IPC2: 0x00000000
[INFO ] IPC3: 0x00000000
[INFO ] Found PCIe Root Port #7 at PCI: 00:1c.0.
[NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #17 (originally PCI: 00:00:1b.0) which was enabled in devicetree, removing and disabling.
[INFO ] Remapping PCIe Root Port #7 from PCI: 00:00:1c.6 to new function number 0.
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 56 / 73 ms
[INFO ] Enumerating buses...
[INFO ] Board ID: ThinkCentre M700 Tiny
[INFO ] Serial header unpopulated
[INFO ] PS/2 header unpopulated
[INFO ] USB header unpopulated
[INFO ] DisplayPort header populated
[INFO ] PCIe / SATA header unpopulated
[DEBUG] Root Device scanning...
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 00000000 enabled
[DEBUG] DOMAIN: 00000000 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG] PCI: 00:00:00.0 [8086/590f] enabled
[DEBUG] PCI: 00:00:02.0 [8086/5912] enabled
[DEBUG] PCI: 00:00:04.0 [8086/1903] enabled
[DEBUG] PCI: 00:00:08.0 [8086/1911] enabled
[DEBUG] PCI: 00:00:14.0 [8086/a12f] enabled
[DEBUG] PCI: 00:00:14.2 [8086/a131] enabled
[DEBUG] PCI: 00:00:16.0 [8086/a13a] enabled
[DEBUG] PCI: 00:00:17.0 [8086/a102] enabled
[DEBUG] PCI: 00:00:19.0 [8086/a166] disabled
[DEBUG] PCI: 00:00:1c.0 [8086/a116] enabled
[DEBUG] PCI: 00:00:1f.0 [8086/a148] enabled
[DEBUG] PCI: 00:00:1f.1 [8086/a120] enabled
[DEBUG] PCI: 00:00:1f.2 [8086/a121] enabled
[DEBUG] PCI: 00:00:1f.3 [8086/a170] enabled
[DEBUG] PCI: 00:00:1f.4 [8086/a123] enabled
[DEBUG] PCI: 00:00:1f.6 [8086/15b8] enabled
[DEBUG] GPIO: 0 enabled
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:00:01.0
[WARN ] PCI: 00:00:01.1
[WARN ] PCI: 00:00:01.2
[WARN ] PCI: 00:00:05.0
[WARN ] PCI: 00:00:07.0
[WARN ] PCI: 00:00:13.0
[WARN ] PCI: 00:00:14.1
[WARN ] PCI: 00:00:14.3
[WARN ] PCI: 00:00:15.0
[WARN ] PCI: 00:00:15.1
[WARN ] PCI: 00:00:15.2
[WARN ] PCI: 00:00:15.3
[WARN ] PCI: 00:00:16.1
[WARN ] PCI: 00:00:16.2
[WARN ] PCI: 00:00:16.3
[WARN ] PCI: 00:00:16.4
[WARN ] PCI: 00:00:19.1
[WARN ] PCI: 00:00:19.2
[WARN ] PCI: 00:00:1e.0
[WARN ] PCI: 00:00:1e.1
[WARN ] PCI: 00:00:1e.2
[WARN ] PCI: 00:00:1e.3
[WARN ] PCI: 00:00:1e.4
[WARN ] PCI: 00:00:1e.5
[WARN ] PCI: 00:00:1e.6
[WARN ] PCI: 00:00:1f.5
[WARN ] PCI: 00:00:1f.7
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] PCI: 00:00:02.0 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs
[DEBUG] PCI: 00:00:14.0 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs
[DEBUG] PCI: 00:00:1c.0 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG] GENERIC: 0.0 enabled
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 18 msecs
[DEBUG] PCI: 00:00:1f.0 scanning...
[DEBUG] PNP: 002e.1 disabled
[DEBUG] PNP: 002e.2 enabled
[DEBUG] PNP: 002e.3 disabled
[DEBUG] PNP: 002e.5 disabled
[DEBUG] PNP: 002e.6 disabled
[DEBUG] PNP: 002e.7 disabled
[DEBUG] PNP: 002e.8 disabled
[DEBUG] PNP: 002e.9 disabled
[DEBUG] PNP: 002e.a enabled
[DEBUG] PNP: 002e.b enabled
[DEBUG] PNP: 002e.c disabled
[DEBUG] PNP: 002e.d disabled
[DEBUG] PNP: 002e.e enabled
[DEBUG] PNP: 002e.f disabled
[INFO ] Found TPM 1.2 NPCT420AA V2 (0x00fe) by Nuvoton (0x1050)
[DEBUG] PNP: 0c31.0 enabled
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 59 msecs
[DEBUG] PCI: 00:00:1f.2 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs
[DEBUG] PCI: 00:00:1f.3 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
[DEBUG] PCI: 00:00:1f.4 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 0 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 336 msecs
[DEBUG] scan_bus: bus Root Device finished in 354 msecs
[INFO ] done
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 391 ms
[INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
[INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 18 ms
[DEBUG] found VGA at PCI: 00:00:02.0
[DEBUG] Setting up VGA for PCI: 00:00:02.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ] Allocating resources...
[INFO ] Reading resources...
[DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000
[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000
[DEBUG] SA MMIO resource: DMIBAR -> base = 0xfed18000, size = 0x00001000
[DEBUG] SA MMIO resource: EPBAR -> base = 0xfed19000, size = 0x00001000
[DEBUG] SA MMIO resource: GDXCBAR -> base = 0xfed84000, size = 0x00001000
[DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
[DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000
[DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000
[INFO ] Available memory above 4GB: 6112M
[INFO ] Done reading resources.
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000080 limit 0000008f io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.a 60 base 00000a10 limit 00000a17 io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.b 60 base 00000a20 limit 00000a27 io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 40 base 00001800 limit 000018ff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
[INFO ] DOMAIN: 00000000: Resource ranges:
[INFO ] * Base: 1000, Size: 800, Tag: 100
[INFO ] * Base: 1900, Size: d6a0, Tag: 100
[INFO ] * Base: efc0, Size: 1040, Tag: 100
[DEBUG] PCI: 00:00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
[DEBUG] PCI: 00:00:17.0 20 * [0x1040 - 0x105f] limit: 105f io
[DEBUG] PCI: 00:00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io
[DEBUG] PCI: 00:00:17.0 1c * [0x1068 - 0x106b] limit: 106b io
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base e0000000 limit efffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed10000 limit fed17fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base fed18000 limit fed18fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed19000 limit fed19fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed84000 limit fed84fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed91000 limit fed91fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 7b000000 limit 7fffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 100000000 limit 27dffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
[DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 48 base fe000000 limit fe00ffff mem (fixed)
[INFO ] DOMAIN: 00000000: Resource ranges:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200
[INFO ] * Base: 27e000000, Size: 7d82000000, Tag: 200
[DEBUG] PCI: 00:00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
[DEBUG] PCI: 00:00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
[DEBUG] PCI: 00:00:1f.6 10 * [0x91000000 - 0x9101ffff] limit: 9101ffff mem
[DEBUG] PCI: 00:00:14.0 10 * [0x91020000 - 0x9102ffff] limit: 9102ffff mem
[DEBUG] PCI: 00:00:1f.3 20 * [0x91030000 - 0x9103ffff] limit: 9103ffff mem
[DEBUG] PCI: 00:00:04.0 10 * [0x91040000 - 0x91047fff] limit: 91047fff mem
[DEBUG] PCI: 00:00:1f.2 10 * [0x91048000 - 0x9104bfff] limit: 9104bfff mem
[DEBUG] PCI: 00:00:1f.3 10 * [0x9104c000 - 0x9104ffff] limit: 9104ffff mem
[DEBUG] PCI: 00:00:17.0 10 * [0x91050000 - 0x91051fff] limit: 91051fff mem
[DEBUG] PCI: 00:00:08.0 10 * [0x91052000 - 0x91052fff] limit: 91052fff mem
[DEBUG] PCI: 00:00:14.2 10 * [0x91053000 - 0x91053fff] limit: 91053fff mem
[DEBUG] PCI: 00:00:16.0 10 * [0x91054000 - 0x91054fff] limit: 91054fff mem
[DEBUG] PCI: 00:00:17.0 24 * [0x91055000 - 0x910557ff] limit: 910557ff mem
[DEBUG] PCI: 00:00:17.0 14 * [0x91056000 - 0x910560ff] limit: 910560ff mem
[DEBUG] PCI: 00:00:1f.4 10 * [0x91057000 - 0x910570ff] limit: 910570ff mem
[DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff done
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
[DEBUG] PCI: 00:00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64
[DEBUG] PCI: 00:00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 00:00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
[DEBUG] PCI: 00:00:04.0 10 <- [0x0000000091040000 - 0x0000000091047fff] size 0x00008000 gran 0x0f mem64
[DEBUG] PCI: 00:00:08.0 10 <- [0x0000000091052000 - 0x0000000091052fff] size 0x00001000 gran 0x0c mem64
[DEBUG] PCI: 00:00:14.0 10 <- [0x0000000091020000 - 0x000000009102ffff] size 0x00010000 gran 0x10 mem64
[DEBUG] PCI: 00:00:14.2 10 <- [0x0000000091053000 - 0x0000000091053fff] size 0x00001000 gran 0x0c mem64
[DEBUG] PCI: 00:00:16.0 10 <- [0x0000000091054000 - 0x0000000091054fff] size 0x00001000 gran 0x0c mem64
[DEBUG] PCI: 00:00:17.0 10 <- [0x0000000091050000 - 0x0000000091051fff] size 0x00002000 gran 0x0d mem
[DEBUG] PCI: 00:00:17.0 14 <- [0x0000000091056000 - 0x00000000910560ff] size 0x00000100 gran 0x08 mem
[DEBUG] PCI: 00:00:17.0 18 <- [0x0000000000001060 - 0x0000000000001067] size 0x00000008 gran 0x03 io
[DEBUG] PCI: 00:00:17.0 1c <- [0x0000000000001068 - 0x000000000000106b] size 0x00000004 gran 0x02 io
[DEBUG] PCI: 00:00:17.0 20 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
[DEBUG] PCI: 00:00:17.0 24 <- [0x0000000091055000 - 0x00000000910557ff] size 0x00000800 gran 0x0b mem
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bumem
[DEBUG] PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
[DEBUG] PNP: 002e.2 70 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 irq
[NOTE ] PNP: 002e.2 f0 irq size: 0x0000000001 not assigned in devicetree
[DEBUG] PNP: 002e.a 60 <- [0x0000000000000a10 - 0x0000000000000a17] size 0x00000008 gran 0x03 io
[NOTE ] PNP: 002e.a 70 irq size: 0x0000000001 not assigned in devicetree
[DEBUG] PNP: 002e.b 60 <- [0x0000000000000a20 - 0x0000000000000a27] size 0x00000008 gran 0x03 io
[NOTE ] PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree
[DEBUG] PNP: 002e.e e4 <- [0x0000000000000010 - 0x000000000000000f] size 0x00000000 gran 0x00 irq
[DEBUG] PNP: 002e.e e5 <- [0x0000000000000009 - 0x0000000000000008] size 0x00000000 gran 0x00 irq
[DEBUG] LPC: enabling default decode range LPC_IOE_COMA_EN
[DEBUG] LPC: Opened IO window LGIR1: base a10 size 8
[DEBUG] LPC: Opened IO window LGIR2: base a20 size 8
[DEBUG] PCI: 00:00:1f.2 10 <- [0x0000000091048000 - 0x000000009104bfff] size 0x00004000 gran 0x0e mem
[DEBUG] PCI: 00:00:1f.3 10 <- [0x000000009104c000 - 0x000000009104ffff] size 0x00004000 gran 0x0e mem64
[DEBUG] PCI: 00:00:1f.3 20 <- [0x0000000091030000 - 0x000000009103ffff] size 0x00010000 gran 0x10 mem64
[DEBUG] PCI: 00:00:1f.4 10 <- [0x0000000091057000 - 0x00000000910570ff] size 0x00000100 gran 0x08 mem64
[DEBUG] PCI: 00:00:1f.6 10 <- [0x0000000091000000 - 0x000000009101ffff] size 0x00020000 gran 0x11 mem
[INFO ] Done setting resources.
[INFO ] Done allocating resources.
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 961 ms
[INFO ] Enabling resources...
[DEBUG] PCI: 00:00:00.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:00.0 cmd <- 06
[DEBUG] PCI: 00:00:02.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:02.0 cmd <- 03
[DEBUG] PCI: 00:00:04.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:04.0 cmd <- 02
[DEBUG] PCI: 00:00:08.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:08.0 cmd <- 06
[DEBUG] PCI: 00:00:14.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:14.0 cmd <- 02
[DEBUG] PCI: 00:00:14.2 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:14.2 cmd <- 02
[DEBUG] PCI: 00:00:16.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:16.0 cmd <- 02
[DEBUG] PCI: 00:00:17.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:17.0 cmd <- 03
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
[DEBUG] PCI: 00:00:1c.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:1c.0 cmd <- 00
[DEBUG] PCI: 00:00:1f.0 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:1f.0 cmd <- 07
[DEBUG] PCI: 00:00:1f.2 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:1f.2 cmd <- 06
[DEBUG] PCI: 00:00:1f.3 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:1f.3 cmd <- 02
[DEBUG] PCI: 00:00:1f.4 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:1f.4 cmd <- 03
[DEBUG] PCI: 00:00:1f.6 subsystem <- 17aa/30d0
[DEBUG] PCI: 00:00:1f.6 cmd <- 02
[INFO ] done.
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 139 ms
[DEBUG] ME: Version: 11.0.2.1003
[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 37 / 4 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[INFO ] CPU TDP = 51 Watts
[INFO ] CPU PL1 = 51 Watts
[INFO ] CPU PL2 = 65 Watts
[DEBUG] PCI: 00:00:00.0 init finished in 10 msecs
[DEBUG] PCI: 00:00:02.0 init
[INFO ] CBFS: Found 'vbt.bin' @0xca340 size 0x47e in mcache @0x7abdc1e4
[INFO ] Found a VBT of 4608 bytes
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
[INFO ] x_res x y_res: 1920 x 1200, size: 9216000 at 0x80000000
[DEBUG] PCI: 00:00:02.0 init finished in 178 msecs
[DEBUG] PCI: 00:00:04.0 init
[DEBUG] PCI: 00:00:04.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:08.0 init
[DEBUG] PCI: 00:00:08.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:14.0 init
[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:14.2 init
[DEBUG] PCI: 00:00:14.2 init finished in 0 msecs
[DEBUG] PCI: 00:00:16.0 init
[DEBUG] PCI: 00:00:16.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:1c.0 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs
[DEBUG] PCI: 00:00:1f.0 init
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
[DEBUG] IOAPIC: ID = 0x00
[DEBUG] IOAPIC: 120 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
[DEBUG] PCI: 00:00:1f.0 init finished in 23 msecs
[DEBUG] PCI: 00:00:1f.2 init
[DEBUG] RTC Init
[INFO ] Set power on after power failure.
[DEBUG] apm_control: Disabling ACPI.
[DEBUG] APMC done.
[DEBUG] Disabling Deep S3
[DEBUG] Disabling Deep S3
[DEBUG] Enabling Deep S4
[DEBUG] Enabling Deep S4
[DEBUG] Enabling Deep S5
[DEBUG] Enabling Deep S5
[DEBUG] PCI: 00:00:1f.2 init finished in 35 msecs
[DEBUG] PCI: 00:00:1f.3 init
[DEBUG] azalia_audio: base = 0x9104c000
[DEBUG] azalia_audio: codec_mask = 0x06
[DEBUG] azalia_audio: initializing codec #2...
[DEBUG] azalia_audio: - vendor/device id: 0x8086280b
[DEBUG] azalia_audio: - no verb!
[DEBUG] azalia_audio: initializing codec #1...
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0233
[DEBUG] azalia_audio: - verb size: 44
[DEBUG] azalia_audio: - verb loaded
[DEBUG] PCI: 00:00:1f.3 init finished in 48 msecs
[DEBUG] PCI: 00:00:1f.4 init
[DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs
[DEBUG] PCI: 00:00:1f.6 init
[DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs
[DEBUG] PNP: 002e.2 init
[DEBUG] PNP: 002e.2 init finished in 0 msecs
[DEBUG] PNP: 002e.a init
[INFO ] set power on after power fail
[DEBUG] PNP: 002e.a init finished in 5 msecs
[DEBUG] PNP: 002e.b init
[DEBUG] PNP: 002e.b init finished in 0 msecs
[DEBUG] PNP: 002e.e init
[DEBUG] PNP: 002e.e init finished in 0 msecs
[INFO ] Devices initialized
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 155 / 307 ms
[DEBUG] TPM: Startup
[DEBUG] TPM: command 0x99 returned 0x0
[DEBUG] TPM: Asserting physical presence
[DEBUG] TPM: command 0x4000000a returned 0x0
[DEBUG] TPM: command 0x65 returned 0x0
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
[INFO ] TPM: setup succeeded
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 3 / 31 ms
[INFO ] Finalize devices...
[DEBUG] PCI: 00:00:02.0 final
[DEBUG] PCI: 00:00:16.0 final
[DEBUG] PCI: 00:00:17.0 final
[DEBUG] PCI: 00:00:1f.2 final
[DEBUG] PCI: 00:00:1f.4 final
[INFO ] Devices finalized
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 25 ms
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0xc73c0 size 0x2f48 in mcache @0x7abdc1b8
[WARN ] CBFS: 'fallback/slic' not found.
[INFO ] ACPI: Writing ACPI tables at 7aa00000.
[DEBUG] ACPI: * FACS
[DEBUG] SCI is IRQ 9, GSI 9
[DEBUG] ACPI: * FACP
[DEBUG] ACPI: added table 1/32, length now 44
[DEBUG] Found 1 CPU(s) with 2/4 physical/logical core(s) each.
[DEBUG] PSS: 3900MHz power 51000 control 0x2700 status 0x2700
[DEBUG] PSS: 3800MHz power 49077 control 0x2600 status 0x2600
[DEBUG] PSS: 3300MHz power 40212 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 32105 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2300MHz power 24812 control 0x1700 status 0x1700
[DEBUG] PSS: 1800MHz power 18221 control 0x1200 status 0x1200
[DEBUG] PSS: 1300MHz power 12329 control 0xd00 status 0xd00
[DEBUG] PSS: 800MHz power 7088 control 0x800 status 0x800
[DEBUG] PSS: 3900MHz power 51000 control 0x2700 status 0x2700
[DEBUG] PSS: 3800MHz power 49077 control 0x2600 status 0x2600
[DEBUG] PSS: 3300MHz power 40212 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 32105 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2300MHz power 24812 control 0x1700 status 0x1700
[DEBUG] PSS: 1800MHz power 18221 control 0x1200 status 0x1200
[DEBUG] PSS: 1300MHz power 12329 control 0xd00 status 0xd00
[DEBUG] PSS: 800MHz power 7088 control 0x800 status 0x800
[DEBUG] PSS: 3900MHz power 51000 control 0x2700 status 0x2700
[DEBUG] PSS: 3800MHz power 49077 control 0x2600 status 0x2600
[DEBUG] PSS: 3300MHz power 40212 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 32105 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2300MHz power 24812 control 0x1700 status 0x1700
[DEBUG] PSS: 1800MHz power 18221 control 0x1200 status 0x1200
[DEBUG] PSS: 1300MHz power 12329 control 0xd00 status 0xd00
[DEBUG] PSS: 800MHz power 7088 control 0x800 status 0x800
[DEBUG] PSS: 3900MHz power 51000 control 0x2700 status 0x2700
[DEBUG] PSS: 3800MHz power 49077 control 0x2600 status 0x2600
[DEBUG] PSS: 3300MHz power 40212 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 32105 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2300MHz power 24812 control 0x1700 status 0x1700
[DEBUG] PSS: 1800MHz power 18221 control 0x1200 status 0x1200
[DEBUG] PSS: 1300MHz power 12329 control 0xd00 status 0xd00
[DEBUG] PSS: 800MHz power 7088 control 0x800 status 0x800
[DEBUG] PCI space above 4GB MMIO is at 0x27e000000, len = 0x7d82000000
[DEBUG] Empty min sleep state array returned
[INFO ] Returning default LPI constraint package
[INFO ] _SB.PCI0.PEPD: Intel Power Engine Plug-in
[INFO ] _SB.PCI0.RP01: WIFI Device GENERIC: 0.0
[DEBUG] PPI: Pending OS request: 0x78c18f7c (0x68f0031f)
[DEBUG] PPI: OS response: CMD 0x7081873c = 0x60f0021f
[INFO ] _SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
[DEBUG] ACPI: * SSDT
[DEBUG] ACPI: added table 2/32, length now 52
[DEBUG] ACPI: * MCFG
[DEBUG] ACPI: added table 3/32, length now 60
[DEBUG] TCPA log created at 0x7a9f0000
[DEBUG] ACPI: * TCPA
[DEBUG] ACPI: added table 4/32, length now 68
[DEBUG] ACPI: * LPIT
[DEBUG] ACPI: added table 5/32, length now 76
[DEBUG] IOAPIC: 120 interrupts
[DEBUG] SCI is IRQ 9, GSI 9
[DEBUG] ACPI: * APIC
[DEBUG] ACPI: added table 6/32, length now 84
[DEBUG] ACPI: * SPCR
[DEBUG] ACPI: added table 7/32, length now 92
[DEBUG] current = 7aa047b0
[DEBUG] ACPI: * DMAR
[DEBUG] ACPI: added table 8/32, length now 100
[DEBUG] acpi_write_dbg2_pci_uart: Device not found
[DEBUG] ACPI: * HPET
[DEBUG] ACPI: added table 9/32, length now 108
[INFO ] ACPI: done.
[DEBUG] ACPI tables: 18560 bytes.
[DEBUG] smbios_write_tables: 7a9e8000
[DEBUG] SMBIOS firmware version is set to coreboot_version: '24.08-272-g735ca7f24ad4'
[INFO ] Create SMBIOS type 16
[INFO ] Create SMBIOS type 17
[INFO ] Create SMBIOS type 20
[INFO ] GENERIC: 0.0 (WIFI Device)
[DEBUG] SMBIOS tables: 1075 bytes.
[DEBUG] Writing table forward entry at 0x00000500
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 453c
[DEBUG] Writing coreboot table at 0x7aa24000
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG] 3. 0000000000100000-000000007a9e7fff: RAM
[DEBUG] 4. 000000007a9e8000-000000007aa7efff: CONFIGURATION TABLES
[DEBUG] 5. 000000007aa7f000-000000007abccfff: RAMSTAGE
[DEBUG] 6. 000000007abcd000-000000007affffff: CONFIGURATION TABLES
[DEBUG] 7. 000000007b000000-000000007fffffff: RESERVED
[DEBUG] 8. 00000000e0000000-00000000efffffff: RESERVED
[DEBUG] 9. 00000000fd000000-00000000fe00ffff: RESERVED
[DEBUG] 10. 00000000fed10000-00000000fed19fff: RESERVED
[DEBUG] 11. 00000000fed40000-00000000fed44fff: RESERVED
[DEBUG] 12. 00000000fed80000-00000000fed84fff: RESERVED
[DEBUG] 13. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG] 14. 0000000100000000-000000027dffffff: RAM
[DEBUG] FMAP: area SMMSTORE found @ 810000 (262144 bytes)
[DEBUG] smm store: 4 # blocks with size 0x10000
[DEBUG] Wrote coreboot table at: 0x7aa24000, 0x534 bytes, checksum 3a46
[DEBUG] coreboot table: 1356 bytes.
[DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
[DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
[DEBUG] FSP MEMORY 2. 0x7abfe000 0x00400000
[DEBUG] CONSOLE 3. 0x7abde000 0x00020000
[DEBUG] TIME STAMP 4. 0x7abdd000 0x00000910
[DEBUG] RO MCACHE 5. 0x7abdc000 0x00000364
[DEBUG] MEM INFO 6. 0x7abdb000 0x00000f48
[DEBUG] AFTER CAR 7. 0x7abcd000 0x0000e000
[DEBUG] RAMSTAGE 8. 0x7aa7e000 0x0014f000
[DEBUG] REFCODE 9. 0x7aa50000 0x0002e000
[DEBUG] SMM BACKUP 10. 0x7aa40000 0x00010000
[DEBUG] SMM COMBUFFER11. 0x7aa30000 0x00010000
[DEBUG] IGD OPREGION12. 0x7aa2c000 0x000030c8
[DEBUG] COREBOOT 13. 0x7aa24000 0x00008000
[DEBUG] ACPI 14. 0x7aa00000 0x00024000
[DEBUG] TCPA TCGLOG15. 0x7a9f0000 0x00010000
[DEBUG] SMBIOS 16. 0x7a9e8000 0x00008000
[DEBUG] IMD small region:
[DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
[DEBUG] POWER STATE 1. 0x7affebc0 0x00000040
[DEBUG] FMAP 2. 0x7affea20 0x00000188
[DEBUG] FSP RUNTIME 3. 0x7affea00 0x00000004
[DEBUG] FSPM VERSION 4. 0x7affe9e0 0x00000004
[DEBUG] ROMSTAGE 5. 0x7affe9c0 0x00000004
[DEBUG] ROMSTG STCK 6. 0x7affe900 0x000000a8
[DEBUG] ACPI GNVS 7. 0x7affe8c0 0x00000038
[DEBUG] TPM PPI 8. 0x7affe760 0x0000015a
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 682 ms
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] MTRR: Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
[DEBUG] 0x000000007b000000 - 0x000000007fffffff size 0x05000000 type 0
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
[DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
[DEBUG] 0x0000000100000000 - 0x000000027dffffff size 0x17e000000 type 6
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
[DEBUG] MTRR: default type WB/UC MTRR counts: 6/6.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
[DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
[INFO ] LAPIC 0x1 in XAPIC mode.
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] LAPIC 0x3 in XAPIC mode.
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x1 setup mtrr for CPU physical address size: 39 bits
[DEBUG] apic_id 0x3 setup mtrr for CPU physical address size: 39 bits
[DEBUG] MTRR: TEMPORARY Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
[DEBUG] 0x000000007b000000 - 0x00000000ff7fffff size 0x84800000 type 0
[DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5
[DEBUG] 0x0000000100000000 - 0x000000027dffffff size 0x17e000000 type 6
[DEBUG] MTRR: default type WB/UC MTRR counts: 11/6.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
[DEBUG] MTRR: 3 base 0x00000000ff800000 mask 0x0000007fff800000 type 5
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR check
[DEBUG] Fixed MTRRs : Enabled
[DEBUG] Variable MTRRs: Enabled

[DEBUG] BS: BS_WRITE_TABLES exit times (exec / console): 205 / 308 ms
[INFO ] CBFS: Found 'fallback/payload' @0x1586c0 size 0x151e6b in mcache @0x7abdc2f4
[DEBUG] Checking segment from ROM address 0xff9a88ec
[DEBUG] Checking segment from ROM address 0xff9a8908
[DEBUG] Loading segment from ROM address 0xff9a88ec
[DEBUG] code (compression=1)
[DEBUG] New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xff9a8924 filesize 0x151e33
[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x0000000000151e33
[DEBUG] using LZMA
[DEBUG] Loading segment from ROM address 0xff9a8908
[DEBUG] Entry Point 0x008016da
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 60 ms
[DEBUG] Finalizing chipset.
[DEBUG] ME: Host Firmware Status Register 1 : 0x90000245
[DEBUG] ME: Host Firmware Status Register 2 : 0x83108106
[DEBUG] ME: Host Firmware Status Register 3 : 0x00000300
[DEBUG] ME: Host Firmware Status Register 4 : 0x00084000
[DEBUG] ME: Host Firmware Status Register 5 : 0x00000000
[DEBUG] ME: Host Firmware Status Register 6 : 0x40000000
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : YES
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: D3 Support : NO
[DEBUG] ME: D0i3 Support : YES
[DEBUG] ME: Low Power State Enabled : NO
[DEBUG] ME: CPU Replaced : NO
[DEBUG] ME: CPU Replacement Valid : YES
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : Unknown (8)
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : Unknown phase: 0x08 state: 0x10
[DEBUG] ME: Power Down Mitigation : NO
[DEBUG] ME: Firmware SKU : Unknown (0x0)
[DEBUG] ME: FPF status : fused
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 10 / 153 ms
[DEBUG] mp_park_aps done after 0 msecs.
[DEBUG] Jumping to boot code at 0x008016da(0x7aa24000)`

I tried many many parameters, but results are always the same.

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