Project

General

Profile

Actions

Feature #7

open

gnawty support based on acer cb3-111

Added by Alexander Couzens almost 7 years ago. Updated almost 7 years ago.

Status:
In Progress
Priority:
Normal
Category:
board support
Target version:
-
Start date:
11/20/2015
Due date:
% Done:

0%

Estimated time:
Affected versions:
Needs backport to:
Affected hardware:
Affected OS:

Description

Adding google gnawty boards.
This board is very similiar to rambi, the only difference known is the ram configuration.

http://review.coreboot.org/#/c/12500
https://www.coreboot.org/Board:acer/cb3-111

SeaBIOS hangs with message:
Press F12 ...

but pressing f12 does nothing.

Booting ELF payload with openwrt fails because e820 isn't properly passed.

Using Linux Payload + x64 kernel openwrt boots up.


Files

bootup_x86_64_openwrt (60 KB) bootup_x86_64_openwrt Alexander Couzens, 11/20/2015 10:07 PM
vga_bios_hangs (29.1 KB) vga_bios_hangs Alexander Couzens, 11/20/2015 11:04 PM
dmesg (63.6 KB) dmesg dmesg_chromeos_gnawty Alexander Couzens, 11/21/2015 03:03 AM
lspci_vvv (10.3 KB) lspci_vvv chromeos Alexander Couzens, 11/21/2015 03:08 AM
lspci (789 Bytes) lspci chromso Alexander Couzens, 11/21/2015 03:08 AM
lspci_vvttnn (716 Bytes) lspci_vvttnn chromeos Alexander Couzens, 11/21/2015 03:09 AM
booting_4.1 (58.7 KB) booting_4.1 openwrt with 4.1 Alexander Couzens, 11/22/2015 10:35 PM
booting_4.1_with_ioapic (63.5 KB) booting_4.1_with_ioapic openwrt with 4.1 but with select ioapic in cb Alexander Couzens, 11/23/2015 01:46 AM
Actions #3

Updated by Alexander Couzens almost 7 years ago

  • Status changed from New to In Progress
Actions #4

Updated by Alexander Couzens almost 7 years ago

Actions #5

Updated by Alexander Couzens almost 7 years ago

Actions #7

Updated by Alexander Couzens almost 7 years ago

I can see

[    0.000000] ACPI: PM-Timer IO Port: 0x408
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] I/O APIC 0xfec00000 registers return all ones, skipping!

But coreboot detects

APIC: 00: enabled 1
APIC: 02: enabled 1
APIC: 00 (Intel BayTrail SoC)
APIC: 02 (unknown)

I guess the second should not be enabled. but why is linux only finds this one ONLY ?

Actions #8

Updated by Alexander Couzens almost 7 years ago

last upstream rev:

commit 7dcf9d51e5ffadfcf8b5fceddcddb4e1d0a7db37
Author: Julius Werner <jwerner@chromium.org>
Date:   Fri Oct 16 13:10:02 2015 -0700

    arm64: tegra132: tegra210: Remove old arm64/stage_entry.S

    Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: http://review.coreboot.org/12078
Actions #10

Updated by Alexander Couzens almost 7 years ago

the second APIC 02 looks good, because it's the second processor.

Actions #11

Updated by lx r almost 7 years ago

linux is now booting.

Actions #12

Updated by Alexander Couzens almost 7 years ago

  • Description updated (diff)
Actions #13

Updated by Alexander Couzens almost 7 years ago

Missing:

  • sdcard as file for SeaBIOS
  • migrate gnawty into rambi
  • pci irq routing
  • test if seabios can work with irq routing

SeaBios is booting without hardware irqs.
I'm waiting for a board to hack on.

Actions

Also available in: Atom PDF