Feature #7
closed
- Status changed from New to In Progress
I can see
[ 0.000000] ACPI: PM-Timer IO Port: 0x408
[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
[ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[ 0.000000] I/O APIC 0xfec00000 registers return all ones, skipping!
But coreboot detects
APIC: 00: enabled 1
APIC: 02: enabled 1
APIC: 00 (Intel BayTrail SoC)
APIC: 02 (unknown)
I guess the second should not be enabled. but why is linux only finds this one ONLY ?
last upstream rev:
commit 7dcf9d51e5ffadfcf8b5fceddcddb4e1d0a7db37
Author: Julius Werner <jwerner@chromium.org>
Date: Fri Oct 16 13:10:02 2015 -0700
arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12078
the second APIC 02 looks good, because it's the second processor.
- Description updated (diff)
Missing:
sdcard as file for SeaBIOS
- migrate gnawty into rambi
- pci irq routing
- test if seabios can work with irq routing
SeaBios is booting without hardware irqs.
I'm waiting for a board to hack on.
- Status changed from In Progress to Closed
No updates in 7 years. Closing.
Martin Roth wrote in #note-14:
No updates in 7 years. Closing.
also, gnawty has been supported as a rambi variant since early 2017
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