- Email: firstname.lastname@example.org
- Registered on: 11/16/2015
- coreboot (Manager, Developer, Reporter, 11/16/2015)
Reported issues: 0
- 05:05 PM coreboot Feature #218 (Resolved): Setting Max Payload Size of End Point in correspondence with Max Payload...
- 03:00 PM coreboot Feature #218 (In Progress): Setting Max Payload Size of End Point in correspondence with Max Payl...
- 10:18 AM coreboot Bug #130: kernel: pci 0000:00:1e.0: bridge has subordinate 06 but max busn 09
- Device 5:0.0 is cardbus controller with hotplug capability. We should leave some reserve of free PCI bus numbers in c...
- 09:47 AM coreboot Bug #126 (Resolved): *AGESA: Fix UMA calculations* breaks boot on ASRock E350M1
- Fixed: https://review.coreboot.org/c/20590/
b6a0fe5 AGESA boards: Fix regressions with LATE_CBMEM_INIT
- 01:18 PM coreboot Bug #126 (In Progress): *AGESA: Fix UMA calculations* breaks boot on ASRock E350M1
- 01:33 PM coreboot Bug #82 (Resolved): CAR fails on LGA775 pentium 4-like CPUs
- Not a cache-as-ram issue.
P4 NetBurst does not implement MSR 0xcd used in udelay() with UDELAY_LAPIC=y. Also the b...
- 01:50 PM coreboot Bug #42 (Closed): Commit 53c388fe6dfb4fc4ffcee6c58345d353c6ec33bf breaks coreboot for alix2d13
- 09:11 PM coreboot Bug #45: F2A85-M fails to detect 24-32GB of RAM properly
- You can find the patch with verbose raminit debugging here: https://review.coreboot.org/#/c/15320/
Record of last ...
- 05:05 AM coreboot Bug #45: F2A85-M fails to detect 24-32GB of RAM properly
- I need to modify source tree to get extended debugging about DIMMs. In the meantime, you can post the serial console ...
- 06:51 AM coreboot Feature #57 (Feedback): Create build rule for ASUS E35M1-I Deluxe
- If you have verified close similarity with some already supported board, preliminary board support could happen with ...
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