KM Kyösti Mälkki
- Login: kyosti.malkki
- Email: kyosti.malkki@gmail.com
- Registered on: 11/16/2015
Issues
| open | closed | Total | |
|---|---|---|---|
| Assigned issues | 0 | 5 | 5 |
| Reported issues | 0 | 0 | 0 |
Projects
| Project | Roles | Registered on |
|---|---|---|
| coreboot | Manager, Developer | 11/16/2015 |
Activity
07/13/2022
- KM 03:54 AM coreboot Bug #388 (Resolved): denverton_ns: crash when starting postcar
06/05/2022
- KM 04:56 PM coreboot Bug #386: ASUS P8Z77-V LX2 - Raminit issue at second boot with two 8GiB DIMMs - bootloop
- > I build coreboot today for the ASUS P8Z77-V LX2 and used the latest coreboot master code.
> ...
I think only 8 GiB of RAM was available at first boot.
One of the DIMMs has SPD CRC error, and while they have matching part number, ti...
12/19/2019
- KM 05:05 PM coreboot Feature #218 (Resolved): Setting Max Payload Size of End Point in correspondence with Max Payload Size of Root Complex
- https://review.coreboot.org/c/coreboot/+/37769
12/16/2019
- KM 03:00 PM coreboot Feature #218 (In Progress): Setting Max Payload Size of End Point in correspondence with Max Payload Size of Root Complex
07/18/2017
- KM 10:18 AM coreboot Bug #130: kernel: pci 0000:00:1e.0: bridge has subordinate 06 but max busn 09
- Device 5:0.0 is cardbus controller with hotplug capability. We should leave some reserve of free PCI bus numbers in case the user plugs in a PCI bridge at runtime. I am not sure where max busn 9 comes from in the kernel messages.
- KM 09:47 AM coreboot Bug #126 (Resolved): *AGESA: Fix UMA calculations* breaks boot on ASRock E350M1
- Fixed: https://review.coreboot.org/c/20590/
b6a0fe5 AGESA boards: Fix regressions with LATE_CBMEM_INIT
06/28/2017
- KM 01:18 PM coreboot Bug #126 (In Progress): *AGESA: Fix UMA calculations* breaks boot on ASRock E350M1
12/14/2016
- KM 01:33 PM coreboot Bug #82 (Resolved): CAR fails on LGA775 pentium 4-like CPUs
- Not a cache-as-ram issue.
P4 NetBurst does not implement MSR 0xcd used in udelay() with UDELAY_LAPIC=y. Also the board this was tested on required super-io GPIOs to replicate BSEL lines between CPU and MCH.
07/09/2016
- KM 01:50 PM coreboot Bug #42 (Closed): Commit 53c388fe6dfb4fc4ffcee6c58345d353c6ec33bf breaks coreboot for alix2d13
06/22/2016
- KM 09:11 PM coreboot Bug #45: F2A85-M fails to detect 24-32GB of RAM properly
- You can find the patch with verbose raminit debugging here: https://review.coreboot.org/#/c/15320/
Record of last known-good f2a85-m test was commit ab90f96b and I have attached a binary with my patch applied on top. Note that I did n...