Feature #218: Setting Max Payload Size of End Point in correspondence with Max Payload Size of Root Complex - coreboot - Issue Tracker

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Feature #218

closed

Setting Max Payload Size of End Point in correspondence with Max Payload Size of Root Complex

Added by Ilya Gurevich over 5 years ago. Updated about 5 years ago.

Status:

Resolved

Priority:

Normal

Assignee:

Kyösti Mälkki

Category:

chipset configuration

Target version:

Start date:

07/03/2019

Due date:

% Done:

100%

Estimated time:

Affected versions:

Needs backport to:

Affected hardware:

Affected OS:

Description

Hello,

Device: Intel Denverton NS (C3955 stepping B1) on Harcuvar CRB
Coreboot revision: 4.9
FSP build: 0015.D99 (provided as the package "565490-denverto-fsp-kit-pv004-v1-51")
OS: VxWorks 7 SR0540

During coreboot integration with Intel Denverton FSP I have found that PCIe bus enumeration doesn't care of matching Max Payload Size (MPS) of End Point (EP) and Root Complex (RC) as advised by PCIe standard.

FSP initializes MPS of RC to 512B whereas MPS of EP is left at default value 128B. As result EP device stops working correctly and reports uncorrectable error - Malformed TLP.
In my case EP is PCIe LAN Controller 82574L GEI (8086:10D3).

I have fixed this problem by adding new routine "pciexp_set_max_payload_size" that is called from "pciexp_tune_dev".
The updated files pciexp_device.c and pciexp.h are attached.

Thanks.

Ilya.

Files

Download all files

pciexp.h (1.1 KB) pciexp.h		Ilya Gurevich, 07/03/2019 02:04 PM
pciexp_device.c (18 KB) pciexp_device.c		Ilya Gurevich, 07/03/2019 02:04 PM
.config (25 KB) .config		Ilya Gurevich, 07/03/2019 02:05 PM