Feature #218

Setting Max Payload Size of End Point in correspondence with Max Payload Size of Root Complex

Added by Ilya Gurevich over 2 years ago. Updated almost 2 years ago.

Status:ResolvedStart date:07/03/2019
Priority:NormalDue date:
Assignee:Kyösti Mälkki% Done:

100%

Category:chipset configuration
Target version:-

Description

Hello,


Device: Intel Denverton NS (C3955 stepping B1) on Harcuvar CRB
Coreboot revision: 4.9
FSP build: 0015.D99 (provided as the package "565490-denverto-fsp-kit-pv004-v1-51")
OS: VxWorks 7 SR0540


During coreboot integration with Intel Denverton FSP I have found that PCIe bus enumeration doesn't care of matching Max Payload Size (MPS) of End Point (EP) and Root Complex (RC) as advised by PCIe standard.

FSP initializes MPS of RC to 512B whereas MPS of EP is left at default value 128B. As result EP device stops working correctly and reports uncorrectable error - Malformed TLP.
In my case EP is PCIe LAN Controller 82574L GEI (8086:10D3).

I have fixed this problem by adding new routine "pciexp_set_max_payload_size" that is called from "pciexp_tune_dev".
The updated files pciexp_device.c and pciexp.h are attached.

Thanks.

Ilya.

pciexp.h Magnifier (1.1 KB) Ilya Gurevich, 07/03/2019 02:04 PM

pciexp_device.c Magnifier (18 KB) Ilya Gurevich, 07/03/2019 02:04 PM

.config (25 KB) Ilya Gurevich, 07/03/2019 02:05 PM

History

#1 Updated by Kyösti Mälkki almost 2 years ago

  • Status changed from New to In Progress
  • Assignee set to Kyösti Mälkki

#2 Updated by Kyösti Mälkki almost 2 years ago

  • Status changed from In Progress to Resolved
  • % Done changed from 0 to 100

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