Added by Paul Menzel about 7 years ago. Updated about 5 years ago.
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Description
On the Asus KGPE-D16, despite setting the error level to 3 (Error) in Kconfig, messages are output with log level spew.
Looking more into it, it looks like the log level is honored for romstage, but not ramstage.
With
[…]
CONFIG_USE_OPTION_TABLE=y
# CONFIG_STATIC_OPTION_TABLE is not set
[…]
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
[…]
I get the messages below.
======= Wed Mar 1 16:59:07 2017 (adjust=86.8us)
00.000: <00>
00.192: WARNING: MC4 Machine Check Exception detected on node 0!
00.193: Signature: e200028000010c0f
00.254: WARNING: MC4 Machine Check Exception detected on node 1!
00.260: Signature: f627f6fe561fd7bb
00.264: WARNING: MC4 Machine Check Exception detected on node 2!
00.277: Signature: fa100aa1ca054c0f
01.576: <00>
02.838: <00>
52.681: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
52.681: CBFS: Locating 'cmos_layout.bin'
52.681: CBFS: Found @ offset 2b000 size e88
52.682:
52.682:
52.682: coreboot-4.5-1091-ge13b775 Wed Mar 1 15:32:21 UTC 2017 ramstage starting...
52.682: Moving GDT to b7ffe9e0...ok
52.682: Normal boot.
52.682: BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
52.682: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
52.682: Enumerating buses...
52.682: Show all devs... Before device enumeration.
52.682: Root Device: enabled 1
52.682: CPU_CLUSTER: 0: enabled 1
52.682: APIC: 00: enabled 1
52.682: DOMAIN: 0000: enabled 1
52.682: PCI: 00:18.0: enabled 1
52.682: PCI: 00:00.0: enabled 1
52.682: PCI: 00:00.1: enabled 1
52.682: PCI: 00:00.2: enabled 1
52.682: PCI: 00:02.0: enabled 1
52.682: PCI: 00:03.0: enabled 0
52.682: PCI: 00:04.0: enabled 1
52.682: PCI: 00:05.0: enabled 0
52.682: PCI: 00:06.0: enabled 0
52.682: PCI: 00:07.0: enabled 0
52.682: PCI: 00:08.0: enabled 0
52.682: PCI: 00:09.0: enabled 1
52.682: PCI: 00:0a.0: enabled 1
52.682: PCI: 00:0b.0: enabled 1
52.682: PCI: 00:0c.0: enabled 1
52.682: PCI: 00:0d.0: enabled 1
52.682: PCI: 00:11.0: enabled 1
52.682: PCI: 00:12.0: enabled 1
52.682: PCI: 00:12.1: enabled 1
52.682: PCI: 00:12.2: enabled 1
52.682: PCI: 00:13.0: enabled 1
52.682: PCI: 00:13.1: enabled 1
52.682: PCI: 00:13.2: enabled 1
52.682: PCI: 00:14.0: enabled 1
[…]
$ nl -ba src/console/init.c
[…]
33 asmlinkage void console_init(void)
34 {
35 #if !defined(__PRE_RAM__)
36 console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
37 get_option(&console_loglevel, "debug_level");
38 #endif
39
40 #if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__)
41 pci_early_bridge_init();
42 #endif
43
44 console_hw_init();
45
46 printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n",
47 coreboot_version, coreboot_extra_version, coreboot_build);
48 }
So the problem results from the NVRAM default value overwriting the built in log level in ramstage.
This is the behavior wanted by people using the debug_level option. If you don't want to maintain NVRAM settings, you can disable CONFIG_USE_OPTION_TABLE. Also the Kconfig option prompts "Default console log level" and NOT "Effective console log level".
Indeed, it’s the current behavior that this CMOS setting does not apply to romstage.