coreboot

dojo-rev1 ~ # lspci
0000:00:00.0 PCI bridge: MEDIATEK Corp. Device 8195 (rev 01)
0000:01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller 980
0001:00:00.0 PCI bridge: MEDIATEK Corp. Device 8195 (rev 01)
0001:01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter

Yu-Ping Wu wrote:

Similar to #499, after https://review.coreboot.org/c/coreboot/+/75012, Dojo fails to boot.
Disabling CONFIG_RESOURCE_ALLOCATION_TOP_DOWN fixes the problem.
However I'm not sure how to fix it from MediaTek's PCIe functions or settings (for example mtk_pcie_domain_read_resources).

I don't understand the hardware however I tried to look at the soc code.
In soc/mediatek/common/pcie.c I see the following:

write32p(table, mmio_res->cpu_addr |
	 PCIE_ATR_SIZE(__fls(mmio_res->size)));

Correct me if I'm wrong but would this not only program the most significant bit of the mmio region size?
Could it be that instead of a 48M window a 32M window is actually set up which would break top down allocation?
Would it be worth trying to set a size of 64M or 32M?

Arthur Heymans wrote in #note-3:

I don't understand the hardware however I tried to look at the soc code.
In soc/mediatek/common/pcie.c I see the following:

write32p(table, mmio_res->cpu_addr |
PCIE_ATR_SIZE(__fls(mmio_res->size)));

Correct me if I'm wrong but would this not only program the most significant bit of the mmio region size?
Could it be that instead of a 48M window a 32M window is actually set up which would break top down allocation?
Would it be worth trying to set a size of 64M or 32M?

Yes, you're right. This will be fixed in https://review.coreboot.org/c/coreboot/+/78044. Thanks.