|
|
|
|
|
coreboot-coreboot-unknown.9999.d77ee41 Tue Aug 29 18:58:05 UTC 2023 aarch64 bootblock starting (log level: 8)...
|
|
ARM64: Exception handlers installed.
|
|
ARM64: Testing exception
|
|
ARM64: Done test exception
|
|
Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
|
|
Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
|
|
Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
|
|
Mapping address range [0x00100000:0x00130000) as cacheable | read-write | secure | normal
|
|
Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
|
|
Backing address range [0x00000000:0x00200000) with new page table @0x00110000
|
|
Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
|
|
Backing address range [0x00200000:0x00400000) with new page table @0x00111000
|
|
Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
|
|
WDT: Status = 0x0
|
|
WDT: Last reset was cold boot
|
|
SPI0(PAD0) initialized at 2971428 Hz
|
|
VBOOT: Loading verstage.
|
|
SF: Detected 00 0000 with sector size 0x1000, total 0x800000
|
|
FMAP: Found "FLASH" version 1.1 at 0x20000.
|
|
FMAP: base = 0x0 size = 0x800000 #areas = 25
|
|
FMAP: area COREBOOT found @ 21000 (4014080 bytes)
|
|
CBFS: mcache @0x00107c00 built for 69 files, used 0xf24 of 0x1000 bytes
|
|
CBFS: Found 'fallback/verstage' @0x770c0 size 0xb227 in mcache @0x00107ec8
|
|
read SPI 0x98114 0xb227: 4011 us, 11370 KB/s, 90.960 Mbps
|
|
|
|
|
|
coreboot-coreboot-unknown.9999.d77ee41 Tue Aug 29 18:58:05 UTC 2023 aarch64 verstage starting (log level: 8)...
|
|
ARM64: Exception handlers installed.
|
|
ARM64: Testing exception
|
|
ARM64: Done test exception
|
|
FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
|
|
SF: Detected 00 0000 with sector size 0x1000, total 0x800000
|
|
Probing TPM I2C: done! DID_VID 0x00281ae0
|
|
TPM ready after 0 ms
|
|
cr50 TPM 2.0 (i2c 3:0x50 id 0x28)
|
|
Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.201/cr50_v3.9
|
|
Current CR50_BOARD_CFG = 0x00000000, matches desired = 0x00000000
|
|
tlcl_send_startup: Startup return code is 0
|
|
TPM: setup succeeded
|
|
src/security/tpm/tss/tcg-2.0/tss.c:250 index 0x1007 return code 0
|
|
src/security/tpm/tss/tcg-2.0/tss.c:250 index 0x1008 return code 0
|
|
out: cmd=0xd: 03 f0 0d 00 00 00 00 00
|
|
in-header: 03 67 00 00 08 00 00 00
|
|
in-data: ea e4 47 03 73 02 01 00
|
|
Chrome EC: UHEPI supported
|
|
out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
|
|
in-header: 03 79 00 00 08 00 00 00
|
|
in-data: 1c 00 60 00 00 00 00 00
|
|
Reading cr50 boot mode
|
|
GSC says boot_mode is VERIFIED_RW(0x00).
|
|
Phase 1
|
|
FMAP: area GBB found @ 3f5000 (12032 bytes)
|
|
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
|
|
Phase 2
|
|
Phase 3
|
|
FMAP: area GBB found @ 3f5000 (12032 bytes)
|
|
read SPI 0x3f5180 0x1000: 376 us, 10893 KB/s, 87.144 Mbps
|
|
FMAP: area VBLOCK_B found @ 580000 (8192 bytes)
|
|
FMAP: area VBLOCK_B found @ 580000 (8192 bytes)
|
|
VB2:vb2_verify_keyblock() Checking keyblock signature...
|
|
VB2:vb2_digest_init() 1144 bytes, hash algo 3, HW acceleration unsupported
|
|
VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using SW
|
|
VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported, using SW
|
|
FMAP: area VBLOCK_B found @ 580000 (8192 bytes)
|
|
FMAP: area VBLOCK_B found @ 580000 (8192 bytes)
|
|
VB2:vb2_verify_fw_preamble() Verifying preamble.
|
|
VB2:vb2_digest_init() 1652 bytes, hash algo 2, HW acceleration enabled
|
|
VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW
|
|
VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW
|
|
Phase 4
|
|
FMAP: area FW_MAIN_B found @ 582000 (1527552 bytes)
|
|
VB2:vb2_digest_init() 753216 bytes, hash algo 2, HW acceleration enabled
|
|
VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW
|
|
VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW
|
|
TPM: Extending digest for `VBOOT: boot mode` into PCR 0
|
|
tlcl_extend: response is 0
|
|
TPM: Digest of `VBOOT: boot mode` to PCR 0 measured
|
|
TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1
|
|
tlcl_extend: response is 0
|
|
TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured
|
|
tlcl_lock_nv_write: response is 0
|
|
Slot B is selected
|
|
VBOOT: Returning from verstage.
|
|
FMAP: area FW_MAIN_B found @ 582000 (1527552 bytes)
|
|
CBFS: mcache @0x00108c00 built for 15 files, used 0x320 of 0x1000 bytes
|
|
CBFS: Found 'fallback/romstage' @0x0 size 0x21b02 in mcache @0x00108c00
|
|
read SPI 0x582054 0x21b02: 12100 us, 11403 KB/s, 91.224 Mbps
|
|
BS: bootblock times (exec / console): total (unknown) / 196 ms
|
|
|
|
|
|
coreboot-coreboot-unknown.9999.d77ee41 Tue Aug 29 18:58:05 UTC 2023 aarch64 romstage starting (log level: 8)...
|
|
ARM64: Exception handlers installed.
|
|
ARM64: Testing exception
|
|
ARM64: Done test exception
|
|
[pmif_ulposc_check] calibration done: cur=249M, CAL_RATE=40, target=248M
|
|
spmi_read_check next, slvid:6 rdata = 0x2a.
|
|
spmi_read_check next, slvid:7 rdata = 0x2a.
|
|
pmic_efuse_setting: Set efuses in 11 msecs
|
|
[CLKBUF]dump_clkbuf_log,59: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8180 0x4c 0xf0f 0x9248
|
|
[CLKBUF]dump_clkbuf_log,70: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
|
|
[CLKBUF]dump_clkbuf_log,75: clk buf vrfck_hv_en=0x0
|
|
[CLKBUF]dump_clkbuf_log,59: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8180 0x4c 0xf0f 0x9248
|
|
[CLKBUF]dump_clkbuf_log,70: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x0 0x1 0x1 0x0 0x0
|
|
[CLKBUF]dump_clkbuf_log,75: clk buf vrfck_hv_en=0x0
|
|
[RTC]rtc_boot,322: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
|
|
[RTC]rtc_boot,325: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
|
|
[RTC]rtc_enable_dcxo,66: con=0x406, osc32con=0xde71, sec=0x0
|
|
[RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
|
|
[RTC]rtc_osc_init,62: osc32con val = 0xde71
|
|
[RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
|
|
[RTC]rtc_get_frequency_meter,152: input=15, output=747
|
|
[RTC]rtc_get_frequency_meter,152: input=23, output=927
|
|
[RTC]rtc_get_frequency_meter,152: input=19, output=837
|
|
[RTC]rtc_get_frequency_meter,152: input=17, output=792
|
|
[RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
|
|
[RTC]rtc_boot_common,202: RTC_STATE_REBOOT
|
|
[RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
|
|
[RTC]rtc_bbpu_power_on,296: rtc_write_trigger=1
|
|
[RTC]rtc_bbpu_power_on,298: done BBPU=0x1
|
|
FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
|
|
SF: Detected 00 0000 with sector size 0x1000, total 0x800000
|
|
read SPI 0x57d024 0x19a8: 580 us, 11324 KB/s, 90.592 Mbps
|
|
Probing TPM I2C: done! DID_VID 0x00281ae0
|
|
Locality already claimed
|
|
cr50 TPM 2.0 (i2c 3:0x50 id 0x28)
|
|
src/security/tpm/tss/tcg-2.0/tss.c:250 index 0x100d return code 0
|
|
VB2:vb2_digest_init() 6568 bytes, hash algo 2, HW acceleration enabled
|
|
MRC: Hash idx 0x100d comparison successful.
|
|
DRAM-K: Running fast calibration
|
|
DRAM-K: DRAM calibration data valid pass
|
|
[DRAMC] Dram fast K start
|
|
Read voltage for 800, 4
|
|
Vcore = 750000
|
|
read calibration data from shuffle 4(For verify: WL B0:23, B1: 27)
|
|
[EMI DOE] emi_dcm 0
|
|
[EMI] CEN_CONA(0xf053f154),CEN_CONF(0x421000),CEN_CONH(0x44440003),CEN_CONK(0x0),CHN_CONA(0x444f051)
|
|
Read voltage for 800, 4
|
|
Vcore = 750000
|
|
read calibration data from shuffle 4(For verify: WL B0:23, B1: 27)
|
|
[EMI DOE] emi_dcm 0
|
|
Read voltage for 2133, 0
|
|
Vcore = 750000
|
|
read calibration data from shuffle 0(For verify: WL B0:12, B1: 13)
|
|
DRAM rank0 size:0x100000000,
|
|
DRAM rank1 size=0x100000000
|
|
[EMI] ch0, rk0, dram addr: 80000
|
|
[EMI] bk0, row20, col0
|
|
DRAM rank0 size:0x100000000,
|
|
DRAM rank1 size=0x100000000
|
|
[EMI] ch0, rk0, dram addr: 80000
|
|
[EMI] bk0, row20, col0
|
|
[MEM] rank 0 complex R/W mem test passed
|
|
[MEM] rank 1 complex R/W mem test passed
|
|
DRAM-K: Fast calibration passed in 242 msecs
|
|
DRAM rank0 size:0x100000000,
|
|
DRAM rank1 size=0x100000000
|
|
dram size = 0x200000000
|
|
Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
|
|
Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
|
|
Backing address range [0x40000000:0x80000000) with new page table @0x00112000
|
|
Backing address range [0x40000000:0x40200000) with new page table @0x00113000
|
|
CBMEM:
|
|
IMD: root @ 0xfffff000 254 entries.
|
|
IMD: root @ 0xffffec00 62 entries.
|
|
FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
|
|
FMAP: area RW_VPD found @ 577000 (16384 bytes)
|
|
FMAP: area FW_MAIN_B found @ 582000 (1527552 bytes)
|
|
FMAP: area COREBOOT found @ 21000 (4014080 bytes)
|
|
DRAM-K: CBMEM DRAM info is unsupported (USE_CBMEM_DRAM_INFO)
|
|
CBFS: Found 'fallback/ramstage' @0x21b80 size 0x115e6 in mcache @0x00108c54
|
|
read SPI 0x5a3bd4 0x115e6: 6082 us, 11697 KB/s, 93.576 Mbps
|
|
BS: romstage times (exec / console): total (unknown) / 460 ms
|
|
|
|
|
|
coreboot-coreboot-unknown.9999.d77ee41 Tue Aug 29 18:58:05 UTC 2023 aarch64 ramstage starting (log level: 8)...
|
|
ARM64: Exception handlers installed.
|
|
ARM64: Testing exception
|
|
ARM64: Done test exception
|
|
Enumerating buses...
|
|
Show all devs... Before device enumeration.
|
|
Root Device: enabled 1
|
|
CPU_CLUSTER: 0: enabled 1
|
|
DOMAIN: 0000: enabled 1
|
|
PCI: 00:00.0: enabled 1
|
|
Compare with tree...
|
|
Root Device: enabled 1
|
|
CPU_CLUSTER: 0: enabled 1
|
|
DOMAIN: 0000: enabled 1
|
|
PCI: 00:00.0: enabled 1
|
|
Root Device scanning...
|
|
scan_static_bus for Root Device
|
|
CPU_CLUSTER: 0 enabled
|
|
out: cmd=0x11f: 03 d3 1f 01 00 00 08 00 02 00 00 00 00 00 00 00
|
|
in-header: 03 f7 00 00 04 00 00 00
|
|
in-data: 02 00 00 00
|
|
SKU Code: 0x2
|
|
mtk_pcie_domain_enable: 1391962 us elapsed since assert PERST#
|
|
mtk_pcie_domain_enable: PCIe link up success (35 tries)
|
|
DOMAIN: 0000 enabled
|
|
DOMAIN: 0000 scanning...
|
|
PCI: pci_scan_bus for bus 00
|
|
PCI: 00:00.0 subordinate bus PCI Express
|
|
PCI: 00:00.0 [14c3/8195] enabled
|
|
PCI: 00:00.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:00.0
|
|
PCI: pci_scan_bus for bus 01
|
|
PCI: 01:00.0 [144d/a809] enabled
|
|
PCIe: Max_Payload_Size adjusted to 256
|
|
scan_bus: bus PCI: 00:00.0 finished in 18 msecs
|
|
scan_bus: bus DOMAIN: 0000 finished in 40 msecs
|
|
scan_static_bus for Root Device done
|
|
scan_bus: bus Root Device finished in 133 msecs
|
|
done
|
|
BS: BS_DEV_ENUMERATE run times (exec / console): 36 / 150 ms
|
|
Allocating resources...
|
|
Reading resources...
|
|
Root Device read_resources bus 0 link: 0
|
|
DRAM rank0 size:0x100000000,
|
|
DRAM rank1 size=0x100000000
|
|
dram size = 0x200000000
|
|
dev: CPU_CLUSTER: 0, index: 0x0, base: 0x40000000, size: 0x200000000
|
|
DOMAIN: 0000 read_resources bus 0 link: 0
|
|
PCI: 00:00.0 read_resources bus 1 link: 0
|
|
PCI: 00:00.0 read_resources bus 1 link: 0 done
|
|
DOMAIN: 0000 read_resources bus 0 link: 0 done
|
|
Root Device read_resources bus 0 link: 0 done
|
|
Done reading resources.
|
|
Show resources in subtree (Root Device)...After reading.
|
|
Root Device child on link 0 CPU_CLUSTER: 0
|
|
CPU_CLUSTER: 0
|
|
CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
|
|
DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
|
DOMAIN: 0000 resource base 20000000 size 0 align 0 gran 0 limit 20ffffff flags 40040100 index 10000000
|
|
DOMAIN: 0000 resource base 21000000 size 0 align 0 gran 0 limit 23ffffff flags 40040200 index 10000100
|
|
PCI: 00:00.0 child on link 0 PCI: 01:00.0
|
|
PCI: 00:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 00:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 10
|
|
PCI: 01:00.0
|
|
PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
|
=== Resource allocator: DOMAIN: 0000 - Pass 1 (relative placement) ===
|
|
PCI: 00:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 00:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
PCI: 00:00.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
|
|
PCI: 00:00.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
|
|
DOMAIN: 0000 io: base: 20000000 size: 0 align: 0 gran: 0 limit: 20ffffff
|
|
DOMAIN: 0000: Resource ranges:
|
|
* Base: 20000000, Size: 1000000, Tag: 100
|
|
DOMAIN: 0000 io: base: 20000000 size: 0 align: 0 gran: 0 limit: 20ffffff done
|
|
DOMAIN: 0000 mem: base: 21000000 size: 0 align: 0 gran: 0 limit: 23ffffff
|
|
DOMAIN: 0000: Resource ranges:
|
|
* Base: 21000000, Size: 3000000, Tag: 200
|
|
PCI: 00:00.0 20 * [0x23f00000 - 0x23ffffff] limit: 23ffffff mem
|
|
PCI: 00:00.0 10 * [0x23efc000 - 0x23efffff] limit: 23efffff prefmem
|
|
DOMAIN: 0000 mem: base: 21000000 size: 0 align: 0 gran: 0 limit: 23ffffff done
|
|
PCI: 01:00.0 10 * [0x23f00000 - 0x23f03fff] limit: 23f03fff mem
|
|
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
|
|
Root Device assign_resources, bus 0 link: 0
|
|
mtk_pcie_set_trans_window: set IO trans window: cpu_addr = 0x20000000, pci_addr = 0x20000000, size = 0x1000000
|
|
mtk_pcie_set_trans_window: set MEM trans window: cpu_addr = 0x21000000, pci_addr = 0x21000000, size = 0x3000000
|
|
DOMAIN: 0000 assign_resources, bus 0 link: 0
|
|
PCI: 00:00.0 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c bus 01 io
|
|
PCI: 00:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
PCI: 00:00.0 20 <- [0x0000000023f00000 - 0x0000000023ffffff] size 0x00100000 gran 0x14 bus 01 mem
|
|
PCI: 00:00.0 10 <- [0x0000000023efc000 - 0x0000000023efffff] size 0x00004000 gran 0x0e prefmem64
|
|
PCI: 00:00.0 assign_resources, bus 1 link: 0
|
|
PCI: 01:00.0 10 <- [0x0000000023f00000 - 0x0000000023f03fff] size 0x00004000 gran 0x0e mem64
|
|
PCI: 00:00.0 assign_resources, bus 1 link: 0 done
|
|
DOMAIN: 0000 assign_resources, bus 0 link: 0 done
|
|
Root Device assign_resources, bus 0 link: 0 done
|
|
Done setting resources.
|
|
Show resources in subtree (Root Device)...After assigning values.
|
|
Root Device child on link 0 CPU_CLUSTER: 0
|
|
CPU_CLUSTER: 0
|
|
CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
|
|
DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
|
DOMAIN: 0000 resource base 20000000 size 0 align 0 gran 0 limit 20ffffff flags 40040100 index 10000000
|
|
DOMAIN: 0000 resource base 21000000 size 0 align 0 gran 0 limit 23ffffff flags 40040200 index 10000100
|
|
PCI: 00:00.0 child on link 0 PCI: 01:00.0
|
|
PCI: 00:00.0 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c
|
|
PCI: 00:00.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
|
|
PCI: 00:00.0 resource base 23f00000 size 100000 align 20 gran 20 limit 23ffffff flags 60080202 index 20
|
|
PCI: 00:00.0 resource base 23efc000 size 4000 align 14 gran 14 limit 23efffff flags 60001201 index 10
|
|
PCI: 01:00.0
|
|
PCI: 01:00.0 resource base 23f00000 size 4000 align 14 gran 14 limit 23f03fff flags 60000201 index 10
|
|
Done allocating resources.
|
|
BS: BS_DEV_RESOURCES run times (exec / console): 0 / 547 ms
|
|
Enabling resources...
|
|
PCI: 00:00.0 bridge ctrl <- 0003
|
|
PCI: 00:00.0 cmd <- 06
|
|
PCI: 01:00.0 cmd <- 02
|
|
done.
|
|
BS: BS_DEV_ENABLE run times (exec / console): 0 / 17 ms
|
|
Initializing devices...
|
|
Root Device init
|
|
configure_display: Starting display initialization
|
|
SINK DPCD version: 0x11
|
|
SINK SUPPORT SSC!
|
|
Extracted contents:
|
|
header: 00 ff ff ff ff ff ff 00
|
|
serial number: 09 e5 25 0a 00 00 00 00 2c 1f
|
|
version: 01 04
|
|
basic params: 95 1d 11 78 03
|
|
chroma info: 28 65 97 59 54 8e 27 1e 50 54
|
|
established: 00 00 00
|
|
standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
|
descriptor 1: a4 39 80 c8 70 38 50 40 30 20 36 00 26 a5 10 00 00 1a
|
|
descriptor 2: 6d 26 80 c8 70 38 50 40 30 20 36 00 26 a5 10 00 00 1a
|
|
descriptor 3: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
descriptor 4: 00 00 00 02 00 0d 40 ff 0a 3c 7d 0f 0f 1f 7d 00 00 00
|
|
extensions: 00
|
|
checksum: d2
|
|
|
|
Manufacturer: BOE Model a25 Serial Number 0
|
|
Made week 44 of 2021
|
|
EDID version: 1.4
|
|
Digital display
|
|
6 bits per primary color channel
|
|
DisplayPort interface
|
|
Maximum image size: 29 cm x 17 cm
|
|
Gamma: 220%
|
|
Check DPMS levels
|
|
Supported color formats: RGB 4:4:4
|
|
First detailed timing is preferred timing
|
|
Supports GTF timings within operating range
|
|
Established timings supported:
|
|
Standard timings supported:
|
|
Detailed timings
|
|
Hex of detail: a43980c8703850403020360026a51000001a
|
|
Detailed mode (IN HEX): Clock 147560 KHz, 126 mm x a5 mm
|
|
0780 07b0 07d0 0848 hborder 0
|
|
0438 043b 0441 0488 vborder 0
|
|
+hsync -vsync
|
|
Did detailed timing
|
|
Hex of detail: 6d2680c8703850403020360026a51000001a
|
|
Detailed mode (IN HEX): Clock 98370 KHz, 126 mm x a5 mm
|
|
0780 07b0 07d0 0848 hborder 0
|
|
0438 043b 0441 0488 vborder 0
|
|
+hsync -vsync
|
|
Hex of detail: 000000000000000000000000000000000000
|
|
Manufacturer-specified data, tag 0
|
|
Hex of detail: 00000002000d40ff0a3c7d0f0f1f7d000000
|
|
Manufacturer-specified data, tag 2
|
|
Checksum
|
|
Checksum: 0xd2 (valid)
|
|
RX support linkrate = 0xa, lanecount = 0x2
|
|
CR Training START
|
|
lane(0), set swing(0x1), emp(0x0)
|
|
lane(1), set swing(0x1), emp(0x0)
|
|
CR Training Success
|
|
lane(0), set swing(0x0), emp(0x0)
|
|
lane(1), set swing(0x0), emp(0x0)
|
|
EQ Training START
|
|
lane(0), set swing(0x1), emp(0x0)
|
|
lane(1), set swing(0x1), emp(0x0)
|
|
EQ Training Success
|
|
Link Training Success
|
|
MSA:Htt(2120), Vtt(1160), Hact(1920), Vact(1080), FPS(60)
|
|
Output Video enable!
|
|
TU_size 522, FValue 2
|
|
pixel rate(khz) = 147560, sdp_dc_init = 0x10
|
|
mute = 0x50
|
|
DPTX calc pixel clock = 147 MHz, dp_intf clock = 36MHz
|
|
configure_display: 'BOE unknown name' 1920x1080@0Hz
|
|
mtk_ddp_mode_set: display resolution: 1920x1080@0 bpp 4
|
|
␛[1;4mmtk_ddp_mode_set: vrefresh is not provided; using 60
|
|
framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
|
|
x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
|
|
init hardware done!
|
|
0x00000018: ctrlr->caps
|
|
52.000 MHz: ctrlr->f_max
|
|
0.400 MHz: ctrlr->f_min
|
|
0x40ff8080: ctrlr->voltages
|
|
sclk: 390625
|
|
Bus Width = 1
|
|
sclk: 390625
|
|
Bus Width = 1
|
|
out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
|
|
in-header: 03 fc 00 00 01 00 00 00
|
|
in-data: 00
|
|
out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
|
|
in-header: 03 fd 00 00 00 00 00 00
|
|
in-data:
|
|
out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
|
|
in-header: 03 fc 00 00 01 00 00 00
|
|
in-data: 00
|
|
out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
|
|
in-header: 03 fd 00 00 00 00 00 00
|
|
in-data:
|
|
[SSUSB] Setting up USB HOST controller...
|
|
[SSUSB] u3phy_ports_enable u2p:1, u3p:1
|
|
[SSUSB] phy power-on done.
|
|
SF: Detected 00 0000 with sector size 0x1000, total 0x800000
|
|
FMAP: area FW_MAIN_B found @ 582000 (1527552 bytes)
|
|
CBFS: Found 'dpm.dm' @0x33e80 size 0x3a in mcache @0xfffdd120
|
|
mtk_init_mcu: Loaded (and reset) dpm.dm in 19 msecs (66 bytes)
|
|
CBFS: Found 'dpm.pm' @0x33f00 size 0x2a3b in mcache @0xfffdd150
|
|
read SPI 0x5b5f30 0x2a3b: 913 us, 11841 KB/s, 94.728 Mbps
|
|
mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (13702 bytes)
|
|
CBFS: Found 'dpm.dm' @0x33e80 size 0x3a in mcache @0xfffdd120
|
|
mtk_init_mcu: Loaded (and reset) dpm.dm in 6 msecs (66 bytes)
|
|
CBFS: Found 'dpm.pm' @0x33f00 size 0x2a3b in mcache @0xfffdd150
|
|
read SPI 0x5b5f30 0x2a3b: 912 us, 11854 KB/s, 94.832 Mbps
|
|
mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (13702 bytes)
|
|
CBFS: Found 'spm_firmware.bin' @0x52400 size 0x1f74 in mcache @0xfffdd1e8
|
|
read SPI 0x5d443c 0x1f74: 734 us, 10970 KB/s, 87.760 Mbps
|
|
SPM: binary array size = 0x9dd
|
|
SPM: spmfw (version pcm_suspend_v1.0_20210519 )
|
|
spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c8/0x15
|
|
mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 33 msecs (10160 bytes)
|
|
SPM: spm_init done in 41 msecs, spm pc = 0x240
|
|
Root Device init finished in 1048 msecs
|
|
CPU_CLUSTER: 0 init
|
|
Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
|
|
[APUAPC] vio 0
|
|
[APUAPC] set_apusys_ao_apc - SUCCESS!
|
|
[APUAPC] set_apusys_noc_dapc - SUCCESS!
|
|
[APUAPC] D0_APC_0: 0x40014010
|
|
[APUAPC] D0_APC_1: 0x0
|
|
[APUAPC] D0_APC_2: 0x40000000
|
|
[APUAPC] D0_APC_3: 0x5515
|
|
[APUAPC] D0_APC_4: 0x0
|
|
[APUAPC] D1_APC_0: 0xffffffff
|
|
[APUAPC] D1_APC_1: 0xffffffff
|
|
[APUAPC] D1_APC_2: 0xffffffff
|
|
[APUAPC] D1_APC_3: 0xffffffff
|
|
[APUAPC] D1_APC_4: 0x3fff
|
|
[APUAPC] D2_APC_0: 0xffffffff
|
|
[APUAPC] D2_APC_1: 0xffffffff
|
|
[APUAPC] D2_APC_2: 0xffffffff
|
|
[APUAPC] D2_APC_3: 0xffffffff
|
|
[APUAPC] D2_APC_4: 0x3fff
|
|
[APUAPC] D3_APC_0: 0xffffffff
|
|
[APUAPC] D3_APC_1: 0x3fffffff
|
|
[APUAPC] D3_APC_2: 0xfffffff0
|
|
[APUAPC] D3_APC_3: 0xffffffff
|
|
[APUAPC] D3_APC_4: 0x3fff
|
|
[APUAPC] D4_APC_0: 0xffffffff
|
|
[APUAPC] D4_APC_1: 0xffffffff
|
|
[APUAPC] D4_APC_2: 0xffffffff
|
|
[APUAPC] D4_APC_3: 0xffffffff
|
|
[APUAPC] D4_APC_4: 0x3fff
|
|
[APUAPC] D5_APC_0: 0xffffffff
|
|
[APUAPC] D5_APC_1: 0xffffffff
|
|
[APUAPC] D5_APC_2: 0xfffff00f
|
|
[APUAPC] D5_APC_3: 0xffffffff
|
|
[APUAPC] D5_APC_4: 0x3fff
|
|
[APUAPC] D6_APC_0: 0xffffffff
|
|
[APUAPC] D6_APC_1: 0xffffffff
|
|
[APUAPC] D6_APC_2: 0xffffffff
|
|
[APUAPC] D6_APC_3: 0xffffffff
|
|
[APUAPC] D6_APC_4: 0x3fff
|
|
[APUAPC] D7_APC_0: 0xffffffff
|
|
[APUAPC] D7_APC_1: 0xffffffff
|
|
[APUAPC] D7_APC_2: 0xffffffff
|
|
[APUAPC] D7_APC_3: 0xffffffff
|
|
[APUAPC] D7_APC_4: 0x3fff
|
|
[APUAPC] D8_APC_0: 0xffffffff
|
|
[APUAPC] D8_APC_1: 0xffffffff
|
|
[APUAPC] D8_APC_2: 0xffffffff
|
|
[APUAPC] D8_APC_3: 0xffffffff
|
|
[APUAPC] D8_APC_4: 0x3fff
|
|
[APUAPC] D9_APC_0: 0xffffffff
|
|
[APUAPC] D9_APC_1: 0xffffffff
|
|
[APUAPC] D9_APC_2: 0xffffffff
|
|
[APUAPC] D9_APC_3: 0xffffffff
|
|
[APUAPC] D9_APC_4: 0x3fff
|
|
[APUAPC] D10_APC_0: 0xffffffff
|
|
[APUAPC] D10_APC_1: 0xffffffff
|
|
[APUAPC] D10_APC_2: 0xffffffff
|
|
[APUAPC] D10_APC_3: 0xffffffff
|
|
[APUAPC] D10_APC_4: 0x3fff
|
|
[APUAPC] D11_APC_0: 0xffffffff
|
|
[APUAPC] D11_APC_1: 0xffffffff
|
|
[APUAPC] D11_APC_2: 0xffffffff
|
|
[APUAPC] D11_APC_3: 0xffffffff
|
|
[APUAPC] D11_APC_4: 0x3fff
|
|
[APUAPC] D12_APC_0: 0xffffffff
|
|
[APUAPC] D12_APC_1: 0xffffffff
|
|
[APUAPC] D12_APC_2: 0xffffffff
|
|
[APUAPC] D12_APC_3: 0xffffffff
|
|
[APUAPC] D12_APC_4: 0x3fff
|
|
[APUAPC] D13_APC_0: 0xffffffff
|
|
[APUAPC] D13_APC_1: 0xffffffff
|
|
[APUAPC] D13_APC_2: 0xffffffff
|
|
[APUAPC] D13_APC_3: 0xffffffff
|
|
[APUAPC] D13_APC_4: 0x3fff
|
|
[APUAPC] D14_APC_0: 0xffffffff
|
|
[APUAPC] D14_APC_1: 0xffffffff
|
|
[APUAPC] D14_APC_2: 0xffffffff
|
|
[APUAPC] D14_APC_3: 0xffffffff
|
|
[APUAPC] D14_APC_4: 0x3fff
|
|
[APUAPC] D15_APC_0: 0xffffffff
|
|
[APUAPC] D15_APC_1: 0xffffffff
|
|
[APUAPC] D15_APC_2: 0xffffffff
|
|
[APUAPC] D15_APC_3: 0xffffffff
|
|
[APUAPC] D15_APC_4: 0x3fff
|
|
[APUAPC] APC_CON: 0x4
|
|
[NOCDAPC] D0_APC_0: 0x0
|
|
[NOCDAPC] D1_APC_0: 0x3fffffff
|
|
[NOCDAPC] D2_APC_0: 0x3fffffff
|
|
[NOCDAPC] D3_APC_0: 0x3fffffff
|
|
[NOCDAPC] D4_APC_0: 0x3fffffff
|
|
[NOCDAPC] D5_APC_0: 0x3fffffff
|
|
[NOCDAPC] D6_APC_0: 0x3fffffff
|
|
[NOCDAPC] D7_APC_0: 0x3fffffff
|
|
[NOCDAPC] D8_APC_0: 0x3fffffff
|
|
[NOCDAPC] D9_APC_0: 0x3fffffff
|
|
[NOCDAPC] D10_APC_0: 0x3fffffff
|
|
[NOCDAPC] D11_APC_0: 0x3fffffff
|
|
[NOCDAPC] D12_APC_0: 0x3fffffff
|
|
[NOCDAPC] D13_APC_0: 0x3fffffff
|
|
[NOCDAPC] D14_APC_0: 0x3fffffff
|
|
[NOCDAPC] D15_APC_0: 0x3fffffff
|
|
[NOCDAPC] APC_CON: 0x4
|
|
[APUAPC] start_apusys_devapc done
|
|
APU_MBOX 0x190000b0 = 0x10001
|
|
APU_MBOX 0x190001b0 = 0x10001
|
|
APU_MBOX 0x190002b0 = 0x10001
|
|
APU_MBOX 0x190003b0 = 0x10001
|
|
APU_MBOX 0x190004b0 = 0x10001
|
|
APU_MBOX 0x190005b0 = 0x10001
|
|
APU_MBOX 0x190006b0 = 0x10001
|
|
APU_MBOX 0x190007b0 = 0x10001
|
|
CBFS: Found 'mcupm.bin' @0x36980 size 0xf5ef in mcache @0xfffdd180
|
|
read SPI 0x5b89b4 0xf5ef: 5390 us, 11680 KB/s, 93.440 Mbps
|
|
mtk_init_mcu: Loaded (and reset) mcupm.bin in 26 msecs (124800 bytes)
|
|
CBFS: Found 'sspm.bin' @0x45fc0 size 0xc3fe in mcache @0xfffdd1b4
|
|
read SPI 0x5c7ff4 0xc3fe: 4267 us, 11758 KB/s, 94.064 Mbps
|
|
mtk_init_mcu: Loaded (and reset) sspm.bin in 23 msecs (137348 bytes)
|
|
dfd_init: enable DFD (Design For Debug)
|
|
hdmi_low_power_setting: Enable HDMI low power setting
|
|
CPU_CLUSTER: 0 init finished in 540 msecs
|
|
PCI: 01:00.0 init
|
|
PCI: 01:00.0 init finished in 0 msecs
|
|
Devices initialized
|
|
Show all devs... After init.
|
|
Root Device: enabled 1
|
|
CPU_CLUSTER: 0: enabled 1
|
|
DOMAIN: 0000: enabled 1
|
|
PCI: 00:00.0: enabled 1
|
|
PCI: 01:00.0: enabled 1
|
|
BS: BS_DEV_INIT run times (exec / console): 513 / 1130 ms
|
|
FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
|
|
ELOG: NV offset 0x57f000 size 0x1000
|
|
read SPI 0x57f000 0x1000: 383 us, 10694 KB/s, 85.552 Mbps
|
|
ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
|
|
ELOG: Event(17) added with size 13 at 2023-08-29 19:06:55 UTC
|
|
out: cmd=0x121: 03 db 21 01 00 00 00 00
|
|
in-header: 03 5f 00 00 2c 00 00 00
|
|
in-data: 94 c0 00 00 00 00 00 00 0a 04 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
VB2:vb2api_get_fw_boot_info() boot_mode=`Developer`
|
|
VB2:vb2api_get_fw_boot_info() fw_tried=`B` fw_try_count=0 fw_prev_tried=`B` fw_prev_result=`Unknown`.
|
|
ELOG: Event(B7) added with size 11 at 2023-08-29 19:06:55 UTC
|
|
BS: BS_POST_DEVICE entry times (exec / console): 3 / 77 ms
|
|
Finalize devices...
|
|
Devices finalized
|
|
BS: BS_POST_DEVICE run times (exec / console): 0 / 6 ms
|
|
Writing coreboot table at 0xffec4000
|
|
0. 000000000010a000-0000000000113fff: RAMSTAGE
|
|
1. 0000000040000000-00000000400fffff: RAM
|
|
2. 0000000040100000-0000000040334fff: RAMSTAGE
|
|
3. 0000000040335000-00000000545fffff: RAM
|
|
4. 0000000054600000-000000005465ffff: BL31
|
|
5. 0000000054660000-0000000069ffffff: RAM
|
|
6. 000000006a000000-000000006a0fffff: RESERVED
|
|
7. 000000006a100000-00000000ffec3fff: RAM
|
|
8. 00000000ffec4000-00000000ffffffff: CONFIGURATION TABLES
|
|
9. 0000000100000000-000000023fffffff: RAM
|
|
Passing 5 GPIOs to payload:
|
|
NAME | PORT | POLARITY | VALUE
|
|
EC interrupt | 0x00000004 | low | undefined
|
|
SD card detect | 0x00000036 | low | undefined
|
|
EC in RW | 0x00000057 | low | undefined
|
|
TPM interrupt | 0x00000058 | high | undefined
|
|
speaker enable | 0x00000064 | high | undefined
|
|
out: cmd=0x6: 03 f7 06 00 00 00 00 00
|
|
in-header: 03 fa 00 00 02 00 00 00
|
|
in-data: 01 00
|
|
ADC[3]: Raw value=85389 ID=0
|
|
ADC[2]: Raw value=326533 ID=2
|
|
RAM Code: 0x2
|
|
Board ID: 1
|
|
RAM code: 2
|
|
SKU ID: 2
|
|
Wrote coreboot table at: 0xffec4000, 0x3dc bytes, checksum fa2a
|
|
coreboot table: 1012 bytes.
|
|
IMD ROOT 0. 0xfffff000 0x00001000
|
|
IMD SMALL 1. 0xffffe000 0x00001000
|
|
CONSOLE 2. 0xfffde000 0x00020000
|
|
RW MCACHE 3. 0xfffdd000 0x00000320
|
|
RO MCACHE 4. 0xfffdc000 0x00000f24
|
|
FMAP 5. 0xfffdb000 0x00000452
|
|
TIME STAMP 6. 0xfffda000 0x00000910
|
|
VBOOT WORK 7. 0xfffc6000 0x00014000
|
|
RAMOOPS 8. 0xffec6000 0x00100000
|
|
COREBOOT 9. 0xffec4000 0x00002000
|
|
IMD small region:
|
|
IMD ROOT 0. 0xffffec00 0x00000400
|
|
VPD 1. 0xffffe9a0 0x00000259
|
|
MMC STATUS 2. 0xffffe980 0x00000004
|
|
BS: BS_WRITE_TABLES run times (exec / console): 0 / 208 ms
|
|
Probing TPM I2C: done! DID_VID 0x00281ae0
|
|
Locality already claimed
|
|
cr50 TPM 2.0 (i2c 3:0x50 id 0x28)
|
|
Checking cr50 for pending updates
|
|
Reading cr50 TPM mode
|
|
BS: BS_PAYLOAD_LOAD entry times (exec / console): 18 / 21 ms
|
|
CBFS: Found 'fallback/payload' @0x9a080 size 0x1dd76 in mcache @0xfffdd2f0
|
|
read SPI 0x61c0ac 0x1dd76: 10450 us, 11696 KB/s, 93.568 Mbps
|
|
Checking segment from ROM address 0x40100000
|
|
Checking segment from ROM address 0x4010001c
|
|
Loading segment from ROM address 0x40100000
|
|
code (compression=1)
|
|
New segment dstaddr 0xf1000000 memsize 0x2197540 srcaddr 0x40100038 filesize 0x1dd3e
|
|
Loading Segment: addr: 0xf1000000 memsz: 0x0000000002197540 filesz: 0x000000000001dd3e
|
|
using LZMA
|
|
[ 0xf1000000, f1046960, 0xf3197540) <- 40100038
|
|
Clearing Segment: addr: 0x00000000f1046960 memsz: 0x0000000002150be0
|
|
Loading segment from ROM address 0x4010001c
|
|
Entry Point 0xf1000000
|
|
Loaded segments
|
|
BS: BS_PAYLOAD_LOAD run times (exec / console): 29 / 80 ms
|
|
Jumping to boot code at 0xf1000000(0xffec4000)
|
|
CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c670, stack used: 2448 bytes
|
|
CBFS: Found 'fallback/bl31' @0x6f800 size 0x77fb in mcache @0xfffdd274
|
|
read SPI 0x5f1828 0x77fb: 2628 us, 11687 KB/s, 93.496 Mbps
|
|
Checking segment from ROM address 0x40100000
|
|
Checking segment from ROM address 0x4010001c
|
|
Loading segment from ROM address 0x40100000
|
|
code (compression=1)
|
|
New segment dstaddr 0x54601000 memsize 0x2c000 srcaddr 0x40100038 filesize 0x77c3
|
|
Loading Segment: addr: 0x54601000 memsz: 0x000000000002c000 filesz: 0x00000000000077c3
|
|
using LZMA
|
|
[ 0x54601000, 54613c48, 0x5462d000) <- 40100038
|
|
Clearing Segment: addr: 0x0000000054613c48 memsz: 0x00000000000193b8
|
|
Loading segment from ROM address 0x4010001c
|
|
Entry Point 0x54601000
|
|
Loaded segments
|
|
NOTICE: MT8195 bl31_setup
|
|
NOTICE: BL31: v2.9(debug):
|
|
NOTICE: BL31: Built : Tue Aug 29 18:58:05 UTC 2023
|
|
INFO: region 0:
|
|
INFO: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
|
|
INFO: region 1:
|
|
INFO: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
|
|
INFO: region 2:
|
|
INFO: sa:0x1000, ea:0x1140, apc0: 0xb6d168 apc1: 0xb6db6d
|
|
INFO: region 3:
|
|
INFO: sa:0x2000, ea:0x210f, apc0: 0xb68b68 apc1: 0xb6db6d
|
|
INFO: region 4:
|
|
INFO: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
|
|
INFO: region 5:
|
|
INFO: sa:0x0, ea:0x1bfff, apc0: 0xb6db68 apc1: 0xb6db6d
|
|
INFO: region 6:
|
|
INFO: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
|
|
INFO: region 7:
|
|
INFO: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
|
|
INFO: GICv3 without legacy support detected.
|
|
INFO: ARM GICv3 driver initialized in EL3
|
|
INFO: Maximum SPI INTID supported: 895
|
|
INFO: [mt_systimer_init] systimer initialization
|
|
NOTICE: MT8195 spm_boot_init
|
|
INFO: BL31: Initializing runtime services
|
|
INFO: BL31: cortex_a55: CPU workaround for 1530923 was applied
|
|
INFO: SPM: enable CPC mode
|
|
INFO: mcdi ready for mcusys-off-idle and system suspend
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INFO: BL31: Preparing for EL3 exit to normal world
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INFO: Entry point address = 0xf1000000
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INFO: SPSR = 0x8
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Starting depthcharge on Dojo...
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Looking for NVMe Controller 0xf1193a78 @ 01:00:00
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Wipe memory regions:
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[0x00000040000000, 0x00000054600000)
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[0x00000054660000, 0x0000006a000000)
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[0x0000006a100000, 0x000000f1000000)
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[0x000000f3197540, 0x000000ffec4000)
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[0x00000100000000, 0x00000240000000)
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Initializing XHCI USB controller at 0x11200000.
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ec_init: CrosEC protocol v3 supported (256, 248)
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cr50 TPM 2.0 (i2c 0x50 id 0x00281ae0)
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tpm_get_response: command 0x14e, return code 0x0
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vb2api_kernel_phase1: This is developer-signed firmware.
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vb2api_kernel_phase2: GBB flags are 0x0
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Trying to locate 'ecrw.hash' in CBFS
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CBFS: Found 'ecrw.hash' @0x9a000 size 0x20 in mcache @0xfffdd2cc
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check_ec_hash: Hexp RW(active): 0d7701488653db5de75fcb49b0456d97e7f31642c230fb2c5fb7b5afd0b9cc75
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check_ec_hash: Hmir: 0d7701488653db5de75fcb49b0456d97e7f31642c230fb2c5fb7b5afd0b9cc75
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check_ec_hash: Heff RW(active): 0d7701488653db5de75fcb49b0456d97e7f31642c230fb2c5fb7b5afd0b9cc75
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sync_ec: select_rw=RW(active)
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CBFS: Found 'locales' @0x343340 size 0x96 in mcache @0xfffdce54
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get_locale_data: Supported locales: en bn ca da de et es es-419 fil fr hr id it lv lt hu ms nl nb pl pt-PT pt-BR ro sk sl fi sv vi tr cs el bg ru sr uk he(rtl) ar(rtl) fa(rtl) mr hi gu ta te kn ml th zh-CN zh-TW ja ko (50 locales)
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ui_loop_impl: <Developer mode> menu item <Boot from internal disk>
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ui_display: screen=0x300, locale=0, selected_item=2, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=0, current_page=0, error=0x0
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CBGFX: cbgfx initialized: screen:width=1920, height=1080, offset=0 canvas:width=1080, height=1080, offset=420
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load_archive: Loading vbgfx.bin
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CBFS: Found 'vbgfx.bin' @0x343440 size 0x6706 in mcache @0xfffdce84
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load_archive: Loading locale_en.bin
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CBFS: Found 'locale_en.bin' @0xf7240 size 0xaf5f in mcache @0xfffdc510
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load_archive: Loading rw_locale_en.bin
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CBFS: 'rw_locale_en.bin' not found.
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load_archive: Failed to load rw_locale_en.bin (dir: 0x0, size: 0)
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load_archive: Loading font.bin
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CBFS: Found 'font.bin' @0x82340 size 0x17c3 in mcache @0xfffdc31c
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Error getting next MKBP event (-2)
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ui_menu_select: Menu item <Boot from internal disk> run action
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Initializing NVMe controller 144d:a809
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NVMe Cap CSS not NVMe (CSS=7f.
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Unsupported NVMe controller found
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Updating storage controller failed.
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MMC did not respond to voltage select!
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Updating storage controller failed.
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ui_developer_mode_boot_internal_action: ERROR: Failed to boot from internal disk: 0x100b3000
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ui_loop_impl: <Developer mode> menu item <Boot from internal disk>
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ui_display: screen=0x300, locale=0, selected_item=2, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=1, current_page=0, error=0x6
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ui_display: Something went wrong booting from internal disk.
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View firmware log for details.
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ui_loop_impl: <Developer mode> menu item <Boot from internal disk>
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ui_display: screen=0x300, locale=0, selected_item=2, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=1, current_page=0, error=0x0
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ui_menu_navigation_action: Pressed key 0x3, trusted? 1
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ui_menu_navigation_action: Pressed key 0x3, trusted? 1
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ui_menu_navigation_action: Pressed key 0x3, trusted? 1
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ui_loop_impl: <Developer mode> menu item <Boot from external disk>
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ui_display: screen=0x300, locale=0, selected_item=3, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=1, current_page=0, error=0x0
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ui_menu_select: Menu item <Boot from external disk> run action
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ui_developer_mode_boot_external_action: ERROR: Dev mode external boot not allowed
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ui_loop_impl: <Developer mode> menu item <Boot from external disk>
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ui_display: screen=0x300, locale=0, selected_item=3, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=1, current_page=0, error=0x7
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ui_display: Booting from an external disk is disabled. For more
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info, visit: google.com/chromeos/devmode
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ui_loop_impl: <Developer mode> menu item <Boot from external disk>
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ui_display: screen=0x300, locale=0, selected_item=3, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=1, current_page=0, error=0x0
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ui_loop_impl: <Developer mode> menu item <Boot from internal disk>
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ui_display: screen=0x300, locale=0, selected_item=2, disabled_item_mask=0x0, hidden_item_mask=0x10, timer_disabled=1, current_page=0, error=0x0
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