Project

General

Profile

Actions

Bug #386

closed

ASUS P8Z77-V LX2 - Raminit issue at second boot with two 8GiB DIMMs - bootloop

Added by gzz5f gzz5f over 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
High
Assignee:
-
Category:
board support
Target version:
Start date:
06/05/2022
Due date:
% Done:

0%

Estimated time:
Affected versions:
Needs backport to:
Affected hardware:
ASUS P8Z77-V LX2
Affected OS:
all

Description

I build coreboot today for the ASUS P8Z77-V LX2 and used the latest coreboot master code.

The 2 8GiB DIMMs are working fine at first boot. You can start computer, install from a live media the OS and so on. But at the second boot it failes boot forever and its bootooping. It does not make a change if i boot for a second until SeaBIOS output and then turn off the computer or use the computer for longer time. The second boot is always broken.
Workaround 1: Remove one of the two 8GiB DIMMs. Then the computer also starts fine after a reboot.
Workaround 2: Install two 4GiB DIMMs instead of two 8GiB DIMMs. Then the computer also starts fine after reboot.
Workaround 3: At every boot boot for a second with one DIMM. Turn off the computer, insert the second DIMM and start it again.

kmalkki told me to rebuid the image with DEBUG_RAM_SETUP=y

I then build a second image, with DEBUG_RAM_SETUP=y.
The logfile contains the first successfull boot (created with Workaround 3), the poweroff and the poweron with the bootloop. I have let it bootloop few times before turned off the PSU.


Files

coreboot_logfie.txt (197 KB) coreboot_logfie.txt gzz5f gzz5f, 06/05/2022 04:06 PM
coreboot_logfile_cleaned.txt (160 KB) coreboot_logfile_cleaned.txt stripped ANSI escapes Kyösti Mälkki, 06/05/2022 04:32 PM
Actions #2

Updated by Kyösti Mälkki over 2 years ago

I build coreboot today for the ASUS P8Z77-V LX2 and used the latest coreboot master code.

The 2 8GiB DIMMs are working fine at first boot.

I think only 8 GiB of RAM was available at first boot.

One of the DIMMs has SPD CRC error, and while they have matching part number, timing parameters are different.

[DEBUG] SPD probe channel1, slot1
[DEBUG] ERROR: SPD CRC failed!!!

Actions #3

Updated by Martin Roth almost 2 years ago

  • Status changed from New to Closed

No update since Kyösti pointed out the issue in the boot log to indicate that this is anything beyond incompatible dimms. Closing.

Actions

Also available in: Atom PDF