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Bug #386 » coreboot_logfie.txt

gzz5f gzz5f, 06/05/2022 04:06 PM

 
picocom v3.1

port is : /dev/ttyUSB0
flowcontrol : none
baudrate is : 115200
parity is : none
databits are : 8
stopbits are : 1
escape is : C-a
local echo is : no
noinit is : no
noreset is : no
hangup is : no
nolock is : no
send_cmd is : sz -vv
receive_cmd is : rz -vv -E
imap is :
omap is :
emap is : crcrlf,delbs,
logfile is : none
initstring : none
exit_after is : not set
exit is : no

Type [C-a] [C-h] to see available commands
Terminal ready


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Stored timings CRC16 mismatch.
[DEBUG] ECC supported: no ECC forced: no
[INFO ] ECC RAM unsupported.
[DEBUG] SPD probe channel0, slot0
[DEBUG] Not a DDR3 SPD!
[DEBUG] No valid XMP profile found.
[DEBUG] Not a DDR3 SPD!
[DEBUG] SPD probe channel0, slot1
[DEBUG] Revision : 11
[DEBUG] Type : b
[DEBUG] Key : 2
[DEBUG] Banks : 8
[DEBUG] Capacity : 4 Gb
[DEBUG] Supported voltages : 1.5V
[DEBUG] SDRAM width : 8
[DEBUG] Bus extension : 0 bits
[DEBUG] Bus width : 64
[DEBUG] FTB timings : yes
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
[DEBUG] Thermal features : PASR ext_temp_range
[DEBUG] Thermal sensor : no
[DEBUG] Standard SDRAM : yes
[DEBUG] Rank1 Address bits : mirrored
[DEBUG] DIMM Reference card: B
[DEBUG] Manufacturer ID : 9e02
[DEBUG] Part number : CMD16GX3M2A1866C
[DEBUG] XMP Profile : 1
[DEBUG] Max DIMMs/channel : 1
[DEBUG] XMP Revision : 1.3
[DEBUG] Requested voltage : 1500 mV
[INFO ] Row addr bits : 16
[INFO ] Column addr bits : 10
[INFO ] Number of ranks : 2
[INFO ] DIMM Capacity : 8192 MB
[INFO ] CAS latencies : 6 10
[INFO ] tCKmin : 1.054 ns
[INFO ] tAAmin : 10.546 ns
[INFO ] tWRmin : 14.765 ns
[INFO ] tRCDmin : 11.601 ns
[INFO ] tRRDmin : 7.382 ns
[INFO ] tRPmin : 10.546 ns
[INFO ] tRASmin : 31.570 ns
[INFO ] tRCmin : 49.851 ns
[INFO ] tRFCmin : 255.937 ns
[INFO ] tWTRmin : 7.382 ns
[INFO ] tRTPmin : 7.382 ns
[INFO ] tFAWmin : 36.914 ns
[INFO ] tCWLmin : 8.437 ns
[INFO ] tCMDmin : 2
[DEBUG] channel[0] rankmap = 0xc
[DEBUG] SPD probe channel1, slot0
[DEBUG] Not a DDR3 SPD!
[DEBUG] No valid XMP profile found.
[DEBUG] Not a DDR3 SPD!
[DEBUG] SPD probe channel1, slot1
[DEBUG] ERROR: SPD CRC failed!!!
[DEBUG] Revision : 0
[DEBUG] Type : b
[DEBUG] Key : 2
[DEBUG] Banks : 8
[DEBUG] Capacity : 4 Gb
[DEBUG] Supported voltages : 1.5V
[DEBUG] SDRAM width : 8
[DEBUG] Bus extension : 0 bits
[DEBUG] Bus width : 64
[DEBUG] FTB timings : no
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
[DEBUG] Thermal features : PASR ext_temp_range
[DEBUG] Thermal sensor : no
[DEBUG] Standard SDRAM : yes
[DEBUG] Rank1 Address bits : mirrored
[DEBUG] DIMM Reference card: B
[DEBUG] Manufacturer ID : 9e02
[DEBUG] Part number : CMD16GX3M2A1866C
[INFO ] Row addr bits : 16
[INFO ] Column addr bits : 10
[INFO ] Number of ranks : 2
[INFO ] DIMM Capacity : 8192 MB
[INFO ] CAS latencies : 6 7 9
[INFO ] tCKmin : 1.500 ns
[INFO ] tAAmin : 13.125 ns
[INFO ] tWRmin : 15.000 ns
[INFO ] tRCDmin : 13.125 ns
[INFO ] tRRDmin : 6.000 ns
[INFO ] tRPmin : 13.125 ns
[INFO ] tRASmin : 36.000 ns
[INFO ] tRCmin : 48.125 ns
[INFO ] tRFCmin : 260.000 ns
[INFO ] tWTRmin : 7.500 ns
[INFO ] tRTPmin : 7.500 ns
[INFO ] tFAWmin : 30.000 ns
[DEBUG] channel[1] rankmap = 0xc
[DEBUG] ECC is disabled
[DEBUG] Starting Ivy Bridge RAM training (full initialization).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Trying CAS 7, tCK 480.
[DEBUG] Trying CAS 6, tCK 640.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 400 MHz
[DEBUG] Selected CAS latency : 6T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 400 MHz
[DEBUG] Selected CWL latency : 4T
[DEBUG] Selected tRCD : 6T
[DEBUG] Selected tRP : 6T
[DEBUG] Selected tRAS : 15T
[DEBUG] Selected tWR : 6T
[DEBUG] Selected tFAW : 15T
[DEBUG] Selected tRRD : 3T
[DEBUG] Selected tRTP : 3T
[DEBUG] Selected tWTR : 3T
[DEBUG] Selected tRFC : 104T
[DEBUG] XOVER CLK [c14] = c000000
[DEBUG] XOVER CMD [320c] = 4004000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = f4666
[DEBUG] RAP [4004] = c60f3333
[DEBUG] OTHP [400c] = 646a
[DEBUG] OTHP [400c] = 646a
[DEBUG] REFI [4298] = 36680c30
[DEBUG] SRFTP [42a4] = 41fc4200
[DEBUG] DBP [4400] = f4666
[DEBUG] RAP [4404] = c60f3333
[DEBUG] OTHP [440c] = 646a
[DEBUG] OTHP [440c] = 646a
[DEBUG] REFI [4698] = 36680c30
[DEBUG] SRFTP [46a4] = 41fc4200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 4
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 4
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 3
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] Done jedec reset
[DEBUG] Done MRS commands
[DEBUG] rcven: 0, 2, 0: 113- 16- 48
[DEBUG] rcven: 0, 2, 1: 121- 24- 56
[DEBUG] rcven: 0, 2, 2: 3- 34- 65
[DEBUG] rcven: 0, 2, 3: 11- 42- 74
[DEBUG] rcven: 0, 2, 4: 23- 54- 85
[DEBUG] rcven: 0, 2, 5: 30- 62- 94
[DEBUG] rcven: 0, 2, 6: 38- 69- 101
[DEBUG] rcven: 0, 2, 7: 44- 75- 107
[DEBUG] 4024++;
[DEBUG] 4028++;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] lane 0: -3, 2
[DEBUG] Aval: 0, 2, 0: 48
[DEBUG] lane 1: 0, 3
[DEBUG] Aval: 0, 2, 1: 57
[DEBUG] lane 2: -1, 3
[DEBUG] Aval: 0, 2, 2: 66
[DEBUG] lane 3: -2, 3
[DEBUG] Aval: 0, 2, 3: 74
[DEBUG] lane 4: -2, 4
[DEBUG] Aval: 0, 2, 4: 86
[DEBUG] lane 5: -3, 3
[DEBUG] Aval: 0, 2, 5: 94
[DEBUG] lane 6: -4, 3
[DEBUG] Aval: 0, 2, 6: 101
[DEBUG] lane 7: -1, 3
[DEBUG] Aval: 0, 2, 7: 108
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4028 -= 0;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4/8: 0, 2, 34, 5
[DEBUG] final results:
[DEBUG] Aval: 0, 2, 0: 48
[DEBUG] Aval: 0, 2, 1: 57
[DEBUG] Aval: 0, 2, 2: 66
[DEBUG] Aval: 0, 2, 3: 74
[DEBUG] Aval: 0, 2, 4: 86
[DEBUG] Aval: 0, 2, 5: 94
[DEBUG] Aval: 0, 2, 6: 101
[DEBUG] Aval: 0, 2, 7: 108
[DEBUG] rcven: 0, 3, 0: 112- 16- 48
[DEBUG] rcven: 0, 3, 1: 121- 24- 56
[DEBUG] rcven: 0, 3, 2: 2- 34- 66
[DEBUG] rcven: 0, 3, 3: 12- 43- 74
[DEBUG] rcven: 0, 3, 4: 24- 54- 85
[DEBUG] rcven: 0, 3, 5: 28- 61- 95
[DEBUG] rcven: 0, 3, 6: 38- 69- 100
[DEBUG] rcven: 0, 3, 7: 44- 76- 108
[DEBUG] 4024++;
[DEBUG] 4028++;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] lane 0: -3, 2
[DEBUG] Aval: 0, 3, 0: 48
[DEBUG] lane 1: 0, 3
[DEBUG] Aval: 0, 3, 1: 57
[DEBUG] lane 2: -2, 2
[DEBUG] Aval: 0, 3, 2: 66
[DEBUG] lane 3: -2, 3
[DEBUG] Aval: 0, 3, 3: 74
[DEBUG] lane 4: 0, 5
[DEBUG] Aval: 0, 3, 4: 87
[DEBUG] lane 5: -5, 1
[DEBUG] Aval: 0, 3, 5: 93
[DEBUG] lane 6: -2, 3
[DEBUG] Aval: 0, 3, 6: 100
[DEBUG] lane 7: -2, 3
[DEBUG] Aval: 0, 3, 7: 108
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4028 -= 0;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4/8: 0, 3, 34, 5
[DEBUG] final results:
[DEBUG] Aval: 0, 3, 0: 48
[DEBUG] Aval: 0, 3, 1: 57
[DEBUG] Aval: 0, 3, 2: 66
[DEBUG] Aval: 0, 3, 3: 74
[DEBUG] Aval: 0, 3, 4: 87
[DEBUG] Aval: 0, 3, 5: 93
[DEBUG] Aval: 0, 3, 6: 100
[DEBUG] Aval: 0, 3, 7: 108
[DEBUG] rcven: 1, 2, 0: 125- 29- 62
[DEBUG] rcven: 1, 2, 1: 8- 38- 68
[DEBUG] rcven: 1, 2, 2: 17- 49- 81
[DEBUG] rcven: 1, 2, 3: 26- 57- 89
[DEBUG] rcven: 1, 2, 4: 38- 68- 99
[DEBUG] rcven: 1, 2, 5: 48- 80- 112
[DEBUG] rcven: 1, 2, 6: 52- 84- 116
[DEBUG] rcven: 1, 2, 7: 59- 90- 122
[DEBUG] 4024++;
[DEBUG] 4028++;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] lane 0: -4, 2
[DEBUG] Aval: 1, 2, 0: 61
[DEBUG] lane 1: 2, 5
[DEBUG] Aval: 1, 2, 1: 71
[DEBUG] lane 2: -1, 4
[DEBUG] Aval: 1, 2, 2: 82
[DEBUG] lane 3: -2, 1
[DEBUG] Aval: 1, 2, 3: 89
[DEBUG] lane 4: -2, 4
[DEBUG] Aval: 1, 2, 4: 100
[DEBUG] lane 5: -1, 1
[DEBUG] Aval: 1, 2, 5: 112
[DEBUG] lane 6: -4, 2
[DEBUG] Aval: 1, 2, 6: 115
[DEBUG] lane 7: -2, 2
[DEBUG] Aval: 1, 2, 7: 122
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4028 -= 0;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4/8: 1, 2, 34, 5
[DEBUG] final results:
[DEBUG] Aval: 1, 2, 0: 61
[DEBUG] Aval: 1, 2, 1: 71
[DEBUG] Aval: 1, 2, 2: 82
[DEBUG] Aval: 1, 2, 3: 89
[DEBUG] Aval: 1, 2, 4: 100
[DEBUG] Aval: 1, 2, 5: 112
[DEBUG] Aval: 1, 2, 6: 115
[DEBUG] Aval: 1, 2, 7: 122
[DEBUG] rcven: 1, 3, 0: 127- 30- 62
[DEBUG] rcven: 1, 3, 1: 8- 39- 70
[DEBUG] rcven: 1, 3, 2: 19- 50- 81
[DEBUG] rcven: 1, 3, 3: 28- 58- 89
[DEBUG] rcven: 1, 3, 4: 40- 69- 99
[DEBUG] rcven: 1, 3, 5: 48- 80- 112
[DEBUG] rcven: 1, 3, 6: 53- 85- 117
[DEBUG] rcven: 1, 3, 7: 59- 90- 122
[DEBUG] 4024++;
[DEBUG] 4028++;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] lane 0: -2, 2
[DEBUG] Aval: 1, 3, 0: 62
[DEBUG] lane 1: 0, 3
[DEBUG] Aval: 1, 3, 1: 71
[DEBUG] lane 2: -1, 5
[DEBUG] Aval: 1, 3, 2: 83
[DEBUG] lane 3: -2, 5
[DEBUG] Aval: 1, 3, 3: 90
[DEBUG] lane 4: -2, 5
[DEBUG] Aval: 1, 3, 4: 100
[DEBUG] lane 5: -1, 1
[DEBUG] Aval: 1, 3, 5: 112
[DEBUG] lane 6: -5, 2
[DEBUG] Aval: 1, 3, 6: 116
[DEBUG] lane 7: -2, 5
[DEBUG] Aval: 1, 3, 7: 123
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4028 -= 0;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4/8: 1, 3, 34, 5
[DEBUG] final results:
[DEBUG] Aval: 1, 3, 0: 62
[DEBUG] Aval: 1, 3, 1: 71
[DEBUG] Aval: 1, 3, 2: 83
[DEBUG] Aval: 1, 3, 3: 90
[DEBUG] Aval: 1, 3, 4: 100
[DEBUG] Aval: 1, 3, 5: 112
[DEBUG] Aval: 1, 3, 6: 116
[DEBUG] Aval: 1, 3, 7: 123
[DEBUG] discover falling edges:
[DEBUG] [4eb0] = 300
[DEBUG] eval 0, 2, 0: 32
[DEBUG] eval 0, 2, 1: 32
[DEBUG] eval 0, 2, 2: 32
[DEBUG] eval 0, 2, 3: 34
[DEBUG] eval 0, 2, 4: 33
[DEBUG] eval 0, 2, 5: 32
[DEBUG] eval 0, 2, 6: 33
[DEBUG] eval 0, 2, 7: 31
[DEBUG] eval 0, 3, 0: 32
[DEBUG] eval 0, 3, 1: 32
[DEBUG] eval 0, 3, 2: 32
[DEBUG] eval 0, 3, 3: 34
[DEBUG] eval 0, 3, 4: 34
[DEBUG] eval 0, 3, 5: 32
[DEBUG] eval 0, 3, 6: 33
[DEBUG] eval 0, 3, 7: 31
[DEBUG] eval 1, 2, 0: 33
[DEBUG] eval 1, 2, 1: 36
[DEBUG] eval 1, 2, 2: 36
[DEBUG] eval 1, 2, 3: 35
[DEBUG] eval 1, 2, 4: 37
[DEBUG] eval 1, 2, 5: 33
[DEBUG] eval 1, 2, 6: 38
[DEBUG] eval 1, 2, 7: 35
[DEBUG] eval 1, 3, 0: 33
[DEBUG] eval 1, 3, 1: 34
[DEBUG] eval 1, 3, 2: 36
[DEBUG] eval 1, 3, 3: 35
[DEBUG] eval 1, 3, 4: 38
[DEBUG] eval 1, 3, 5: 33
[DEBUG] eval 1, 3, 6: 38
[DEBUG] eval 1, 3, 7: 34
[DEBUG] discover rising edges:
[DEBUG] [4eb0] = 200
[DEBUG] eval 0, 2, 0: 37
[DEBUG] eval 0, 2, 1: 36
[DEBUG] eval 0, 2, 2: 36
[DEBUG] eval 0, 2, 3: 37
[DEBUG] eval 0, 2, 4: 36
[DEBUG] eval 0, 2, 5: 37
[DEBUG] eval 0, 2, 6: 38
[DEBUG] eval 0, 2, 7: 39
[DEBUG] eval 0, 3, 0: 38
[DEBUG] eval 0, 3, 1: 36
[DEBUG] eval 0, 3, 2: 37
[DEBUG] eval 0, 3, 3: 37
[DEBUG] eval 0, 3, 4: 36
[DEBUG] eval 0, 3, 5: 37
[DEBUG] eval 0, 3, 6: 38
[DEBUG] eval 0, 3, 7: 39
[DEBUG] eval 1, 2, 0: 36
[DEBUG] eval 1, 2, 1: 36
[DEBUG] eval 1, 2, 2: 37
[DEBUG] eval 1, 2, 3: 38
[DEBUG] eval 1, 2, 4: 38
[DEBUG] eval 1, 2, 5: 40
[DEBUG] eval 1, 2, 6: 39
[DEBUG] eval 1, 2, 7: 37
[DEBUG] eval 1, 3, 0: 36
[DEBUG] eval 1, 3, 1: 38
[DEBUG] eval 1, 3, 2: 37
[DEBUG] eval 1, 3, 3: 38
[DEBUG] eval 1, 3, 4: 37
[DEBUG] eval 1, 3, 5: 41
[DEBUG] eval 1, 3, 6: 39
[DEBUG] eval 1, 3, 7: 38
[DEBUG] CPE
[DEBUG] tx_dqs: 0, 2, 0: 58- 90- 123
[DEBUG] tx_dqs: 0, 2, 1: 69- 102- 8
[DEBUG] tx_dqs: 0, 2, 2: 75- 108- 14
[DEBUG] tx_dqs: 0, 2, 3: 83- 116- 21
[DEBUG] tx_dqs: 0, 2, 4: 92- 125- 31
[DEBUG] tx_dqs: 0, 2, 5: 99- 4- 37
[DEBUG] tx_dqs: 0, 2, 6: 105- 10- 43
[DEBUG] tx_dqs: 0, 2, 7: 109- 14- 48
[DEBUG] tx_dqs: 0, 3, 0: 58- 90- 123
[DEBUG] tx_dqs: 0, 3, 1: 69- 102- 8
[DEBUG] tx_dqs: 0, 3, 2: 78- 111- 16
[DEBUG] tx_dqs: 0, 3, 3: 83- 115- 20
[DEBUG] tx_dqs: 0, 3, 4: 93- 126- 31
[DEBUG] tx_dqs: 0, 3, 5: 99- 4- 37
[DEBUG] tx_dqs: 0, 3, 6: 105- 9- 42
[DEBUG] tx_dqs: 0, 3, 7: 109- 14- 48
[DEBUG] tx_dqs: 1, 2, 0: 56- 90- 124
[DEBUG] tx_dqs: 1, 2, 1: 65- 99- 5
[DEBUG] tx_dqs: 1, 2, 2: 74- 107- 13
[DEBUG] tx_dqs: 1, 2, 3: 80- 113- 18
[DEBUG] tx_dqs: 1, 2, 4: 92- 125- 31
[DEBUG] tx_dqs: 1, 2, 5: 94- 127- 32
[DEBUG] tx_dqs: 1, 2, 6: 102- 6- 39
[DEBUG] tx_dqs: 1, 2, 7: 106- 12- 46
[DEBUG] tx_dqs: 1, 3, 0: 56- 90- 124
[DEBUG] tx_dqs: 1, 3, 1: 67- 100- 5
[DEBUG] tx_dqs: 1, 3, 2: 75- 108- 14
[DEBUG] tx_dqs: 1, 3, 3: 81- 115- 22
[DEBUG] tx_dqs: 1, 3, 4: 90- 124- 30
[DEBUG] tx_dqs: 1, 3, 5: 96- 0- 33
[DEBUG] tx_dqs: 1, 3, 6: 100- 5- 39
[DEBUG] tx_dqs: 1, 3, 7: 106- 11- 44
[DEBUG] CPF
[DEBUG] tx_dq: 0, 2, 0: 58- 88- 118
[DEBUG] tx_dq: 0, 2, 1: 4- 34- 64
[DEBUG] tx_dq: 0, 2, 2: 11- 41- 72
[DEBUG] tx_dq: 0, 2, 3: 17- 47- 77
[DEBUG] tx_dq: 0, 2, 4: 26- 56- 86
[DEBUG] tx_dq: 0, 2, 5: 33- 64- 95
[DEBUG] tx_dq: 0, 2, 6: 40- 70- 100
[DEBUG] tx_dq: 0, 2, 7: 41- 71- 101
[DEBUG] tx_dq: 0, 3, 0: 57- 87- 117
[DEBUG] tx_dq: 0, 3, 1: 4- 34- 65
[DEBUG] tx_dq: 0, 3, 2: 12- 42- 73
[DEBUG] tx_dq: 0, 3, 3: 17- 47- 77
[DEBUG] tx_dq: 0, 3, 4: 26- 56- 87
[DEBUG] tx_dq: 0, 3, 5: 33- 64- 95
[DEBUG] tx_dq: 0, 3, 6: 39- 69- 100
[DEBUG] tx_dq: 0, 3, 7: 41- 71- 101
[EMERG] tx_dq write leveling failed: 1, 2, 0
[DEBUG] threshold=2000 min=1 max=4000
[DEBUG] tx_dq: 1, 2, 0: 52- 82- 113
[DEBUG] tx_dq: 1, 2, 1: 0- 31- 62
[DEBUG] tx_dq: 1, 2, 2: 9- 40- 71
[DEBUG] tx_dq: 1, 2, 3: 17- 47- 77
[DEBUG] tx_dq: 1, 2, 4: 25- 55- 86
[DEBUG] tx_dq: 1, 2, 5: 30- 59- 88
[EMERG] tx_dq write leveling failed: 1, 2, 6
[DEBUG] threshold=2000 min=1 max=4000
[DEBUG] tx_dq: 1, 2, 6: 32- 62- 92
[EMERG] tx_dq write leveling failed: 1, 2, 7
[DEBUG] threshold=2000 min=1 max=4000
[DEBUG] tx_dq: 1, 2, 7: 40- 70- 101
[EMERG] tx_dq write leveling failed: 1, 3, 0
[DEBUG] threshold=2000 min=1 max=4000
[DEBUG] tx_dq: 1, 3, 0: 53- 83- 113
[DEBUG] tx_dq: 1, 3, 1: 1- 32- 63
[DEBUG] tx_dq: 1, 3, 2: 9- 40- 71
[DEBUG] tx_dq: 1, 3, 3: 18- 48- 79
[DEBUG] tx_dq: 1, 3, 4: 24- 54- 85
[DEBUG] tx_dq: 1, 3, 5: 32- 61- 90
[DEBUG] tx_dq: 1, 3, 6: 31- 60- 89
[EMERG] tx_dq write leveling failed: 1, 3, 7
[DEBUG] threshold=2000 min=1 max=4000
[DEBUG] tx_dq: 1, 3, 7: 40- 70- 101
[DEBUG] High adjust 0:ffff000000000000
[DEBUG] Bval+: 0, 2, 0, 58 -> 65210
[DEBUG] High adjust 1:ffff000000000000
[DEBUG] Bval+: 0, 2, 1, 69 -> 65221
[DEBUG] High adjust 2:ffff000000000000
[DEBUG] Bval+: 0, 2, 2, 75 -> 65227
[DEBUG] High adjust 3:ffff000000000000
[DEBUG] Bval+: 0, 2, 3, 83 -> 65235
[DEBUG] High adjust 4:ffff000000000000
[DEBUG] Bval+: 0, 2, 4, 92 -> 65244
[DEBUG] High adjust 5:ffff000000000000
[DEBUG] Bval+: 0, 2, 5, 99 -> 65251
[DEBUG] High adjust 6:ffff000000000000
[DEBUG] Bval+: 0, 2, 6, 105 -> 65257
[DEBUG] High adjust 7:ffff000000000000
[DEBUG] Bval+: 0, 2, 7, 109 -> 65261
[DEBUG] High adjust 0:ffff000000000000
[DEBUG] Bval+: 0, 3, 0, 58 -> 65210
[DEBUG] High adjust 1:ffff000000000000
[DEBUG] Bval+: 0, 3, 1, 69 -> 65221
[DEBUG] High adjust 2:ffff000000000000
[DEBUG] Bval+: 0, 3, 2, 78 -> 65230
[DEBUG] High adjust 3:ffff000000000000
[DEBUG] Bval+: 0, 3, 3, 83 -> 65235
[DEBUG] High adjust 4:ffff000000000000
[DEBUG] Bval+: 0, 3, 4, 93 -> 65245
[DEBUG] High adjust 5:ffff000000000000
[DEBUG] Bval+: 0, 3, 5, 99 -> 65251
[DEBUG] High adjust 6:ffff000000000000
[DEBUG] Bval+: 0, 3, 6, 105 -> 65257
[DEBUG] High adjust 7:ffff000000000000
[DEBUG] Bval+: 0, 3, 7, 109 -> 65261
[DEBUG] High adjust 0:ffff000000000000
[DEBUG] Bval+: 1, 2, 0, 56 -> 65208
[DEBUG] High adjust 1:ffff000000000000
[DEBUG] Bval+: 1, 2, 1, 65 -> 65217
[DEBUG] High adjust 2:ffff000000000000
[DEBUG] Bval+: 1, 2, 2, 74 -> 65226
[DEBUG] High adjust 3:ffff000000000000
[DEBUG] Bval+: 1, 2, 3, 80 -> 65232
[DEBUG] High adjust 4:ffff000000000000
[DEBUG] Bval+: 1, 2, 4, 92 -> 65244
[DEBUG] High adjust 5:ffff000000000000
[DEBUG] Bval+: 1, 2, 5, 94 -> 65246
[DEBUG] High adjust 6:ffff000000000000
[DEBUG] Bval+: 1, 2, 6, 102 -> 65254
[DEBUG] High adjust 7:ffff000000000000
[DEBUG] Bval+: 1, 2, 7, 106 -> 65258
[DEBUG] High adjust 0:ffff000000000000
[DEBUG] Bval+: 1, 3, 0, 56 -> 65208
[DEBUG] High adjust 1:ffff000000000000
[DEBUG] Bval+: 1, 3, 1, 67 -> 65219
[DEBUG] High adjust 2:ffff000000000000
[DEBUG] Bval+: 1, 3, 2, 75 -> 65227
[DEBUG] High adjust 3:ffff000000000000
[DEBUG] Bval+: 1, 3, 3, 81 -> 65233
[DEBUG] High adjust 4:ffff000000000000
[DEBUG] Bval+: 1, 3, 4, 90 -> 65242
[DEBUG] High adjust 5:ffff000000000000
[DEBUG] Bval+: 1, 3, 5, 96 -> 65248
[DEBUG] High adjust 6:ffff000000000000
[DEBUG] Bval+: 1, 3, 6, 100 -> 65252
[DEBUG] High adjust 7:ffff000000000000
[DEBUG] Bval+: 1, 3, 7, 106 -> 65258
[DEBUG] CP5a
[DEBUG] CP5b
[DEBUG] Trying cmd_stretch 2 on channel 0
[DEBUG] cmd_stretch: 0, 2: 0- 127- 255
[EMERG] Command training failed: 0
[ERROR] RAM training failed, trying fallback.
[DEBUG] Disable failing channel.
[DEBUG] ECC supported: no ECC forced: no
[DEBUG] SPD probe channel0, slot0
[DEBUG] Not a DDR3 SPD!
[DEBUG] No valid XMP profile found.
[DEBUG] Not a DDR3 SPD!
[DEBUG] SPD probe channel0, slot1
[DEBUG] Revision : 11
[DEBUG] Type : b
[DEBUG] Key : 2
[DEBUG] Banks : 8
[DEBUG] Capacity : 4 Gb
[DEBUG] Supporterd: B
[DEBUG] Manufacturer ID : 9e02
[DEBUG] Part number : CMD16GX3M2A1866C
[DEBUG] XMP Profile : 1
[DEBUG] Max DIMMs/channel : 1
[DEBUG] XMP Revision : 1.3
[DEBUG] Requested voltage : 1500 mV
[INFO ] Row addr bits : 16
[INFO ] Column addr bits : 10
[INFO ] Number of ranks : 2
[INFO ] DIMM Capacity : 8192 MB
[INFO ] CAS latencies : 6 10
[INFO ] tCKmin : 1.054 ns
[INFO ] tAAmin : 10.546 ns
[INFO ] tWRmin : 14.765 ns
[INFO ] tRCDmin : 11.601 ns
[INFO ] tRRDmin : 7.382 ns
[INFO ] tRPmin : 10.546 ns
[INFO ] tRASmin : 31.570 ns
[INFO ] tRCmin : 49.851 ns
[INFO ] tRFCmin : 255.937 ns
[INFO ] tWTRmin : 7.382 ns
[INFO ] tRTPmin : 7.382 ns
[INFO ] tFAWmin : 36.914 ns
[INFO ] tCWLmin : 8.437 ns
[INFO ] tCMDmin : 2
[DEBUG] channel[0] rankmap = 0xc
[DEBUG] SPD probe channel1, slot0
[DEBUG] Not a DDR3 SPD!
[DEBUG] No valid XMP profile found.
[DEBUG] Not a DDR3 SPD!
[DEBUG] SPD probe channel1, slot1
[DEBUG] ERROR: SPD CRC failed!!!
[DEBUG] Revision : 0
[DEBUG] Type : b
[DEBUG] Key : 2
[DEBUG] Banks : 8
[DEBUG] Capacity : 4 Gb
[DEBUG] Supported voltages : 1.5V
[DEBUG] SDRAM width : 8
[DEBUG] Bus extension : 0 bits
[DEBUG] Bus width : 64
[DEBUG] FTB timings : no
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
[DEBUG] Thermal features : PASR ext_temp_range
[DEBUG] Thermal sensor : no
[DEBUG] Standard SDRAM : yes
[DEBUG] Rank1 Address bits : mirrored
[DEBUG] DIMM Reference card: B
[DEBUG] Manufacturer ID : 9e02
[DEBUG] Part number : CMD16GX3M2A1866C
[INFO ] Row addr bits : 16
[INFO ] Column addr bits : 10
[INFO ] Number of ranks : 2
[INFO ] DIMM Capacity : 8192 MB
[INFO ] CAS latencies : 6 7 9
[INFO ] tCKmin : 1.500 ns
[INFO ] tAAmin : 13.125 ns
[INFO ] tWRmin : 15.000 ns
[INFO ] tRCDmin : 13.125 ns
[INFO ] tRRDmin : 6.000 ns
[INFO ] tRPmin : 13.125 ns
[INFO ] tRASmin : 36.000 ns
[INFO ] tRCmin : 48.125 ns
[INFO ] tRFCmin : 260.000 ns
[INFO ] tWTRmin : 7.500 ns
[INFO ] tRTPmin : 7.500 ns
[INFO ] tFAWmin : 30.000 ns
[DEBUG] channel[1] rankmap = 0xc
[DEBUG] ECC is disabled
[DEBUG] Starting Ivy Bridge RAM training (full initialization).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] Selected CWL latency : 7T
[DEBUG] Selected tRCD : 9T
[DEBUG] Selected tRP : 9T
[DEBUG] Selected tRAS : 24T
[DEBUG] Selected tWR : 10T
[DEBUG] Selected tFAW : 20T
[DEBUG] Selected tRRD : 4T
[DEBUG] Selected tRTP : 5T
[DEBUG] Selected tWTR : 5T
[DEBUG] Selected tRFC : 174T
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] Done jedec reset
[DEBUG] Done MRS commands
[DEBUG] rcven: 1, 2, 0: 7- 38- 70
[DEBUG] rcven: 1, 2, 1: 17- 47- 77
[DEBUG] rcven: 1, 2, 2: 29- 60- 92
[DEBUG] rcven: 1, 2, 3: 38- 69- 100
[DEBUG] rcven: 1, 2, 4: 47- 78- 110
[DEBUG] rcven: 1, 2, 5: 57- 88- 120
[DEBUG] rcven: 1, 2, 6: 63- 94- 126
[DEBUG] rcven: 1, 2, 7: 69- 99- 2
[DEBUG] 4024++;
[DEBUG] 4028++;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] lane 0: -4, 2
[DEBUG] Aval: 1, 2, 0: 69
[DEBUG] lane 1: 2, 7
[DEBUG] Aval: 1, 2, 1: 81
[DEBUG] lane 2: -4, 3
[DEBUG] Aval: 1, 2, 2: 92
[DEBUG] lane 3: -5, 2
[DEBUG] Aval: 1, 2, 3: 99
[DEBUG] lane 4: -4, 1
[DEBUG] Aval: 1, 2, 4: 109
[DEBUG] lane 5: -1, 2
[DEBUG] Aval: 1, 2, 5: 120
[DEBUG] lane 6: -5, 2
[DEBUG] Aval: 1, 2, 6: 125
[DEBUG] lane 7: -3, 4
[DEBUG] Aval: 1, 2, 7: 130
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4028 -= 1;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4/8: 1, 2, 40, 4
[DEBUG] final results:
[DEBUG] Aval: 1, 2, 0: 5
[DEBUG] Aval: 1, 2, 1: 17
[DEBUG] Aval: 1, 2, 2: 28
[DEBUG] Aval: 1, 2, 3: 35
[DEBUG] Aval: 1, 2, 4: 45
[DEBUG] Aval: 1, 2, 5: 56
[DEBUG] Aval: 1, 2, 6: 61
[DEBUG] Aval: 1, 2, 7: 66
[DEBUG] rcven: 1, 3, 0: 8- 39- 70
[DEBUG] rcven: 1, 3, 1: 19- 49- 80
[DEBUG] rcven: 1, 3, 2: 31- 62- 93
[DEBUG] rcven: 1, 3, 3: 39- 70- 102
[DEBUG] rcven: 1, 3, 4: 48- 79- 111
[DEBUG] rcven: 1, 3, 5: 60- 91- 122
[DEBUG] rcven: 1, 3, 6: 64- 96- 0
[DEBUG] rcven: 1, 3, 7: 71- 101- 4
[DEBUG] 4024++;
[DEBUG] 4028++;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 -= 2;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] lane 0: -1, 3
[DEBUG] Aval: 1, 3, 0: 71
[DEBUG] lane 1: -1, 4
[DEBUG] Aval: 1, 3, 1: 81
[DEBUG] lane 2: -3, 2
[DEBUG] Aval: 1, 3, 2: 93
[DEBUG] lane 3: -5, 2
[DEBUG] Aval: 1, 3, 3: 101
[DEBUG] lane 4: -1, 1
[DEBUG] Aval: 1, 3, 4: 111
[DEBUG] lane 5: -3, 2
[DEBUG] Aval: 1, 3, 5: 122
[DEBUG] lane 6: -3, 0
[DEBUG] Aval: 1, 3, 6: 127
[DEBUG] lane 7: -3, 3
[DEBUG] Aval: 1, 3, 7: 132
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4028 -= 1;
[DEBUG] 4024 += 0;
[DEBUG] 4028 += 0;
[DEBUG] 4/8: 1, 3, 40, 4
[DEBUG] final results:
[DEBUG] Aval: 1, 3, 0: 7
[DEBUG] Aval: 1, 3, 1: 17
[DEBUG] Aval: 1, 3, 2: 29
[DEBUG] Aval: 1, 3, 3: 37
[DEBUG] Aval: 1, 3, 4: 47
[DEBUG] Aval: 1, 3, 5: 58
[DEBUG] Aval: 1, 3, 6: 63
[DEBUG] Aval: 1, 3, 7: 68
[DEBUG] discover falling edges:
[DEBUG] [4eb0] = 300
[DEBUG] eval 1, 2, 0: 33
[DEBUG] eval 1, 2, 1: 36
[DEBUG] eval 1, 2, 2: 36
[DEBUG] eval 1, 2, 3: 35
[DEBUG] eval 1, 2, 4: 38
[DEBUG] eval 1, 2, 5: 33
[DEBUG] eval 1, 2, 6: 38
[DEBUG] eval 1, 2, 7: 35
[DEBUG] eval 1, 3, 0: 33
[DEBUG] eval 1, 3, 1: 34
[DEBUG] eval 1, 3, 2: 36
[DEBUG] eval 1, 3, 3: 36
[DEBUG] eval 1, 3, 4: 38
[DEBUG] eval 1, 3, 5: 34
[DEBUG] eval 1, 3, 6: 38
[DEBUG] eval 1, 3, 7: 34
[DEBUG] discover rising edges:
[DEBUG] [4eb0] = 200
[DEBUG] eval 1, 2, 0: 37
[DEBUG] eval 1, 2, 1: 36
[DEBUG] eval 1, 2, 2: 37
[DEBUG] eval 1, 2, 3: 38
[DEBUG] eval 1, 2, 4: 38
[DEBUG] eval 1, 2, 5: 40
[DEBUG] eval 1, 2, 6: 38
[DEBUG] eval 1, 2, 7: 37
[DEBUG] eval 1, 3, 0: 36
[DEBUG] eval 1, 3, 1: 38
[DEBUG] eval 1, 3, 2: 37
[DEBUG] eval 1, 3, 3: 38
[DEBUG] eval 1, 3, 4: 37
[DEBUG] eval 1, 3, 5: 41
[DEBUG] eval 1, 3, 6: 39
[DEBUG] eval 1, 3, 7: 38
[DEBUG] CPE
[DEBUG] tx_dqs: 1, 2, 0: 65- 99- 5
[DEBUG] tx_dqs: 1, 2, 1: 75- 109- 15
[DEBUG] tx_dqs: 1, 2, 2: 83- 117- 23
[DEBUG] tx_dqs: 1, 2, 3: 90- 124- 30
[DEBUG] tx_dqs: 1, 2, 4: 103- 7- 40
[DEBUG] tx_dqs: 1, 2, 5: 104- 9- 43
[DEBUG] tx_dqs: 1, 2, 6: 112- 16- 49
[DEBUG] tx_dqs: 1, 2, 7: 118- 22- 55
[DEBUG] tx_dqs: 1, 3, 0: 65- 99- 6
[DEBUG] tx_dqs: 1, 3, 1: 79- 111- 15
[DEBUG] tx_dqs: 1, 3, 2: 86- 119- 24
[DEBUG] tx_dqs: 1, 3, 3: 94- 127- 32
[DEBUG] tx_dqs: 1, 3, 4: 102- 6- 39
[DEBUG] tx_dqs: 1, 3, 5: 106- 11- 45
[DEBUG] tx_dqs: 1, 3, 6: 112- 16- 49
[DEBUG] tx_dqs: 1, 3, 7: 118- 22- 55
[DEBUG] CPF
[DEBUG] tx_dq: 1, 2, 0: 0- 30- 61
[DEBUG] tx_dq: 1, 2, 1: 11- 41- 71
[DEBUG] tx_dq: 1, 2, 2: 20- 50- 80
[DEBUG] tx_dq: 1, 2, 3: 26- 56- 86
[DEBUG] tx_dq: 1, 2, 4: 37- 66- 96
[DEBUG] tx_dq: 1, 2, 5: 40- 70- 100
[DEBUG] tx_dq: 1, 2, 6: 42- 72- 103
[DEBUG] tx_dq: 1, 2, 7: 50- 80- 111
[DEBUG] tx_dq: 1, 3, 0: 0- 31- 62
[DEBUG] tx_dq: 1, 3, 1: 15- 44- 73
[DEBUG] tx_dq: 1, 3, 2: 22- 52- 82
[DEBUG] tx_dq: 1, 3, 3: 28- 57- 87
[DEBUG] tx_dq: 1, 3, 4: 34- 64- 95
[DEBUG] tx_dq: 1, 3, 5: 41- 71- 102
[DEBUG] tx_dq: 1, 3, 6: 42- 72- 103
[DEBUG] tx_dq: 1, 3, 7: 50- 80- 111
[DEBUG] High adjust 0:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 0, 65 -> 193
[DEBUG] High adjust 1:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 1, 75 -> 203
[DEBUG] High adjust 2:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 2, 83 -> 211
[DEBUG] High adjust 3:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 3, 90 -> 218
[DEBUG] High adjust 4:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 4, 103 -> 231
[DEBUG] High adjust 5:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 5, 104 -> 232
[DEBUG] High adjust 6:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 6, 112 -> 240
[DEBUG] High adjust 7:0000ffffffffffff
[DEBUG] Bval+: 1, 2, 7, 118 -> 246
[DEBUG] High adjust 0:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 0, 65 -> 193
[DEBUG] High adjust 1:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 1, 79 -> 207
[DEBUG] High adjust 2:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 2, 86 -> 214
[DEBUG] High adjust 3:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 3, 94 -> 222
[DEBUG] High adjust 4:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 4, 102 -> 230
[DEBUG] High adjust 5:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 5, 106 -> 234
[DEBUG] High adjust 6:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 6, 112 -> 240
[DEBUG] High adjust 7:0000ffffffffffff
[DEBUG] Bval+: 1, 3, 7, 118 -> 246
[DEBUG] CP5a
[DEBUG] CP5b
[DEBUG] Trying cmd_stretch 0 on channel 1
[DEBUG] cmd_stretch: 1, 2: 73- 126- 180
[DEBUG] cmd_stretch: 1, 3: 73- 126- 179
[DEBUG] Using CMD rate 1T on channel 1
[DEBUG] CP5c
[DEBUG] discover falling edges aggressive:
[DEBUG] [4eb0] = 300
[DEBUG] [3100] = 0x00000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 2, 0: 7- 31- 55, 17- 45
[DEBUG] edges: 1, 2, 0: 8- 35- 62, 18- 52
[DEBUG] edges: 1, 2, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 2, 0: 8- 34- 60, 18- 50
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 7- 34- 61, 17- 51
[DEBUG] edges: 1, 2, 0: 12- 37- 63, 22- 53
[DEBUG] edges: 1, 2, 0: 8- 34- 60, 18- 50
[DEBUG] using pattern 1
[DEBUG] edges: 1, 2, 0: 7- 31- 55, 17- 45
[DEBUG] edges: 1, 2, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 2, 0: 8- 34- 60, 18- 50
[DEBUG] edges: 1, 2, 0: 8- 34- 60, 18- 50
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 7- 33- 59, 17- 49
[DEBUG] edges: 1, 2, 0: 12- 37- 63, 22- 53
[DEBUG] edges: 1, 2, 0: 8- 34- 60, 18- 50
[DEBUG] using pattern 2
[DEBUG] edges: 1, 2, 0: 7- 31- 55, 17- 45
[DEBUG] edges: 1, 2, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 2, 0: 8- 34- 60, 18- 50
[DEBUG] edges: 1, 2, 0: 8- 32- 57, 18- 47
[DEBUG] edges: 1, 2, 0: 10- 36- 63, 20- 53
[DEBUG] edges: 1, 2, 0: 7- 34- 61, 17- 51
[DEBUG] edges: 1, 2, 0: 11- 36- 62, 21- 52
[DEBUG] edges: 1, 2, 0: 8- 33- 59, 18- 49
[DEBUG] using pattern 3
[DEBUG] edges: 1, 2, 0: 8- 31- 55, 18- 45
[DEBUG] edges: 1, 2, 0: 8- 35- 63, 18- 53
[DEBUG] edges: 1, 2, 0: 8- 35- 62, 18- 52
[DEBUG] edges: 1, 2, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 7- 34- 61, 17- 51
[DEBUG] edges: 1, 2, 0: 12- 38- 64, 22- 54
[DEBUG] edges: 1, 2, 0: 8- 34- 61, 18- 51
[DEBUG] [3100] = 0x0c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 2, 1: 7- 31- 56, 11- 52
[DEBUG] edges: 1, 2, 1: 7- 35- 63, 11- 59
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 2, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 2, 1: 7- 34- 62, 11- 58
[DEBUG] edges: 1, 2, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 2, 1: 8- 35- 62, 12- 58
[DEBUG] using pattern 1
[DEBUG] edges: 1, 2, 1: 7- 32- 57, 11- 53
[DEBUG] edges: 1, 2, 1: 7- 35- 63, 11- 59
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 8- 34- 60, 12- 56
[DEBUG] edges: 1, 2, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 2, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 2, 1: 12- 38- 65, 16- 61
[DEBUG] edges: 1, 2, 1: 9- 35- 61, 13- 57
[DEBUG] using pattern 2
[DEBUG] edges: 1, 2, 1: 7- 31- 55, 11- 51
[DEBUG] edges: 1, 2, 1: 7- 35- 63, 11- 59
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 8- 34- 61, 12- 57
[DEBUG] edges: 1, 2, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 2, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 2, 1: 12- 37- 63, 16- 59
[DEBUG] edges: 1, 2, 1: 9- 35- 61, 13- 57
[DEBUG] using pattern 3
[DEBUG] edges: 1, 2, 1: 7- 32- 57, 11- 53
[DEBUG] edges: 1, 2, 1: 7- 35- 63, 11- 59
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 2, 1: 9- 36- 63, 13- 59
[DEBUG] edges: 1, 2, 1: 8- 34- 61, 12- 57
[DEBUG] edges: 1, 2, 1: 12- 37- 63, 16- 59
[DEBUG] edges: 1, 2, 1: 8- 35- 62, 12- 58
[DEBUG] [3100] = 0x2c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 2, 2: 10- 31- 52, 14- 48
[DEBUG] edges: 1, 2, 2: 11- 34- 58, 15- 54
[DEBUG] edges: 1, 2, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 2, 2: 12- 33- 55, 16- 51
[DEBUG] edges: 1, 2, 2: 15- 37- 59, 19- 55
[DEBUG] edges: 1, 2, 2: 10- 34- 58, 14- 54
[DEBUG] edges: 1, 2, 2: 15- 38- 61, 19- 57
[DEBUG] edges: 1, 2, 2: 11- 34- 57, 15- 53
[DEBUG] using pattern 1
[DEBUG] edges: 1, 2, 2: 9- 31- 54, 13- 50
[DEBUG] edges: 1, 2, 2: 11- 34- 58, 15- 54
[DEBUG] edges: 1, 2, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 2, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 2, 2: 15- 37- 59, 19- 55
[DEBUG] edges: 1, 2, 2: 10- 33- 57, 14- 53
[DEBUG] edges: 1, 2, 2: 15- 37- 60, 19- 56
[DEBUG] edges: 1, 2, 2: 10- 33- 57, 14- 53
[DEBUG] using pattern 2
[DEBUG] edges: 1, 2, 2: 10- 32- 54, 14- 50
[DEBUG] edges: 1, 2, 2: 11- 35- 59, 15- 55
[DEBUG] edges: 1, 2, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 2, 2: 11- 33- 55, 15- 51
[DEBUG] edges: 1, 2, 2: 15- 38- 61, 19- 57
[DEBUG] edges: 1, 2, 2: 10- 34- 58, 14- 54
[DEBUG] edges: 1, 2, 2: 15- 37- 59, 19- 55
[DEBUG] edges: 1, 2, 2: 11- 33- 56, 15- 52
[DEBUG] using pattern 3
[DEBUG] edges: 1, 2, 2: 9- 31- 54, 13- 50
[DEBUG] edges: 1, 2, 2: 11- 35- 60, 15- 56
[DEBUG] edges: 1, 2, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 2, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 2, 2: 15- 37- 59, 19- 55
[DEBUG] edges: 1, 2, 2: 10- 34- 58, 14- 54
[DEBUG] edges: 1, 2, 2: 15- 39- 63, 19- 59
[DEBUG] edges: 1, 2, 2: 10- 33- 57, 14- 53
[DEBUG] CPA
[DEBUG] [3100] = 0x00000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 3, 0: 7- 31- 55, 17- 45
[DEBUG] edges: 1, 3, 0: 8- 33- 59, 18- 49
[DEBUG] edges: 1, 3, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 3, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 3, 0: 9- 36- 63, 19- 53
[DEBUG] edges: 1, 3, 0: 7- 34- 61, 17- 51
[DEBUG] edges: 1, 3, 0: 12- 38- 64, 22- 54
[DEBUG] edges: 1, 3, 0: 8- 34- 60, 18- 50
[DEBUG] using pattern 1
[DEBUG] edges: 1, 3, 0: 8- 32- 56, 18- 46
[DEBUG] edges: 1, 3, 0: 8- 33- 58, 18- 48
[DEBUG] edges: 1, 3, 0: 9- 34- 59, 19- 49
[DEBUG] edges: 1, 3, 0: 9- 35- 61, 19- 51
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] edges: 1, 3, 0: 7- 33- 59, 17- 49
[DEBUG] edges: 1, 3, 0: 12- 37- 63, 22- 53
[DEBUG] edges: 1, 3, 0: 8- 34- 60, 18- 50
[DEBUG] using pattern 2
[DEBUG] edges: 1, 3, 0: 8- 32- 56, 18- 46
[DEBUG] edges: 1, 3, 0: 8- 33- 58, 18- 48
[DEBUG] edges: 1, 3, 0: 8- 33- 59, 18- 49
[DEBUG] edges: 1, 3, 0: 8- 33- 58, 18- 48
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] edges: 1, 3, 0: 8- 33- 59, 18- 49
[DEBUG] edges: 1, 3, 0: 12- 37- 63, 22- 53
[DEBUG] edges: 1, 3, 0: 9- 34- 59, 19- 49
[DEBUG] using pattern 3
[DEBUG] edges: 1, 3, 0: 8- 32- 56, 18- 46
[DEBUG] edges: 1, 3, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 3, 0: 9- 35- 61, 19- 51
[DEBUG] edges: 1, 3, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] edges: 1, 3, 0: 8- 34- 61, 18- 51
[DEBUG] edges: 1, 3, 0: 12- 38- 64, 22- 54
[DEBUG] edges: 1, 3, 0: 8- 34- 60, 18- 50
[DEBUG] [3100] = 0x0c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 3, 1: 6- 31- 57, 10- 53
[DEBUG] edges: 1, 3, 1: 7- 34- 62, 11- 58
[DEBUG] edges: 1, 3, 1: 10- 36- 62, 14- 58
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 3, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 3, 1: 7- 34- 62, 11- 58
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 8- 34- 61, 12- 57
[DEBUG] using pattern 1
[DEBUG] edges: 1, 3, 1: 7- 33- 59, 11- 55
[DEBUG] edges: 1, 3, 1: 7- 34- 61, 11- 57
[DEBUG] edges: 1, 3, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 3, 1: 8- 33- 59, 12- 55
[DEBUG] edges: 1, 3, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 3, 1: 12- 38- 65, 16- 61
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] using pattern 2
[DEBUG] edges: 1, 3, 1: 7- 32- 57, 11- 53
[DEBUG] edges: 1, 3, 1: 7- 34- 61, 11- 57
[DEBUG] edges: 1, 3, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 3, 1: 9- 36- 63, 13- 59
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 8- 34- 60, 12- 56
[DEBUG] using pattern 3
[DEBUG] edges: 1, 3, 1: 6- 32- 59, 10- 55
[DEBUG] edges: 1, 3, 1: 7- 35- 63, 11- 59
[DEBUG] edges: 1, 3, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] edges: 1, 3, 1: 9- 36- 63, 13- 59
[DEBUG] edges: 1, 3, 1: 8- 34- 61, 12- 57
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 8- 35- 62, 12- 58
[DEBUG] [3100] = 0x2c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 3, 2: 9- 31- 54, 13- 50
[DEBUG] edges: 1, 3, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 3, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 3, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 3, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 3, 2: 10- 34- 58, 14- 54
[DEBUG] edges: 1, 3, 2: 15- 38- 62, 19- 58
[DEBUG] edges: 1, 3, 2: 11- 34- 58, 15- 54
[DEBUG] using pattern 1
[DEBUG] edges: 1, 3, 2: 9- 32- 55, 13- 51
[DEBUG] edges: 1, 3, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 3, 2: 12- 34- 56, 16- 52
[DEBUG] edges: 1, 3, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 3, 2: 15- 38- 62, 19- 58
[DEBUG] edges: 1, 3, 2: 10- 33- 57, 14- 53
[DEBUG] edges: 1, 3, 2: 15- 38- 61, 19- 57
[DEBUG] edges: 1, 3, 2: 11- 34- 57, 15- 53
[DEBUG] using pattern 2
[DEBUG] edges: 1, 3, 2: 9- 32- 55, 13- 51
[DEBUG] edges: 1, 3, 2: 11- 33- 55, 15- 51
[DEBUG] edges: 1, 3, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 3, 2: 12- 33- 55, 16- 51
[DEBUG] edges: 1, 3, 2: 15- 39- 63, 19- 59
[DEBUG] edges: 1, 3, 2: 10- 34- 58, 14- 54
[DEBUG] edges: 1, 3, 2: 16- 38- 60, 20- 56
[DEBUG] edges: 1, 3, 2: 11- 33- 56, 15- 52
[DEBUG] using pattern 3
[DEBUG] edges: 1, 3, 2: 9- 32- 55, 13- 51
[DEBUG] edges: 1, 3, 2: 11- 34- 57, 15- 53
[DEBUG] edges: 1, 3, 2: 12- 34- 57, 16- 53
[DEBUG] edges: 1, 3, 2: 11- 33- 56, 15- 52
[DEBUG] edges: 1, 3, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 3, 2: 10- 34- 59, 14- 55
[DEBUG] edges: 1, 3, 2: 16- 39- 63, 20- 59
[DEBUG] edges: 1, 3, 2: 11- 34- 57, 15- 53
[DEBUG] CPA
[DEBUG] discover rising edges aggressive:
[DEBUG] [4eb0] = 200
[DEBUG] [3100] = 0x00000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 2, 0: 9- 34- 60, 19- 50
[DEBUG] edges: 1, 2, 0: 9- 34- 59, 19- 49
[DEBUG] edges: 1, 2, 0: 9- 36- 63, 19- 53
[DEBUG] edges: 1, 2, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 2, 0: 9- 36- 64, 19- 54
[DEBUG] edges: 1, 2, 0: 10- 38- 66, 20- 56
[DEBUG] edges: 1, 2, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 2, 0: 9- 36- 63, 19- 53
[DEBUG] using pattern 1
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 10- 33- 57, 20- 47
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 2, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 2, 0: 11- 38- 65, 21- 55
[DEBUG] edges: 1, 2, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 2, 0: 10- 36- 63, 20- 53
[DEBUG] using pattern 2
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 10- 34- 58, 20- 48
[DEBUG] edges: 1, 2, 0: 9- 35- 62, 19- 52
[DEBUG] edges: 1, 2, 0: 11- 37- 63, 21- 53
[DEBUG] edges: 1, 2, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 2, 0: 11- 38- 66, 21- 56
[DEBUG] edges: 1, 2, 0: 11- 37- 63, 21- 53
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] using pattern 3
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 2, 0: 10- 34- 58, 20- 48
[DEBUG] edges: 1, 2, 0: 9- 35- 62, 19- 52
[DEBUG] edges: 1, 2, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 2, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 2, 0: 11- 38- 65, 21- 55
[DEBUG] edges: 1, 2, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 2, 0: 10- 36- 62, 20- 52
[DEBUG] [3100] = 0x0c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 9- 35- 61, 13- 57
[DEBUG] edges: 1, 2, 1: 11- 36- 62, 15- 58
[DEBUG] edges: 1, 2, 1: 10- 37- 64, 14- 60
[DEBUG] edges: 1, 2, 1: 10- 37- 64, 14- 60
[DEBUG] edges: 1, 2, 1: 12- 38- 65, 16- 61
[DEBUG] edges: 1, 2, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] using pattern 1
[DEBUG] edges: 1, 2, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 2, 1: 9- 34- 60, 13- 56
[DEBUG] edges: 1, 2, 1: 10- 36- 62, 14- 58
[DEBUG] edges: 1, 2, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 2, 1: 10- 37- 64, 14- 60
[DEBUG] edges: 1, 2, 1: 12- 39- 67, 16- 63
[DEBUG] edges: 1, 2, 1: 11- 37- 64, 15- 60
[DEBUG] edges: 1, 2, 1: 10- 36- 62, 14- 58
[DEBUG] using pattern 2
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 9- 34- 59, 13- 55
[DEBUG] edges: 1, 2, 1: 11- 36- 62, 15- 58
[DEBUG] edges: 1, 2, 1: 11- 37- 64, 15- 60
[DEBUG] edges: 1, 2, 1: 10- 37- 64, 14- 60
[DEBUG] edges: 1, 2, 1: 13- 39- 66, 17- 62
[DEBUG] edges: 1, 2, 1: 12- 37- 62, 16- 58
[DEBUG] edges: 1, 2, 1: 10- 36- 62, 14- 58
[DEBUG] using pattern 3
[DEBUG] edges: 1, 2, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 2, 1: 9- 35- 61, 13- 57
[DEBUG] edges: 1, 2, 1: 11- 36- 61, 15- 57
[DEBUG] edges: 1, 2, 1: 10- 37- 65, 14- 61
[DEBUG] edges: 1, 2, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 2, 1: 13- 38- 64, 17- 60
[DEBUG] edges: 1, 2, 1: 12- 37- 62, 16- 58
[DEBUG] edges: 1, 2, 1: 10- 37- 64, 14- 60
[DEBUG] [3100] = 0x2c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 2, 2: 13- 35- 57, 17- 53
[DEBUG] edges: 1, 2, 2: 15- 35- 56, 19- 52
[DEBUG] edges: 1, 2, 2: 13- 36- 59, 17- 55
[DEBUG] edges: 1, 2, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 2, 2: 13- 37- 62, 17- 58
[DEBUG] edges: 1, 2, 2: 14- 39- 64, 18- 60
[DEBUG] edges: 1, 2, 2: 13- 37- 62, 17- 58
[DEBUG] edges: 1, 2, 2: 11- 36- 61, 15- 57
[DEBUG] using pattern 1
[DEBUG] edges: 1, 2, 2: 15- 37- 59, 19- 55
[DEBUG] edges: 1, 2, 2: 15- 35- 56, 19- 52
[DEBUG] edges: 1, 2, 2: 13- 36- 59, 17- 55
[DEBUG] edges: 1, 2, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 2, 2: 14- 38- 63, 18- 59
[DEBUG] edges: 1, 2, 2: 15- 39- 64, 19- 60
[DEBUG] edges: 1, 2, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 2, 2: 13- 37- 61, 17- 57
[DEBUG] using pattern 2
[DEBUG] edges: 1, 2, 2: 14- 36- 59, 18- 55
[DEBUG] edges: 1, 2, 2: 15- 35- 56, 19- 52
[DEBUG] edges: 1, 2, 2: 13- 36- 59, 17- 55
[DEBUG] edges: 1, 2, 2: 14- 37- 60, 18- 56
[DEBUG] edges: 1, 2, 2: 14- 38- 63, 18- 59
[DEBUG] edges: 1, 2, 2: 15- 39- 64, 19- 60
[DEBUG] edges: 1, 2, 2: 15- 38- 61, 19- 57
[DEBUG] edges: 1, 2, 2: 13- 35- 58, 17- 54
[DEBUG] using pattern 3
[DEBUG] edges: 1, 2, 2: 14- 36- 59, 18- 55
[DEBUG] edges: 1, 2, 2: 15- 35- 56, 19- 52
[DEBUG] edges: 1, 2, 2: 13- 35- 58, 17- 54
[DEBUG] edges: 1, 2, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 2, 2: 14- 37- 61, 18- 57
[DEBUG] edges: 1, 2, 2: 15- 39- 64, 19- 60
[DEBUG] edges: 1, 2, 2: 15- 39- 63, 19- 59
[DEBUG] edges: 1, 2, 2: 13- 36- 59, 17- 55
[DEBUG] CPA
[DEBUG] [3100] = 0x00000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 3, 0: 9- 34- 59, 19- 49
[DEBUG] edges: 1, 3, 0: 9- 36- 63, 19- 53
[DEBUG] edges: 1, 3, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 3, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 3, 0: 9- 36- 64, 19- 54
[DEBUG] edges: 1, 3, 0: 11- 38- 66, 21- 56
[DEBUG] edges: 1, 3, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 3, 0: 9- 36- 63, 19- 53
[DEBUG] using pattern 1
[DEBUG] edges: 1, 3, 0: 10- 35- 61, 20- 51
[DEBUG] edges: 1, 3, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 3, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 3, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 3, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 3, 0: 12- 38- 65, 22- 55
[DEBUG] edges: 1, 3, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] using pattern 2
[DEBUG] edges: 1, 3, 0: 10- 35- 61, 20- 51
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] edges: 1, 3, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 3, 0: 11- 37- 63, 21- 53
[DEBUG] edges: 1, 3, 0: 10- 37- 64, 20- 54
[DEBUG] edges: 1, 3, 0: 12- 38- 65, 22- 55
[DEBUG] edges: 1, 3, 0: 11- 37- 63, 21- 53
[DEBUG] edges: 1, 3, 0: 11- 36- 62, 21- 52
[DEBUG] using pattern 3
[DEBUG] edges: 1, 3, 0: 10- 35- 61, 20- 51
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] edges: 1, 3, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 3, 0: 11- 37- 64, 21- 54
[DEBUG] edges: 1, 3, 0: 10- 36- 62, 20- 52
[DEBUG] edges: 1, 3, 0: 12- 39- 66, 22- 56
[DEBUG] edges: 1, 3, 0: 11- 37- 63, 21- 53
[DEBUG] edges: 1, 3, 0: 10- 36- 63, 20- 53
[DEBUG] [3100] = 0x0c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 3, 1: 9- 35- 62, 13- 58
[DEBUG] edges: 1, 3, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 11- 37- 64, 15- 60
[DEBUG] edges: 1, 3, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 3, 1: 12- 39- 66, 16- 62
[DEBUG] edges: 1, 3, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 3, 1: 9- 35- 62, 13- 58
[DEBUG] using pattern 1
[DEBUG] edges: 1, 3, 1: 9- 36- 63, 13- 59
[DEBUG] edges: 1, 3, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 3, 1: 12- 39- 67, 16- 63
[DEBUG] edges: 1, 3, 1: 10- 37- 64, 14- 60
[DEBUG] edges: 1, 3, 1: 9- 36- 63, 13- 59
[DEBUG] using pattern 2
[DEBUG] edges: 1, 3, 1: 9- 34- 60, 13- 56
[DEBUG] edges: 1, 3, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 11- 37- 64, 15- 60
[DEBUG] edges: 1, 3, 1: 10- 36- 63, 14- 59
[DEBUG] edges: 1, 3, 1: 13- 39- 66, 17- 62
[DEBUG] edges: 1, 3, 1: 11- 37- 63, 15- 59
[DEBUG] edges: 1, 3, 1: 10- 36- 63, 14- 59
[DEBUG] using pattern 3
[DEBUG] edges: 1, 3, 1: 9- 35- 61, 13- 57
[DEBUG] edges: 1, 3, 1: 9- 36- 64, 13- 60
[DEBUG] edges: 1, 3, 1: 11- 36- 62, 15- 58
[DEBUG] edges: 1, 3, 1: 11- 37- 64, 15- 60
[DEBUG] edges: 1, 3, 1: 10- 36- 62, 14- 58
[DEBUG] edges: 1, 3, 1: 13- 38- 64, 17- 60
[DEBUG] edges: 1, 3, 1: 11- 36- 62, 15- 58
[DEBUG] edges: 1, 3, 1: 10- 37- 64, 14- 60
[DEBUG] [3100] = 0x2c000000
[DEBUG] using pattern 0
[DEBUG] edges: 1, 3, 2: 13- 35- 57, 17- 53
[DEBUG] edges: 1, 3, 2: 15- 37- 60, 19- 56
[DEBUG] edges: 1, 3, 2: 13- 36- 60, 17- 56
[DEBUG] edges: 1, 3, 2: 14- 38- 62, 18- 58
[DEBUG] edges: 1, 3, 2: 13- 37- 61, 17- 57
[DEBUG] edges: 1, 3, 2: 15- 39- 64, 19- 60
[DEBUG] edges: 1, 3, 2: 13- 37- 62, 17- 58
[DEBUG] edges: 1, 3, 2: 12- 36- 61, 16- 57
[DEBUG] using pattern 1
[DEBUG] edges: 1, 3, 2: 15- 37- 59, 19- 55
[DEBUG] edges: 1, 3, 2: 15- 36- 58, 19- 54
[DEBUG] edges: 1, 3, 2: 14- 36- 59, 18- 55
[DEBUG] edges: 1, 3, 2: 14- 38- 63, 18- 59
[DEBUG] edges: 1, 3, 2: 13- 37- 61, 17- 57
[DEBUG] edges: 1, 3, 2: 16- 40- 64, 20- 60
[DEBUG] edges: 1, 3, 2: 15- 38- 62, 19- 58
[DEBUG] edges: 1, 3, 2: 14- 38- 62, 18- 58
[DEBUG] using pattern 2
[DEBUG] edges: 1, 3, 2: 14- 36- 58, 18- 54
[DEBUG] edges: 1, 3, 2: 15- 36- 58, 19- 54
[DEBUG] edges: 1, 3, 2: 13- 36- 59, 17- 55
[DEBUG] edges: 1, 3, 2: 14- 37- 61, 18- 57
[DEBUG] edges: 1, 3, 2: 13- 37- 62, 17- 58
[DEBUG] edges: 1, 3, 2: 16- 40- 64, 20- 60
[DEBUG] edges: 1, 3, 2: 15- 38- 61, 19- 57
[DEBUG] edges: 1, 3, 2: 14- 36- 59, 18- 55
[DEBUG] using pattern 3
[DEBUG] edges: 1, 3, 2: 15- 36- 58, 19- 54
[DEBUG] edges: 1, 3, 2: 15- 37- 60, 19- 56
[DEBUG] edges: 1, 3, 2: 14- 36- 59, 18- 55
[DEBUG] edges: 1, 3, 2: 14- 37- 61, 18- 57
[DEBUG] edges: 1, 3, 2: 13- 36- 59, 17- 55
[DEBUG] edges: 1, 3, 2: 16- 40- 64, 20- 60
[DEBUG] edges: 1, 3, 2: 14- 38- 63, 18- 59
[DEBUG] edges: 1, 3, 2: 14- 38- 62, 18- 58
[DEBUG] CPA
[DEBUG] Aggressive write training:
[DEBUG] tx_dq: 1, 2, 0: 0- 28- 56, 11- 45
[DEBUG] tx_dq: 1, 2, 0: 12- 38- 65, 23- 54
[DEBUG] tx_dq: 1, 2, 0: 21- 49- 77, 32- 66
[DEBUG] tx_dq: 1, 2, 0: 27- 55- 83, 38- 72
[DEBUG] tx_dq: 1, 2, 0: 38- 65- 93, 49- 82
[DEBUG] tx_dq: 1, 2, 0: 40- 67- 95, 51- 84
[DEBUG] tx_dq: 1, 2, 0: 43- 70- 98, 54- 87
[DEBUG] tx_dq: 1, 2, 0: 51- 79- 107, 62- 96
[DEBUG] tx_dq: 1, 3, 0: 0- 28- 57, 11- 46
[DEBUG] tx_dq: 1, 3, 0: 15- 41- 68, 26- 57
[DEBUG] tx_dq: 1, 3, 0: 23- 51- 79, 34- 68
[DEBUG] tx_dq: 1, 3, 0: 31- 58- 86, 42- 75
[DEBUG] tx_dq: 1, 3, 0: 36- 64- 92, 47- 81
[DEBUG] tx_dq: 1, 3, 0: 42- 69- 97, 53- 86
[DEBUG] tx_dq: 1, 3, 0: 43- 70- 98, 54- 87
[DEBUG] tx_dq: 1, 3, 0: 51- 79- 108, 62- 97
[DEBUG] tx_dq: 1, 2, 0: 0- 28- 56, 11- 45
[DEBUG] tx_dq: 1, 2, 0: 13- 39- 65, 24- 54
[DEBUG] tx_dq: 1, 2, 0: 22- 49- 77, 33- 66
[DEBUG] tx_dq: 1, 2, 0: 27- 54- 82, 38- 71
[DEBUG] tx_dq: 1, 2, 0: 38- 65- 92, 49- 81
[DEBUG] tx_dq: 1, 2, 0: 41- 68- 95, 52- 84
[DEBUG] tx_dq: 1, 2, 0: 44- 71- 98, 55- 87
[DEBUG] tx_dq: 1, 2, 0: 52- 79- 107, 63- 96
[DEBUG] tx_dq: 1, 3, 0: 0- 28- 57, 11- 46
[DEBUG] tx_dq: 1, 3, 0: 15- 41- 68, 26- 57
[DEBUG] tx_dq: 1, 3, 0: 24- 51- 79, 35- 68
[DEBUG] tx_dq: 1, 3, 0: 31- 58- 86, 42- 75
[DEBUG] tx_dq: 1, 3, 0: 37- 64- 92, 48- 81
[DEBUG] tx_dq: 1, 3, 0: 43- 70- 97, 54- 86
[DEBUG] tx_dq: 1, 3, 0: 45- 71- 98, 56- 87
[DEBUG] tx_dq: 1, 3, 0: 52- 79- 107, 63- 96
[DEBUG] tx_dq: 1, 2, 0: 0- 28- 56, 11- 45
[DEBUG] tx_dq: 1, 2, 0: 12- 39- 66, 23- 55
[DEBUG] tx_dq: 1, 2, 0: 22- 49- 77, 33- 66
[DEBUG] tx_dq: 1, 2, 0: 28- 55- 83, 39- 72
[DEBUG] tx_dq: 1, 2, 0: 38- 65- 93, 49- 82
[DEBUG] tx_dq: 1, 2, 0: 40- 67- 95, 51- 84
[DEBUG] tx_dq: 1, 2, 0: 43- 70- 98, 54- 87
[DEBUG] tx_dq: 1, 2, 0: 52- 79- 107, 63- 96
[DEBUG] tx_dq: 1, 3, 0: 0- 28- 56, 11- 45
[DEBUG] tx_dq: 1, 3, 0: 15- 42- 69, 26- 58
[DEBUG] tx_dq: 1, 3, 0: 23- 51- 79, 34- 68
[DEBUG] tx_dq: 1, 3, 0: 32- 59- 86, 43- 75
[DEBUG] tx_dq: 1, 3, 0: 36- 63- 91, 47- 80
[DEBUG] tx_dq: 1, 3, 0: 41- 69- 97, 52- 86
[DEBUG] tx_dq: 1, 3, 0: 44- 71- 98, 55- 87
[DEBUG] tx_dq: 1, 3, 0: 53- 80- 107, 64- 96
[DEBUG] tx_dq: 1, 2, 0: 0- 28- 56, 11- 45
[DEBUG] tx_dq: 1, 2, 0: 12- 39- 66, 23- 55
[DEBUG] tx_dq: 1, 2, 0: 22- 49- 77, 33- 66
[DEBUG] tx_dq: 1, 2, 0: 27- 55- 83, 38- 72
[DEBUG] tx_dq: 1, 2, 0: 38- 65- 93, 49- 82
[DEBUG] tx_dq: 1, 2, 0: 41- 68- 96, 52- 85
[DEBUG] tx_dq: 1, 2, 0: 43- 70- 98, 54- 87
[DEBUG] tx_dq: 1, 2, 0: 50- 78- 107, 61- 96
[DEBUG] tx_dq: 1, 3, 0: 0- 28- 56, 11- 45
[DEBUG] tx_dq: 1, 3, 0: 15- 42- 69, 26- 58
[DEBUG] tx_dq: 1, 3, 0: 23- 51- 79, 34- 68
[DEBUG] tx_dq: 1, 3, 0: 31- 58- 86, 42- 75
[DEBUG] tx_dq: 1, 3, 0: 36- 63- 91, 47- 80
[DEBUG] tx_dq: 1, 3, 0: 43- 70- 97, 54- 86
[DEBUG] tx_dq: 1, 3, 0: 44- 71- 99, 55- 88
[DEBUG] tx_dq: 1, 3, 0: 51- 79- 107, 62- 96
[DEBUG] tx_dq: 1, 2, 1: 1- 28- 55, 5- 51
[DEBUG] tx_dq: 1, 2, 1: 14- 38- 63, 18- 59
[DEBUG] tx_dq: 1, 2, 1: 23- 48- 73, 27- 69
[DEBUG] tx_dq: 1, 2, 1: 30- 55- 80, 34- 76
[DEBUG] tx_dq: 1, 2, 1: 40- 65- 90, 44- 86
[DEBUG] tx_dq: 1, 2, 1: 42- 67- 93, 46- 89
[DEBUG] tx_dq: 1, 2, 1: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 2, 1: 55- 79- 104, 59- 100
[DEBUG] tx_dq: 1, 3, 1: 1- 27- 54, 5- 50
[DEBUG] tx_dq: 1, 3, 1: 16- 41- 66, 20- 62
[DEBUG] tx_dq: 1, 3, 1: 24- 50- 76, 28- 72
[DEBUG] tx_dq: 1, 3, 1: 32- 57- 83, 36- 79
[DEBUG] tx_dq: 1, 3, 1: 39- 63- 88, 43- 84
[DEBUG] tx_dq: 1, 3, 1: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 3, 1: 46- 71- 96, 50- 92
[DEBUG] tx_dq: 1, 3, 1: 55- 79- 104, 59- 100
[DEBUG] tx_dq: 1, 2, 1: 1- 28- 55, 5- 51
[DEBUG] tx_dq: 1, 2, 1: 14- 38- 63, 18- 59
[DEBUG] tx_dq: 1, 2, 1: 24- 48- 72, 28- 68
[DEBUG] tx_dq: 1, 2, 1: 31- 55- 80, 35- 76
[DEBUG] tx_dq: 1, 2, 1: 40- 65- 90, 44- 86
[DEBUG] tx_dq: 1, 2, 1: 43- 68- 93, 47- 89
[DEBUG] tx_dq: 1, 2, 1: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 2, 1: 56- 80- 104, 60- 100
[DEBUG] tx_dq: 1, 3, 1: 1- 27- 54, 5- 50
[DEBUG] tx_dq: 1, 3, 1: 16- 41- 66, 20- 62
[DEBUG] tx_dq: 1, 3, 1: 25- 50- 76, 29- 72
[DEBUG] tx_dq: 1, 3, 1: 32- 57- 83, 36- 79
[DEBUG] tx_dq: 1, 3, 1: 39- 63- 88, 43- 84
[DEBUG] tx_dq: 1, 3, 1: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 3, 1: 48- 72- 97, 52- 93
[DEBUG] tx_dq: 1, 3, 1: 56- 80- 104, 60- 100
[DEBUG] tx_dq: 1, 2, 1: 2- 28- 55, 6- 51
[DEBUG] tx_dq: 1, 2, 1: 15- 39- 63, 19- 59
[DEBUG] tx_dq: 1, 2, 1: 24- 48- 73, 28- 69
[DEBUG] tx_dq: 1, 2, 1: 31- 55- 80, 35- 76
[DEBUG] tx_dq: 1, 2, 1: 40- 65- 90, 44- 86
[DEBUG] tx_dq: 1, 2, 1: 42- 67- 93, 46- 89
[DEBUG] tx_dq: 1, 2, 1: 46- 70- 95, 50- 91
[DEBUG] tx_dq: 1, 2, 1: 56- 80- 104, 60- 100
[DEBUG] tx_dq: 1, 3, 1: 1- 27- 54, 5- 50
[DEBUG] tx_dq: 1, 3, 1: 16- 41- 66, 20- 62
[DEBUG] tx_dq: 1, 3, 1: 24- 50- 77, 28- 73
[DEBUG] tx_dq: 1, 3, 1: 32- 57- 83, 36- 79
[DEBUG] tx_dq: 1, 3, 1: 39- 63- 88, 43- 84
[DEBUG] tx_dq: 1, 3, 1: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 3, 1: 46- 71- 96, 50- 92
[DEBUG] tx_dq: 1, 3, 1: 56- 80- 104, 60- 100
[DEBUG] tx_dq: 1, 2, 1: 1- 27- 54, 5- 50
[DEBUG] tx_dq: 1, 2, 1: 14- 38- 63, 18- 59
[DEBUG] tx_dq: 1, 2, 1: 23- 47- 72, 27- 68
[DEBUG] tx_dq: 1, 2, 1: 31- 55- 80, 35- 76
[DEBUG] tx_dq: 1, 2, 1: 40- 65- 90, 44- 86
[DEBUG] tx_dq: 1, 2, 1: 43- 68- 94, 47- 90
[DEBUG] tx_dq: 1, 2, 1: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 2, 1: 54- 79- 104, 58- 100
[DEBUG] tx_dq: 1, 3, 1: 1- 27- 54, 5- 50
[DEBUG] tx_dq: 1, 3, 1: 16- 41- 66, 20- 62
[DEBUG] tx_dq: 1, 3, 1: 24- 50- 76, 28- 72
[DEBUG] tx_dq: 1, 3, 1: 32- 57- 83, 36- 79
[DEBUG] tx_dq: 1, 3, 1: 39- 63- 88, 43- 84
[DEBUG] tx_dq: 1, 3, 1: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 3, 1: 47- 71- 96, 51- 92
[DEBUG] tx_dq: 1, 3, 1: 55- 79- 104, 59- 100
[DEBUG] tx_dq: 1, 2, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 2, 2: 15- 39- 63, 19- 59
[DEBUG] tx_dq: 1, 2, 2: 23- 47- 72, 27- 68
[DEBUG] tx_dq: 1, 2, 2: 31- 55- 79, 35- 75
[DEBUG] tx_dq: 1, 2, 2: 40- 64- 88, 44- 84
[DEBUG] tx_dq: 1, 2, 2: 42- 66- 91, 46- 87
[DEBUG] tx_dq: 1, 2, 2: 46- 70- 95, 50- 91
[DEBUG] tx_dq: 1, 2, 2: 54- 78- 103, 58- 99
[DEBUG] tx_dq: 1, 3, 2: 2- 27- 53, 6- 49
[DEBUG] tx_dq: 1, 3, 2: 16- 39- 63, 20- 59
[DEBUG] tx_dq: 1, 3, 2: 24- 49- 74, 28- 70
[DEBUG] tx_dq: 1, 3, 2: 32- 56- 81, 36- 77
[DEBUG] tx_dq: 1, 3, 2: 39- 63- 87, 43- 83
[DEBUG] tx_dq: 1, 3, 2: 45- 69- 94, 49- 90
[DEBUG] tx_dq: 1, 3, 2: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 3, 2: 55- 79- 103, 59- 99
[DEBUG] tx_dq: 1, 2, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 2, 2: 15- 39- 63, 19- 59
[DEBUG] tx_dq: 1, 2, 2: 24- 48- 72, 28- 68
[DEBUG] tx_dq: 1, 2, 2: 31- 55- 79, 35- 75
[DEBUG] tx_dq: 1, 2, 2: 40- 63- 87, 44- 83
[DEBUG] tx_dq: 1, 2, 2: 42- 66- 91, 46- 87
[DEBUG] tx_dq: 1, 2, 2: 46- 70- 95, 50- 91
[DEBUG] tx_dq: 1, 2, 2: 56- 79- 103, 60- 99
[DEBUG] tx_dq: 1, 3, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 3, 2: 16- 39- 63, 20- 59
[DEBUG] tx_dq: 1, 3, 2: 25- 49- 74, 29- 70
[DEBUG] tx_dq: 1, 3, 2: 32- 56- 81, 36- 77
[DEBUG] tx_dq: 1, 3, 2: 39- 63- 87, 43- 83
[DEBUG] tx_dq: 1, 3, 2: 45- 69- 94, 49- 90
[DEBUG] tx_dq: 1, 3, 2: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 3, 2: 55- 79- 103, 59- 99
[DEBUG] tx_dq: 1, 2, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 2, 2: 15- 39- 63, 19- 59
[DEBUG] tx_dq: 1, 2, 2: 23- 47- 72, 27- 68
[DEBUG] tx_dq: 1, 2, 2: 31- 55- 79, 35- 75
[DEBUG] tx_dq: 1, 2, 2: 40- 64- 88, 44- 84
[DEBUG] tx_dq: 1, 2, 2: 42- 66- 91, 46- 87
[DEBUG] tx_dq: 1, 2, 2: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 2, 2: 55- 79- 103, 59- 99
[DEBUG] tx_dq: 1, 3, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 3, 2: 16- 39- 63, 20- 59
[DEBUG] tx_dq: 1, 3, 2: 24- 49- 74, 28- 70
[DEBUG] tx_dq: 1, 3, 2: 32- 56- 81, 36- 77
[DEBUG] tx_dq: 1, 3, 2: 39- 63- 87, 43- 83
[DEBUG] tx_dq: 1, 3, 2: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 3, 2: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 3, 2: 55- 79- 103, 59- 99
[DEBUG] tx_dq: 1, 2, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 2, 2: 14- 38- 63, 18- 59
[DEBUG] tx_dq: 1, 2, 2: 24- 48- 72, 28- 68
[DEBUG] tx_dq: 1, 2, 2: 31- 55- 79, 35- 75
[DEBUG] tx_dq: 1, 2, 2: 40- 64- 88, 44- 84
[DEBUG] tx_dq: 1, 2, 2: 42- 66- 91, 46- 87
[DEBUG] tx_dq: 1, 2, 2: 47- 71- 95, 51- 91
[DEBUG] tx_dq: 1, 2, 2: 53- 78- 103, 57- 99
[DEBUG] tx_dq: 1, 3, 2: 1- 26- 52, 5- 48
[DEBUG] tx_dq: 1, 3, 2: 16- 39- 63, 20- 59
[DEBUG] tx_dq: 1, 3, 2: 24- 49- 74, 28- 70
[DEBUG] tx_dq: 1, 3, 2: 32- 56- 81, 36- 77
[DEBUG] tx_dq: 1, 3, 2: 38- 62- 87, 42- 83
[DEBUG] tx_dq: 1, 3, 2: 45- 69- 94, 49- 90
[DEBUG] tx_dq: 1, 3, 2: 45- 70- 95, 49- 91
[DEBUG] tx_dq: 1, 3, 2: 53- 78- 103, 57- 99
[DEBUG] CPB
[DEBUG] tx_dq 1, 2, 0: 28
[DEBUG] tx_dq 1, 2, 1: 39
[DEBUG] tx_dq 1, 2, 2: 49
[DEBUG] tx_dq 1, 2, 3: 55
[DEBUG] tx_dq 1, 2, 4: 65
[DEBUG] tx_dq 1, 2, 5: 68
[DEBUG] tx_dq 1, 2, 6: 71
[DEBUG] tx_dq 1, 2, 7: 79
[DEBUG] tx_dq 1, 3, 0: 28
[DEBUG] tx_dq 1, 3, 1: 41
[DEBUG] tx_dq 1, 3, 2: 51
[DEBUG] tx_dq 1, 3, 3: 59
[DEBUG] tx_dq 1, 3, 4: 64
[DEBUG] tx_dq 1, 3, 5: 70
[DEBUG] tx_dq 1, 3, 6: 71
[DEBUG] tx_dq 1, 3, 7: 80
[DEBUG] normalize 1, 2, 8: mat 66
[DEBUG] normalize 1, 2, 8: delta -3
[DEBUG] normalize 1, 3, 8: mat 68
[DEBUG] normalize 1, 3, 8: delta -3
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x101f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x0
[NOTE ] ME: Progress code : 0x1
[NOTE ] 1m[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x50
[NOTE ] ME: Current PM event: 0x0
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : uKernel Phase
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
[DEBUG] ME: Progress Phase State : Unknown 0x00
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 798 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode on
[DEBUG] rank interleave on
[DEBUG] DIMMA 8192 MB width x8 dual rank
[DEBUG] DIMMB 0 MB width x8 single rank, selected
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x803ff000 254 entries.
[DEBUG] IMD: root @ 0x803fec00 62 entries.
[DEBUG] CBMEM entry for DIMM info: 0x7ffda000
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x80000000 0x800000
[DEBUG] Subregion 0: 0x80000000 0x300000
[DEBUG] Subregion 1: 0x80300000 0x100000
[DEBUG] Subregion 2: 0x80400000 0x400000
[DEBUG] Normal boot
[INFO ] CBFS: Found 'fallback/postcar' @0x416c0 size 0x51a8 in mcache @0xfeff1078
[DEBUG] Loading module at 0x7ffce000 with entry 0x7ffce031. filesize: 0x4de0 memsize: 0xb118
[DEBUG] Processing 226 relocs. Offset value of 0x7dfce000
[DEBUG] BS: romstage times (exec / console): total (unknown) / 7050 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 postcar starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: Found 'fallback/ramstage' @0x1b1c0 size 0x1be4d in mcache @0x7ffdd0dc
[DEBUG] Loading module at 0x7ff75000 with entry 0x7ff75000. filesize: 0x38778 memsize: 0x57f50
[DEBUG] Processing 3995 relocs. Offset value of 0x7bf75000
[DEBUG] BS: postcar times (exec / console): total (unknown) / 42 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 ramstage starting (log level: 7)...
[DEBUG] Normal boot
[INFO ] Enumerating buses...
[DEBUG] Root Device scanning...
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 0000 enabled
[DEBUG] DOMAIN: 0000 scanning...
[DEBUG] PCI: pci_scan_bus for bus 00
[DEBUG] PCI: 00:00.0 [8086/0150] enabled
[DEBUG] PCI: 00:01.0 [8086/0151] enabled
[DEBUG] PCI: 00:02.0 [8086/0152] enabled
[DEBUG] PCI: 00:14.0 [8086/1e31] enabled
[DEBUG] PCI: 00:16.0 [8086/1e3a] enabled
[DEBUG] PCI: 00:16.1: Disabling device
[DEBUG] PCI: 00:16.1 [8086/1e3b] disabled No operations
[DEBUG] PCI: 00:16.2: Disabling device
[DEBUG] PCI: 00:16.3: Disabling device
[DEBUG] PCI: 00:19.0: Disabling device
[DEBUG] PCI: 00:1a.0 [8086/1e2d] enabled
[DEBUG] PCI: 00:1b.0 [8086/1e20] enabled
[DEBUG] PCI: 00:1c.0 [8086/1e10] enabled
[DEBUG] PCI: 00:1c.1: Disabling device
[DEBUG] PCI: 00:1c.2: Disabling device
[DEBUG] PCI: 00:1c.3: Disabling device
[DEBUG] PCI: 00:1c.4 [8086/1e18] enabled
[DEBUG] PCI: 00:1c.5 [8086/1e1a] enabled
[DEBUG] PCI: 00:1c.6 [8086/1e1c] enabled
[DEBUG] PCI: 00:1c.7 [8086/1e1e] enabled
[DEBUG] PCI: 00:1d.0 [8086/1e26] enabled
[DEBUG] PCI: 00:1e.0: Disabling device
[DEBUG] PCI: 00:1e.0 [8086/244e] disabled
[DEBUG] PCI: 00:1f.0 [8086/1e44] enabled
[DEBUG] PCI: 00:1f.2 [8086/1e00] enabled
[DEBUG] PCI: 00:1f.3 [8086/1e22] enabled
[DEBUG] PCI: 00:1f.5: Disabling device
[DEBUG] PCI: 00:1f.5 [8086/1e08] disabled No operations
[DEBUG] PCI: 00:1f.6: Disabling device
[DEBUG] PCI: 00:1f.6 [8086/1e24] disabled No operations
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:16.2
[WARN ] PCI: 00:16.3
[WARN ] PCI: 00:19.0
[WARN ] PCI: 00:1c.1
[WARN ] PCI: 00:1c.2
[WARN ] PCI: 00:1c.3
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] PCI: 00:01.0 scanning...
[DEBUG] PCI: 00:01.0: No LTR support
[DEBUG] PCI: pci_scan_bus for bus 01
[DEBUG] scan_bus: bus PCI: 00:01.0 finished in 8 msecs
[DEBUG] PCI: 00:1c.0 scanning...
[DEBUG] PCI: 00:1c.0: No LTR support
[DEBUG] PCI: pci_scan_bus for bus 02
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 8 msecs
[DEBUG] PCI: 00:1c.4 scanning...
[DEBUG] PCI: 00:1c.4: No LTR support
[DEBUG] PCI: pci_scan_bus for bus 03
[DEBUG] PCI: 03:00.0 [10ec/8168] enabled
[INFO ] Enabling Common Clock Configuration
[INFO ] ASPM: Enabled L1
[INFO ] PCIe: Max_Payload_Size adjusted to 128
[DEBUG] PCI: 03:00.0: No LTR support
[DEBUG] scan_bus: bus PCI: 00:1c.4 finished in 29 msecs
[DEBUG] PCI: 00:1c.5 scanning...
[DEBUG] PCI: 00:1c.5: No LTR support
[DEBUG] PCI: pci_scan_bus for bus 04
[DEBUG] PCI: 04:00.0 subordinate PCI
[DEBUG] PCI: 04:00.0 [1b21/1080] enabled
[DEBUG] PCI: 04:00.0 scanning...
[DEBUG] PCI: pci_scan_bus for bus 05
[DEBUG] scan_bus: bus PCI: 04:00.0 finished in 4 msecs
[INFO ] ASPM: Enabled None
[INFO ] PCIe: Max_Payload_Size adjusted to 128
[DEBUG] PCI: 04:00.0: No LTR support
[DEBUG] scan_bus: bus PCI: 00:1c.5 finished in 42 msecs
[DEBUG] PCI: 00:1c.6 scanning...
[DEBUG] PCI: 00:1c.6: No LTR support
[DEBUG] PCI: pci_scan_bus for bus 06
[DEBUG] scan_bus: bus PCI: 00:1c.6 finished in 8 msecs
[DEBUG] PCI: 00:1c.7 scanning...
[DEBUG] PCI: 00:1c.7: No LTR support
[DEBUG] PCI: pci_scan_bus for bus 07
[DEBUG] scan_bus: bus PCI: 00:1c.7 finished in 8 msecs
[DEBUG] PCI: 00:1f.0 scanning...
[DEBUG] PNP: 002e.1 disabled
[DEBUG] PNP: 002e.2 enabled
[DEBUG] PNP: 002e.3 disabled
[DEBUG] PNP: 002e.5 enabled
[DEBUG] PNP: 002e.6 disabled
[DEBUG] PNP: 002e.7 disabled
[DEBUG] PNP: 002e.8 disabled
[DEBUG] PNP: 002e.108 disabled
[DEBUG] PNP: 002e.9 disabled
[DEBUG] PNP: 002e.109 disabled
[DEBUG] PNP: 002e.209 enabled
[DEBUG] PNP: 002e.309 disabled
[DEBUG] PNP: 002e.409 disabled
[DEBUG] PNP: 002e.509 disabled
[DEBUG] PNP: 002e.609 disabled
[DEBUG] PNP: 002e.709 disabled
[DEBUG] PNP: 002e.a enabled
[DEBUG] PNP: 002e.b enabled
[DEBUG] PNP: 002e.d disabled
[DEBUG] PNP: 002e.e disabled
[DEBUG] PNP: 002e.f disabled
[DEBUG] PNP: 002e.14 disabled
[DEBUG] PNP: 002e.16 disabled
[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 78 msecs
[DEBUG] PCI: 00:1f.3 scanning...
[DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 422 msecs
[DEBUG] scan_bus: bus Root Device finished in 438 msecs
[INFO ] done
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 452 ms
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ] Manufacturer: ef
[INFO ] SF: Detected ef 4017 with sector size 0x1000, total 0x800000
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 4 / 38 ms
[DEBUG] found VGA at PCI: 00:02.0
[DEBUG] Setting up VGA for PCI: 00:02.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ] Allocating resources...
[INFO ] Reading resources...
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
[DEBUG] TOUUD 0x27c600000 TOLUD 0x82a00000 TOM 0x200000000
[DEBUG] MEBASE 0x3ff000000
[DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT
[DEBUG] TSEG base 0x80000000 size 8M
[INFO ] Available memory below 4GB: 2048M
[INFO ] Available memory above 4GB: 6086M
[INFO ] Done reading resources.
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
[DEBUG] PCI: 00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 03:00.0 10 * [0x0 - 0xff] io
[DEBUG] PCI: 00:1c.4 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
[DEBUG] PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
[DEBUG] PCI: 00:1c.4 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG] PCI: 00:1c.5 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:1c.5 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:1c.5 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:1c.5 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:1c.5 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:1c.5 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
[DEBUG] update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
[DEBUG] update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
[DEBUG] update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
[DEBUG] update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
[DEBUG] update_constraints: PNP: 002e.b 62 base 00000000 limit 00000001 io (fixed)
[DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
[INFO ] DOMAIN: 0000: Resource ranges:
[INFO ] * Base: 1000, Size: f000, Tag: 100
[DEBUG] PCI: 00:1c.4 1c * [0x1000 - 0x1fff] limit: 1fff io
[DEBUG] PCI: 00:02.0 20 * [0x2000 - 0x203f] limit: 203f io
[DEBUG] PCI: 00:1f.2 20 * [0x2040 - 0x205f] limit: 205f io
[DEBUG] PCI: 00:1f.2 10 * [0x2060 - 0x2067] limit: 2067 io
[DEBUG] PCI: 00:1f.2 18 * [0x2068 - 0x206f] limit: 206f io
[DEBUG] PCI: 00:1f.2 14 * [0x2070 - 0x2073] limit: 2073 io
[DEBUG] PCI: 00:1f.2 1c * [0x2074 - 0x2077] limit: 2077 io
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
[DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 05 base 100000000 limit 27c5fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 09 base fed90000 limit fed90fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0a base fed91000 limit fed91fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
[INFO ] DOMAIN: 0000: Resource ranges:
[INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200
[INFO ] * Base: f4000000, Size: ac00000, Tag: 200
[INFO ] * Base: fec01000, Size: 18f000, Tag: 200
[INFO ] * Base: fed92000, Size: 26e000, Tag: 200
[INFO ] * Base: 27c600000, Size: d83a00000, Tag: 100200
[DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
[DEBUG] PCI: 00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem
[DEBUG] PCI: 00:1c.4 24 * [0x82a00000 - 0x82afffff] limit: 82afffff prefmem
[DEBUG] PCI: 00:14.0 10 * [0x82b00000 - 0x82b0ffff] limit: 82b0ffff mem
[DEBUG] PCI: 00:1b.0 10 * [0x82b10000 - 0x82b13fff] limit: 82b13fff mem
[DEBUG] PCI: 00:1f.2 24 * [0x82b14000 - 0x82b147ff] limit: 82b147ff mem
[DEBUG] PCI: 00:1a.0 10 * [0x82b15000 - 0x82b153ff] limit: 82b153ff mem
[DEBUG] PCI: 00:1d.0 10 * [0x82b16000 - 0x82b163ff] limit: 82b163ff mem
[DEBUG] PCI: 00:1f.3 10 * [0x82b17000 - 0x82b170ff] limit: 82b170ff mem
[DEBUG] PCI: 00:16.0 10 * [0x82b18000 - 0x82b1800f] limit: 82b1800f mem
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
[DEBUG] PCI: 00:1c.4 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff
[INFO ] PCI: 00:1c.4: Resource ranges:
[INFO ] * Base: 1000, Size: 1000, Tag: 100
[DEBUG] PCI: 03:00.0 10 * [0x1000 - 0x10ff] limit: 10ff io
[DEBUG] PCI: 00:1c.4 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done
[DEBUG] PCI: 00:1c.4 prefmem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff
[INFO ] PCI: 00:1c.4: Resource ranges:
[INFO ] * Base: 82a00000, Size: 100000, Tag: 1200
[DEBUG] PCI: 03:00.0 20 * [0x82a00000 - 0x82a03fff] limit: 82a03fff prefmem
[DEBUG] PCI: 03:00.0 18 * [0x82a04000 - 0x82a04fff] limit: 82a04fff prefmem
[DEBUG] PCI: 00:1c.4 prefmem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff done
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG] PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
[DEBUG] PCI: 00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
[DEBUG] PCI: 00:01.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 01 mem
[DEBUG] PCI: 00:02.0 10 <- [0x0082c00000 - 0x0082ffffff] size 0x00400000 gran 0x16 mem64
[DEBUG] PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io
[DEBUG] PCI: 00:14.0 10 <- [0x0082b00000 - 0x0082b0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG] PCI: 00:16.0 10 <- [0x0082b18000 - 0x0082b1800f] size 0x00000010 gran 0x04 mem64
[DEBUG] PCI: 00:1a.0 10 <- [0x0082b15000 - 0x0082b153ff] size 0x00000400 gran 0x0a mem
[DEBUG] PCI: 00:1b.0 10 <- [0x0082b10000 - 0x0082b13fff] size 0x00004000 gran 0x0e mem64
[DEBUG] PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
[DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
[DEBUG] PCI: 00:1c.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 02 mem
[DEBUG] PCI: 00:1c.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
[DEBUG] PCI: 00:1c.4 24 <- [0x0082a00000 - 0x0082afffff] size 0x00100000 gran 0x14 bus 03 prefmem
[DEBUG] PCI: 00:1c.4 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 03 mem
[DEBUG] PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
[DEBUG] PCI: 03:00.0 18 <- [0x0082a04000 - 0x0082a04fff] size 0x00001000 gran 0x0c prefmem64
[DEBUG] PCI: 03:00.0 20 <- [0x0082a00000 - 0x0082a03fff] size 0x00004000 gran 0x0e prefmem64
[DEBUG] PCI: 00:1c.5 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
[DEBUG] PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
[DEBUG] PCI: 00:1c.5 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 04 mem
[DEBUG] PCI: 04:00.0 1c <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x0c bus 05 io
[DEBUG] PCI: 04:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
[DEBUG] PCI: 04:00.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 05 mem
[DEBUG] PCI: 00:1c.6 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io
[DEBUG] PCI: 00:1c.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 06 prefmem
[DEBUG] PCI: 00:1c.6 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 06 mem
[DEBUG] PCI: 00:1c.7 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 07 io
[DEBUG] PCI: 00:1c.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 07 prefmem
[DEBUG] PCI: 00:1c.7 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 07 mem
[DEBUG] PCI: 00:1d.0 10 <- [0x0082b16000 - 0x0082b163ff] size 0x00000400 gran 0x0a mem
[DEBUG] PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
[DEBUG] PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
[DEBUG] PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
[DEBUG] PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
[DEBUG] PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
[DEBUG] PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
[DEBUG] PNP: 002e.209 e0 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq
[WARN ] PNP: 002e.a f2 irq size: 0x0000000001 not assigned in devicetree
[DEBUG] PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
[DEBUG] PNP: 002e.b 62 <- [0x0000000000 - 0x0000000001] size 0x00000002 gran 0x01 io
[DEBUG] PNP: 002e.b 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq
[WARN ] PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree
[DEBUG] PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io
[DEBUG] PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io
[DEBUG] PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io
[DEBUG] PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io
[DEBUG] PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
[DEBUG] PCI: 00:1f.2 24 <- [0x0082b14000 - 0x0082b147ff] size 0x00000800 gran 0x0b mem
[DEBUG] PCI: 00:1f.3 10 <- [0x0082b17000 - 0x0082b170ff] size 0x00000100 gran 0x08 mem64
[INFO ] Done setting resources.
[INFO ] Done allocating resources.
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 1058 ms
[INFO ] Enabling resources...
[DEBUG] PCI: 00:00.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:00.0 cmd <- 06
[DEBUG] PCI: 00:01.0 bridge ctrl <- 0013
[DEBUG] PCI: 00:01.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:01.0 cmd <- 00
[DEBUG] PCI: 00:02.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:02.0 cmd <- 03
[DEBUG] PCI: 00:14.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:14.0 cmd <- 102
[DEBUG] PCI: 00:16.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:16.0 cmd <- 02
[DEBUG] PCI: 00:1a.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1a.0 cmd <- 102
[DEBUG] PCI: 00:1b.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1b.0 cmd <- 102
[DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1c.0 cmd <- 100
[DEBUG] PCI: 00:1c.4 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.4 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1c.4 cmd <- 107
[DEBUG] PCI: 00:1c.5 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.5 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1c.5 cmd <- 100
[DEBUG] PCI: 00:1c.6 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.6 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1c.6 cmd <- 100
[DEBUG] PCI: 00:1c.7 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.7 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1c.7 cmd <- 100
[DEBUG] PCI: 00:1d.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1d.0 cmd <- 102
[DEBUG] PCI: 00:1f.0 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1f.0 cmd <- 107
[DEBUG] PCI: 00:1f.2 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1f.2 cmd <- 03
[DEBUG] PCI: 00:1f.3 subsystem <- 1043/84ca
[DEBUG] PCI: 00:1f.3 cmd <- 103
[DEBUG] PCI: 03:00.0 cmd <- 03
[DEBUG] PCI: 04:00.0 bridge ctrl <- 0013
[DEBUG] PCI: 04:00.0 cmd <- 00
[INFO ] done.
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 176 ms
[INFO ] Initializing devices...
[DEBUG] CPU_CLUSTER: 0 init
[DEBUG] MTRR: Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
[DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
[DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
[DEBUG] 0x0000000100000000 - 0x000000027c5fffff size 0x17c600000 type 6
[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] CPU physical address size: 36 bits
[DEBUG] MTRR: default type WB/UC MTRR counts: 4/4.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
[DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1
[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
[DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6

[DEBUG] MTRR check
[DEBUG] Fixed MTRRs : Enabled
[DEBUG] Variable MTRRs: Enabled

[DEBUG] CPU has 4 cores, 4 threads enabled.
[DEBUG] Setting up SMI for CPU
[INFO ] Will perform SMM setup.
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x14980 size 0x6800 in mcache @0x7ffdd0ac
[DEBUG] microcode: sig=0x306a9 pf=0x2 revision=0x21
[INFO ] CPU: Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz.
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 18 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000021
[INFO ] LAPIC 0x4 in XAPIC mode.
[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x00000021
[INFO ] LAPIC 0x6 in XAPIC mode.
[INFO ] AP: slot 3 apic_id 6, MCU rev: 0x00000021
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8
[DEBUG] Processing 11 relocs. Offset value of 0x00038000
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ff9203d
[DEBUG] Installing permanent SMM handler to 0x80000000
[DEBUG] FX_SAVE [0x802ff800-0x80300000]
[DEBUG] HANDLER [0x802fe000-0x802ff1e8]

[DEBUG] CPU 0
[DEBUG] ss0 [0x802fdc00-0x802fe000]
[DEBUG] stub0 [0x802f6000-0x802f61e8]

[DEBUG] CPU 1
[DEBUG] ss1 [0x802fd800-0x802fdc00]
[DEBUG] stub1 [0x802f5c00-0x802f5de8]

[DEBUG] CPU 2
[DEBUG] ss2 [0x802fd400-0x802fd800]
[DEBUG] stub2 [0x802f5800-0x802f59e8]

[DEBUG] CPU 3
[DEBUG] ss3 [0x802fd000-0x802fd400]
[DEBUG] stub3 [0x802f5400-0x802f55e8]

[DEBUG] stacks [0x80000000-0x80001000]
[DEBUG] Loading module at 0x802fe000 with entry 0x802fe2b9. filesize: 0x11d0 memsize: 0x11e8
[DEBUG] Processing 59 relocs. Offset value of 0x802fe000
[DEBUG] Loading module at 0x802f6000 with entry 0x802f6000. filesize: 0x1e8 memsize: 0x1e8
[DEBUG] Processing 11 relocs. Offset value of 0x802f6000
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
[DEBUG] SMM Module: placing smm entry code at 802f5c00, cpu # 0x1
[DEBUG] SMM Module: placing smm entry code at 802f5800, cpu # 0x2
[DEBUG] SMM Module: placing smm entry code at 802f5400, cpu # 0x3
[DEBUG] SMM Module: stub loaded at 802f6000. Will call 0x802fe2b9
[DEBUG] Initializing southbridge SMI...
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ee000, cpu = 0
[DEBUG] In relocation handler: cpu 0
[DEBUG] New SMBASE=0x802ee000 IEDBASE=0x80400000
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802edc00, cpu = 1
[DEBUG] In relocation handler: cpu 1
[DEBUG] New SMBASE=0x802edc00 IEDBASE=0x80400000
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed400, cpu = 3
[DEBUG] In relocation handler: cpu 3
[DEBUG] New SMBASE=0x802ed400 IEDBASE=0x80400000
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed800, cpu = 2
[DEBUG] In relocation handler: cpu 2
[DEBUG] New SMBASE=0x802ed800 IEDBASE=0x80400000
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device 306a9
[DEBUG] CPU: family 06, model 3a, stepping 09
[INFO ] CPU: Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz.
[INFO ] CPU: platform id 1
[INFO ] CPU: cpuid(1) 0x306a9
[INFO ] CPU: AES supported
[INFO ] CPU: TXT supported
[INFO ] CPU: VT supported
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] cpu: energy policy set to 6
[DEBUG] model_x06ax: frequency set to 3300
[INFO ] Turbo is available but hidden
[INFO ] Turbo is available and visible
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[INFO ] Initializing CPU #3
[DEBUG] CPU: vendor Intel device 306a9
[DEBUG] CPU: family 06, model 3a, stepping 09
[DEBUG] CPU: vendor Intel device 306a9
[DEBUG] CPU: family 06, model 3a, stepping 09
[INFO ] CPU: Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz.
[INFO ] Initializing CPU #2
[INFO ] CPU: platform id 1
[DEBUG] CPU: vendor Intel device 306a9
[DEBUG] CPU: family 06, model 3a, stepping 09
[INFO ] CPU: cpuid(1) 0x306a9
[INFO ] CPU: Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz.
[INFO ] CPU: Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz.
[INFO ] CPU: platform id 1
[INFO ] CPU: AES supported
[INFO ] CPU: TXT supported
[INFO ] CPU: VT supported
[INFO ] CPU: platform id 1
[DEBUG] VMX status: enabled
[INFO ] CPU: cpuid(1) 0x306a9
[INFO ] CPU: cpuid(1) 0x306a9
[DEBUG] IA32_FEATURE_CONTROL status: locked
[INFO ] CPU: AES supported
[INFO ] CPU: TXT supported
[INFO ] CPU: VT supported
[INFO ] CPU: AES supported
[INFO ] CPU: TXT supported
[INFO ] CPU: VT supported
[DEBUG] VMX status: enabled
[DEBUG] cpu: energy policy set to 6
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] model_x06ax: frequency set to 3300
[INFO ] CPU #1 initialized
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] cpu: energy policy set to 6
[DEBUG] cpu: energy policy set to 6
[DEBUG] model_x06ax: frequency set to 3300
[INFO ] CPU #2 initialized
[DEBUG] model_x06ax: frequency set to 3300
[INFO ] CPU #3 initialized
[INFO ] bsp_do_flight_plan done after 574 msecs.
[DEBUG] Initializing southbridge SMI...
[DEBUG] SMI_STS: 
[DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
[DEBUG] TCO_STS: 
[DEBUG] Locking SMM.
[DEBUG] CPU_CLUSTER: 0 init finished in 862 msecs
[DEBUG] PCI: 00:00.0 init
[DEBUG] Disabling PEG12.
[DEBUG] Disabling PEG11.
[DEBUG] Disabling Device 4.
[DEBUG] Disabling PEG60.
[DEBUG] Disabling Device 7.
[DEBUG] Set BIOS_RESET_CPL
[DEBUG] CPU TDP: 77 Watts
[DEBUG] PCI: 00:00.0 init finished in 22 msecs
[DEBUG] PCI: 00:01.0 init
[DEBUG] PCI: 00:01.0 init finished in 0 msecs
[DEBUG] PCI: 00:02.0 init
[INFO ] CBFS: Found 'vbt.bin' @0x40c00 size 0x569 in mcache @0x7ffdd220
[INFO ] Found a VBT of 7168 bytes after decompression
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[DEBUG] GT Power Management Init
[DEBUG] IVB GT1 Power Meter Weights
[DEBUG] GT Power Management Init (post VBIOS)

[2.732473] CONFIG =>
[2.734374] (Primary =>
[2.736795] (Port => Analog ,
[2.739908] Framebuffer =>
[2.742761] (Width => 640,
[2.746132] Height => 400,
[2.749504] Start_X => 0,
[2.752703] Start_Y => 0,
[2.755902] Stride => 1,
[2.759101] V_Stride => 1,
[2.762300] Tiling => Linear ,
[2.766018] Rotation => No_Rotation,
[2.770081] Offset => 0xffffffff,
[2.773799] BPC => 8),
[2.776824] Mode =>
[2.779073] (Dotclock => 108000000,
[2.783742] H_Visible => 1280,
[2.787978] H_Sync_Begin => 1328,
[2.792216] H_Sync_End => 1440,
[2.796453] H_Total => 1688,
[2.800689] V_Visible => 1024,
[2.804926] V_Sync_Begin => 1025,
[2.809163] V_Sync_End => 1028,
[2.813399] V_Total => 1066,
[2.817635] H_Sync_Active_High => True,
[2.821871] V_Sync_Active_High => True,
[2.826107] BPC => 5)),
[2.830258] Secondary =>
[2.832679] (Port => Disabled,
[2.835791] Framebuffer =>
[2.838643] (Width => 1,
[2.841842] Height => 1,
[2.845042] Start_X => 0,
[2.848240] Start_Y => 0,
[2.851439] Stride => 1,
[2.854637] V_Stride => 1,
[2.857836] Tiling => Linear ,
[2.861554] Rotation => No_Rotation,
[2.865618] Offset => 0x00000000,
[2.869335] BPC => 8),
[2.872362] Mode =>
[2.874610] (Dotclock => 1000000,
[2.879105] H_Visible => 1,
[2.883082] H_Sync_Begin => 1,
[2.887059] H_Sync_End => 1,
[2.891037] H_Total => 1,
[2.895014] V_Visible => 1,
[2.898991] V_Sync_Begin => 1,
[2.902968] V_Sync_End => 1,
[2.906945] V_Total => 1,
[2.910922] H_Sync_Active_High => False,
[2.915244] V_Sync_Active_High => False,
[2.919568] BPC => 5)),
[2.923718] Tertiary =>
[2.926138] (Port => Disabled,
[2.929250] Framebuffer =>
[2.932103] (Width => 1,
[2.935302] Height => 1,
[2.938501] Start_X => 0,
[2.941699] Start_Y => 0,
[2.944898] Stride => 1,
[2.948096] V_Stride => 1,
[2.951295] Tiling => Linear ,
[2.955013] Rotation => No_Rotation,
[2.959077] Offset => 0x00000000,
[2.962795] BPC => 8),
[2.965820] Mode =>
[2.968068] (Dotclock => 1000000,
[2.972564] H_Visible => 1,
[2.976542] H_Sync_Begin => 1,
[2.980518] H_Sync_End => 1,
[2.984497] H_Total => 1,
[2.988474] V_Visible => 1,
[2.992451] V_Sync_Begin => 1,
[2.996428] V_Sync_End => 1,
[3.000405] V_Total => 1,
[3.004381] H_Sync_Active_High => False,
[3.008704] V_Sync_Active_High => False,
[3.013027] BPC => 5)));
[DEBUG] PCI: 00:02.0 init finished in 330 msecs
[DEBUG] PCI: 00:14.0 init
[DEBUG] XHCI: Setting up controller.. done.
[DEBUG] PCI: 00:14.0 init finished in 4 msecs
[DEBUG] PCI: 00:16.0 init
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : YES
[DEBUG] ME: Manufacturing Mode : YES
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : Host Communication
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
[DEBUG] ME: Progress Phase State : Host communication established
[NOTE ] ME: BIOS path: Normal
[DEBUG] ME: me_state=0, me_state_prev=0
[DEBUG] ME: Extend SHA-256: 1184469a774dddb5fc671a60339db09bc5441794ea02c5e1731bd1d83cda295e
[INFO ] ME: MBP item header 00020103
[INFO ] ME: MBP item header 00050102
[INFO ] ME: MBP item header 00020501
[INFO ] ME: MBP item header 00020201
[INFO ] ME: MBP item header 02030101
[INFO ] ME: MBP item header 02060301
[INFO ] ME: MBP item header 02090401
[DEBUG] ME: found version 8.1.2.1318
[DEBUG] ME Capability: Full Network manageability : disabled
[DEBUG] ME Capability: Regular Network manageability : disabled
[DEBUG] ME Capability: Manageability : disabled
[DEBUG] ME Capability: Small business technology : disabled
[DEBUG] ME Capability: Level III manageability : disabled
[DEBUG] ME Capability: IntelR Anti-Theft (AT) : disabled
[DEBUG] ME Capability: IntelR Capability Licensing Service (CLS) : enabled
[DEBUG] ME Capability: IntelR Power Sharing Technology (MPC) : enabled
[DEBUG] ME Capability: ICC Over Clocking : enabled
[DEBUG] ME Capability: Protected Audio Video Path (PAVP) : enabled
[DEBUG] ME Capability: IPV6 : disabled
[DEBUG] ME Capability: KVM Remote Control (KVM) : disabled
[DEBUG] ME Capability: Outbreak Containment Heuristic (OCH) : disabled
[DEBUG] ME Capability: Virtual LAN (VLAN) : enabled
[DEBUG] ME Capability: TLS : disabled
[DEBUG] ME Capability: Wireless LAN (WLAN) : disabled
[DEBUG] PCI: 00:16.0 init finished in 232 msecs
[DEBUG] PCI: 00:1a.0 init
[DEBUG] EHCI: Setting up controller.. done.
[DEBUG] PCI: 00:1a.0 init finished in 4 msecs
[DEBUG] PCI: 00:1b.0 init
[DEBUG] Azalia: base = 0x82b10000
[DEBUG] Azalia: codec_mask = 09
[DEBUG] azalia_audio: Initializing codec #3
[DEBUG] azalia_audio: codec viddid: 80862806
[DEBUG] azalia_audio: verb_size: 16
[DEBUG] azalia_audio: verb loaded.
[DEBUG] azalia_audio: Initializing codec #0
[DEBUG] azalia_audio: codec viddid: 10ec0887
[DEBUG] azalia_audio: verb_size: 60
[DEBUG] azalia_audio: verb loaded.
[DEBUG] PCI: 00:1b.0 init finished in 46 msecs
[DEBUG] PCI: 00:1c.0 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.0 init finished in 4 msecs
[DEBUG] PCI: 00:1c.4 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.4 init finished in 4 msecs
[DEBUG] PCI: 00:1c.5 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.5 init finished in 4 msecs
[DEBUG] PCI: 00:1c.6 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.6 init finished in 4 msecs
[DEBUG] PCI: 00:1c.7 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.7 init finished in 4 msecs
[DEBUG] PCI: 00:1d.0 init
[DEBUG] EHCI: Setting up controller.. done.
[DEBUG] PCI: 00:1d.0 init finished in 4 msecs
[DEBUG] PCI: 00:1f.0 init
[DEBUG] pch: lpc_init
[INFO ] PCH: detected Z77, device id: 0x1e44, rev id 0x4
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG] IOAPIC: ID = 0x02
[DEBUG] IOAPIC: 24 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
[INFO ] Set power off after power failure.
[INFO ] NMI sources disabled.
[DEBUG] PantherPoint PM init
[DEBUG] RTC: failed = 0x0
[DEBUG] RTC Init
[DEBUG] apm_control: Disabling ACPI.
[DEBUG] APMC done.
[DEBUG] pch_spi_init
[DEBUG] PCI: 00:1f.0 init finished in 56 msecs
[DEBUG] PCI: 00:1f.2 init
[DEBUG] SATA: Initializing...
[DEBUG] SATA: Controller in AHCI mode.
[DEBUG] ABAR: 0x82b14000
[DEBUG] PCI: 00:1f.2 init finished in 10 msecs
[DEBUG] PCI: 00:1f.3 init
[DEBUG] PCI: 00:1f.3 init finished in 0 msecs
[DEBUG] PCI: 03:00.0 init
[INFO ] CBFS: Found 'rt8168-macaddress' @0x40bc0 size 0x11 in mcache @0x7ffdd1f4
[DEBUG] r8168: Resetting NIC...done
[DEBUG] r8168: Programming MAC Address...done
[INFO ] rtl: Enable ASPM L1.2
[DEBUG] PCI: 03:00.0 init finished in 20 msecs
[DEBUG] PNP: 002e.2 init
[DEBUG] PNP: 002e.2 init finished in 0 msecs
[DEBUG] PNP: 002e.5 init
[DEBUG] PNP: 002e.5 init finished in 0 msecs
[DEBUG] PNP: 002e.209 init
[DEBUG] PNP: 002e.209 init finished in 0 msecs
[DEBUG] PNP: 002e.a init
[DEBUG] PNP: 002e.a init finished in 0 msecs
[DEBUG] PNP: 002e.b init
[DEBUG] PNP: 002e.b init finished in 0 msecs
[INFO ] Devices initialized
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 601 / 1207 ms
[INFO ] Finalize devices...
[DEBUG] PCI: 00:1f.0 final
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[INFO ] Devices finalized
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 5 / 16 ms
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3e900 size 0x2277 in mcache @0x7ffdd1c8
[WARN ] CBFS: 'fallback/slic' not found.
[INFO ] ACPI: Writing ACPI tables at 7ff34000.
[DEBUG] ACPI: * FACS
[DEBUG] ACPI: * DSDT
[DEBUG] ACPI: * FADT
[DEBUG] ACPI: added table 1/32, length now 40
[DEBUG] ACPI: * SSDT
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
[DEBUG] PSS: 3301MHz power 77000 control 0x2500 status 0x2500
[DEBUG] PSS: 3300MHz power 77000 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 61574 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 50381 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 39989 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 30410 control 0x1000 status 0x1000
[DEBUG] PSS: 3301MHz power 77000 control 0x2500 status 0x2500
[DEBUG] PSS: 3300MHz power 77000 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 61574 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 50381 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 39989 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 30410 control 0x1000 status 0x1000
[DEBUG] PSS: 3301MHz power 77000 control 0x2500 status 0x2500
[DEBUG] PSS: 3300MHz power 77000 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 61574 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 50381 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 39989 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 30410 control 0x1000 status 0x1000
[DEBUG] PSS: 3301MHz power 77000 control 0x2500 status 0x2500
[DEBUG] PSS: 3300MHz power 77000 control 0x2100 status 0x2100
[DEBUG] PSS: 2800MHz power 61574 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 50381 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 39989 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 30410 control 0x1000 status 0x1000
[DEBUG] PCI space above 4GB MMIO is at 0x27c600001, len = 0xd839fffff
[DEBUG] Generating ACPI PIRQ entries
[DEBUG] ACPI: added table 2/32, length now 44
[DEBUG] ACPI: * MCFG
[DEBUG] ACPI: added table 3/32, length now 48
[DEBUG] ACPI: * MADT
[DEBUG] ACPI: added table 4/32, length now 52
[DEBUG] current = 7ff37b50
[DEBUG] ACPI: * DMAR
[DEBUG] ACPI: added table 5/32, length now 56
[DEBUG] current = 7ff37c10
[DEBUG] ACPI: * HPET
[DEBUG] ACPI: added table 6/32, length now 60
[INFO ] ACPI: done.
[DEBUG] ACPI tables: 15440 bytes.
[DEBUG] smbios_write_tables: 7ff2c000
[DEBUG] SMBIOS firmware version is set to coreboot_version: '4.17-27-gc07b88c052'
[INFO ] Create SMBIOS type 16
[INFO ] Create SMBIOS type 17
[INFO ] Create SMBIOS type 20
[DEBUG] SMBIOS tables: 796 bytes.
[DEBUG] Writing table forward entry at 0x00000500
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum ffe8
[DEBUG] Writing coreboot table at 0x7ff58000
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG] 3. 0000000000100000-000000007ff2bfff: RAM
[DEBUG] 4. 000000007ff2c000-000000007ff74fff: CONFIGURATION TABLES
[DEBUG] 5. 000000007ff75000-000000007ffccfff: RAMSTAGE
[DEBUG] 6. 000000007ffcd000-000000007fffffff: CONFIGURATION TABLES
[DEBUG] 7. 0000000080000000-00000000829fffff: RESERVED
[DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED
[DEBUG] 9. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG] 10. 0000000100000000-000000027c5fffff: RAM
[DEBUG] Wrote coreboot table at: 0x7ff58000, 0x3c8 bytes, checksum f2e1
[DEBUG] coreboot table: 992 bytes.
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
[DEBUG] RO MCACHE 3. 0x7ffdd000 0x000003a4
[DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910
[DEBUG] MRC DATA 5. 0x7ffdb000 0x00000644
[DEBUG] MEM INFO 6. 0x7ffda000 0x00000768
[DEBUG] AFTER CAR 7. 0x7ffcd000 0x0000d000
[DEBUG] RAMSTAGE 8. 0x7ff74000 0x00059000
[DEBUG] SMM BACKUP 9. 0x7ff64000 0x00010000
[DEBUG] IGD OPREGION10. 0x7ff60000 0x000030b8
[DEBUG] COREBOOT 11. 0x7ff58000 0x00008000
[DEBUG] ACPI 12. 0x7ff34000 0x00024000
[DEBUG] SMBIOS 13. 0x7ff2c000 0x00008000
[DEBUG] IMD small region:
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
[DEBUG] FMAP 1. 0x7fffeb20 0x000000e0
[DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004
[DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8
[DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 461 ms
[INFO ] CBFS: Found 'fallback/payload' @0x468c0 size 0x11bf9 in mcache @0x7ffdd2bc
[DEBUG] Checking segment from ROM address 0xfff56aec
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
[DEBUG] Checking segment from ROM address 0xfff56b08
[DEBUG] Loading segment from ROM address 0xfff56aec
[DEBUG] code (compression=1)
[DEBUG] New segment dstaddr 0x000de6e0 memsize 0x21920 srcaddr 0xfff56b24 filesize 0x11bc1
[DEBUG] Loading Segment: addr: 0x000de6e0 memsz: 0x0000000000021920 filesz: 0x0000000000011bc1
[DEBUG] using LZMA
[DEBUG] Loading segment from ROM address 0xfff56b08
[DEBUG] Entry Point 0x000fd28c
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 21 / 66 ms
[DEBUG] ICH-NM10-PCH: watchdog disabled
[DEBUG] Jumping to boot code at 0x000fd28c(0x7ff58000)
SeaBIOS (version rel-1.16.0-0-gd239552)
BUILD: gcc: (coreboot toolchain v2022-05-30_74129e5141) 11.2.0 binutils: (GNU Binutils) 2.37
SeaBIOS (version rel-1.16.0-0-gd239552)
BUILD: gcc: (coreboot toolchain v2022-05-30_74129e5141) 11.2.0 binutils: (GNU Binutils) 2.37
Found coreboot cbmem console @ 7ffde000
Found mainboard ASUS P8Z77-V LX2
Relocating init from 0x000dfe40 to 0x7fedeaa0 (size 54464)
Found CBFS header at 0xfff1022c
multiboot: eax=7fface3c, ebx=7fface04
Found 17 PCI devices (max PCI bus is 07)
Copying SMBIOS from 0x7ff2c000 to 0x000f61e0
Copying SMBIOS 3.0 from 0x7ff2c020 to 0x000f61c0
Copying ACPI RSDP from 0x7ff34000 to 0x000f6190
table(50434146)=0x7ff36510 (via xsdt)
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
Start SeaVGABIOS (version rel-1.16.0-0-gd239552)
VGABUILD: gcc: (coreboot toolchain v2022-05-30_74129e5141) 11.2.0 binutils: (GNU Binutils) 2.37
enter vga_post:
a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000
si=00000000 di=00006600 bp=00000000 sp=00006dae cs=f000 ip=d059 f=0000
coreboot vga init
Did not find coreboot framebuffer - assuming EGA text
Attempting to allocate 512 bytes lowmem via pmm call to f000:d0d1
pmm call arg1=0
VGA stack allocated at ec840
Hooking hardware timer irq (old=f000fea5 new=c0003f59)
Turning on vga text mode console
set VGA mode 3
SeaBIOS (version rel-1.16.0-0-gd239552)
PCI: XHCI at 00:14.0 (mmio 0x82b00000)
XHCI init: regs @ 0x82b00000, 8 ports, 32 slots, 32 byte contexts
XHCI protocol USB 2.00, 4 ports (offset 1), def 3001
XHCI protocol USB 3.00, 4 ports (offset 5), def 1000
XHCI extcap 0xc1 @ 0x82b08040
XHCI extcap 0xc0 @ 0x82b08070
XHCI extcap 0x1 @ 0x82b08330
EHCI init on dev 00:1a.0 (regs=0x82b15020)
EHCI init on dev 00:1d.0 (regs=0x82b16020)
AHCI controller at 00:1f.2, iobase 0x82b14000, irq 11
Searching bootorder for: HALT
Found 0 lpt ports
Found 1 serial ports
Searching bootorder for: /rom@img/memtest
XHCI no devices found
ehci_wait_td error - status=80e42
USB mouse initialized
Initialized USB HUB (0 ports used)
PS2 keyboard initialized
Initialized USB HUB (0 ports used)
Initialized USB HUB (1 ports used)
All threads complete.
Scan for option roms

Press ESC for boot menu.

Searching bootorder for: HALT
Space available for UMB: c7800-ea000, f5a00-f6170
Returned 184320 bytes of ZoneHigh
e820 map has 8 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007ff19000 = 1 RAM
4: 000000007ff19000 - 0000000082a00000 = 2 RESERVED
5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
7: 0000000100000000 - 000000027c600000 = 1 RAM
enter handle_19:
NULL
Booting from CBFS...
Run img/memtest
Calling addr 0x00010000
INE_SCROLL;24rMemtest86+ 5.01 coreboot 002| Time: 0:00:00Pass %Test %Test #Testing: Pattern: CLK: (32b Mode)L1 Cache: Unknown L2 Cache: Unknown L3 Cache: None Memory : ------------------------------------------------------------------------------Core#:State:Cores: Active / Total (Run: All) | Pass: 0 Errors: 0 ------------------------------------------------------------------------------| Chipset : Unknown| Memory Type : Unknown| | | | | | (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock8133MIntel(R) Core(TM) i5-3550 CPU @ 3.30GHzMHz3293 K 32MB/s109753 K 256MB/s49887 K 6144MB/s37415==> Press F1 to enter Fail-Safe Mode <====> Press F2 to force Multi-Threading (SMP) <==  0S1(SMP: Disabled)Running...RAM: 399 MHz (DDR3-798)- BCLK: 99Timings: CAS 9-9-9-24@ 64-bit ModeASUSP8Z77-V LX2(CPU0)Memory SPD Informations--------------------------- Slot :08192MBDDR3-1066-CorsairCMD16GX3M2A1866C10*XMP*- Slot :18192MBDDR3-1066-CorsairCMD16GX3M2A1866C10*XMP*0| CPU Temp| CPAE Mode)X64 Mode)

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x101f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x0
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x10500126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x50
[NOTE ] ME: Current PM event: 0x0
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : uKernel Phase
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
[DEBUG] ME: Progress Phase State : Unknown 0x00
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inacti

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inac

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inactive


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[D
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inact 

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC 

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inactive


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inac

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] 

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC inactive

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC 

[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 bootblock starting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes)
[INFO ] CBFS: mcache @0xfeff0e00 built for 18 files, used 0x3a4 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14858 in mcache @0xfeff0e2c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 44 ms


[NOTE ] coreboot-4.17-27-gc07b88c052 Sun Jun 5 07:48:49 UTC 2022 romstage starting (log level: 7)...
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done
[DEBUG] Initializing Graphics...
[DEBUG] Back from systemagent_early_init()
[INFO ] Intel ME early init
[INFO ] Intel ME firmware is ready
[DEBUG] ME: Requested 16MB UMA
[DEBUG] Starting native Platform init
[DEBUG] DMI: Running at X4 @ 5000MT/s
[DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes)
[DEBUG] Trying stored timings.
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
[DEBUG] 100MHz reference clock support: yes
[DEBUG] PLL_REF100_CFG value: 0x7
[DEBUG] Trying CAS 11, tCK 320.
[DEBUG] Trying CAS 10, tCK 365.
[DEBUG] Trying CAS 9, tCK 384.
[DEBUG] Found compatible clock, CAS pair.
[DEBUG] Selected DRAM frequency: 666 MHz
[DEBUG] Selected CAS latency : 9T
[DEBUG] MPLL busy... done in 10 us
[DEBUG] MPLL frequency is set at : 666 MHz
[DEBUG] XOVER CLK [c14] = 0
[DEBUG] XOVER CMD [320c] = 4000
[DEBUG] XOVER CLK [d14] = c000000
[DEBUG] XOVER CMD [330c] = 4004000
[DEBUG] DBP [4000] = 187999
[DEBUG] RAP [4004] = ca145454
[DEBUG] OTHP [400c] = 6690
[DEBUG] OTHP [400c] = 6690
[DEBUG] REFI [4298] = 5aae1450
[DEBUG] SRFTP [42a4] = 41f97200
[DEBUG] DBP [4400] = 187999
[DEBUG] RAP [4404] = ca145454
[DEBUG] OTHP [440c] = 6690
[DEBUG] OTHP [440c] = 6690
[DEBUG] REFI [4698] = 5aae1450
[DEBUG] SRFTP [46a4] = 41f97200
[DEBUG] Done dimm mapping
[DEBUG] Update PCI-E configuration space:
[DEBUG] PCI(0, 0, 0)[a0] = 0
[DEBUG] PCI(0, 0, 0)[a4] = 2
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
[DEBUG] PCI(0, 0, 0)[a8] = 7c600000
[DEBUG] PCI(0, 0, 0)[ac] = 2
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
[DEBUG] PCI(0, 0, 0)[7c] = 7f
[DEBUG] PCI(0, 0, 0)[70] = ff000000
[DEBUG] PCI(0, 0, 0)[74] = 1
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
[DEBUG] Done memory map
[DEBUG] RCOMP...done
[DEBUG] COMP2 done
[DEBUG] COMP1 done
[DEBUG] FORCE RCOMP and wait 20us...done
[DEBUG] Done io registers
[DEBUG] CPE
[DEBUG] CP5b
[DEBUG] CP5c
[DEBUG] OTHP [440c] = 6690
[DEBUG] t123: 1912, 6000, 7620
[NOTE ] ME: FWS2: 0x131f0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x1f
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] PASSED! Tell ME that DRAM is ready
[NOTE ] ME: FWS2: 0x132c0126
[NOTE ] ME: Bist in progress: 0x0
[NOTE ] ME: ICC Status : 0x3
[NOTE ] ME: Invoke MEBx : 0x0
[NOTE ] ME: CPU replaced : 0x0
[NOTE ] ME: MBP ready : 0x1
[NOTE ] ME: MFS failure : 0x0
[NOTE ] ME: Warm reset req : 0x0
[NOTE ] ME: CPU repl valid : 0x1
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: FW update req : 0x0
[NOTE ] ME: (Reserved) : 0x0
[NOTE ] ME: Current state : 0x2c
[NOTE ] ME: Current PM event: 0x3
[NOTE ] ME: Progress code : 0x1
[NOTE ] ME: Requested BIOS Action: Continue to boot
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Global reset after an error
[DEBUG] ME: Progress Phase State : M0 kernel load
[DEBUG] memcfg DDR3 ref clock 133 MHz
[DEBUG] memcfg DDR3 clock 1330 MHz
[DEBUG] memcfg channel assignment: A: 1, B 0, C 2
[DEBUG] memcfg channel[0] config (00000000):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode off
[DEBUG] rank interleave off
[DEBUG] DIMMA 0 MB width x8 single rank, selected
[DEBUG] DIMMB 0 MB width x8 single rank
[DEBUG] memcfg channel[1] config (00630020):
[DEBUG] ECC i.
** read zero bytes from stdin **

Terminating...
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