flashrom

According to the follow up comment post-merge:

"Are we sure about this? the datasheet explicitly mentions the sequence: CS# goes low -> sending Enter 4-Byte mode command -> CS# goes high."

Nikolai can you validate this commit with a datasheet please?

IIUC, the comment is about whether enter 4BA command is permitted after a WREN command.

The "CS# goes low -> sending Enter 4-Byte mode command -> CS# goes high." part of the datasheet seems to just be describing the a minimal transaction for issuing an enter 4BA command, I don't think it's saying anything about whether it's permitted after a WREN or not.

We'd probably need to test, but flashrom isn't capable of that right now.

Nikolai Artemiev wrote in #note-4:

IIUC, the comment is about whether enter 4BA command is permitted after a WREN command.

Actually, if it is only permitted after WREN. IOW, if WREN is needed.

The "CS# goes low -> sending Enter 4-Byte mode command -> CS# goes high." part of the datasheet seems to just be describing the a minimal transaction for issuing an enter 4BA command, I don't think it's saying anything about whether it's permitted after a WREN or not.

Ack. I misread that. WREN would have its own CS#low/high sequence. Still if one looks at the WREN description, EN4B is not mentioned.

We'd probably need to test, but flashrom isn't capable of that right now.

You can replace FEATURE_4BA_WREN with FEATURE_4BA_ENTER, if reading >16MiB works, WREN is not needed (requires a programmer that supports 4BA modes).

I have tested a GD25Q256D with it's current definition at head using a ft2232_spi programmer - the read, write, erase, and verify functions worked correctly.

I've tested and found WREN is not needed, so we should change the chip definition for 1.3.

Here is a patch to update the chip definition: https://review.coreboot.org/c/flashrom/+/70342