I can see in cbmem.log that your CPU is an Intel(R) Core(TM) i5-4300M CPU @ 2.60GHz. According to Intel ARK [1], the processor only supports a maximum of 1600 MT/s. As the MRC binary was designed with Chrome-devices (Chromebooks and such) in mind, it is expected that it doesn't support higher frequencies.
More specifically, the code inside mrc.bin that prints the message you see is something like this:
/* Some other code exists before reaching this point */
switch (pei_data.max_ddr_freq) {
case 1600:
mrcdata.ddrfreq = 1600;
break;
case 1333:
mrcdata.ddrfreq = 1333;
break;
case 1067:
mrcdata.ddrfreq = 1067;
break;
case 800:
mrcdata.ddrfreq = 800;
break;
default:
printf("System Agent: Unsupported DDR3 frequence %d (Supported are 800, 1067, 1333, 1600)\n", ddr_freq);
/* This value is returned by mrc.bin and is handled on sdram_initialize() in raminit.c */
return -2;
}
/* Continue with memory initialization */
Note that patching out this code in the binary will not be enough. The MRC binary contains many tables with optimal calibration parameters, and these values depend on the memory frequency. It is very likely that mrc.bin only contains the values for the speeds it supports.
If you still want to overclock your memory on Haswell, I would try to change the memory timings, which are stored on an EEPROM on the DIMMs. With coreboot, you don't need to reflash the EEPROM on the sticks: you can put the modified SPD data in CBFS and make the mrc.bin use that. You can see how to do that on some other boards, which use memory-down (RAM chips soldered on the mainboard, no SPD EEPROM).
Best regards,
Angel
[1]: https://ark.intel.com/content/www/us/en/ark/products/76347/intel-core-i5-4300m-processor-3m-cache-up-to-3-30-ghz.html