Bug #243
openT440P: Unable to initialize memory speeds above 1600 MT/s
0%
Description
I just bought a pair of HyperX DDR3L-2133 CL11 memory. They are supported and run fine at 2133 MT/s with the original Lenovo firmware.
However Coreboot only registers them at 1600 MT/s.
What logs do you need to analyze this problem?
Files
Updated by Peter Lap about 5 years ago
System Agent: Starting up...
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)
System Agent: Initializing PCH (SA Init)
System Agent: Initializing PCH (Me UMA)
System Agent: Initializing Memory
System Agent: Done.
Sanity checking heap.
System Agent Version 1.6.1 Build 2
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B 1, C 2
memcfg channel[0] config (00620020):
ECC inactive
enhanced interleave mode on
rank interleave on
DIMMA 8192 MB width x8 or x32 dual rank, selected
DIMMB 0 MB width x8 or x32 single rank
memcfg channel[1] config (00620020):
ECC inactive
enhanced interleave mode on
rank interleave on
DIMMA 8192 MB width x8 or x32 dual rank, selected
DIMMB 0 MB width x8 or x32 single rank
While researching I found this interesting plaintext notice in the mrc.bin.
...
^@System Agent: Unsupported DDR3 frequence %d (Supported are 800, 1067, 1333, 1600)
^@System Agent: Initializing PCH
...
Does coreboot adhere to this mrc limitation?
Updated by Peter Lap about 5 years ago
Changing the value of .max_ddr3_freq to 2133 in src/mainboard/lenovo/t440p/romstage.c leads to a bricked notebook. A beeping sound occurs, regardless of the installed memory type (1600 or 2133).
Updated by Angel Pons almost 5 years ago
I can see in cbmem.log that your CPU is an Intel(R) Core(TM) i5-4300M CPU @ 2.60GHz. According to Intel ARK [1], the processor only supports a maximum of 1600 MT/s. As the MRC binary was designed with Chrome-devices (Chromebooks and such) in mind, it is expected that it doesn't support higher frequencies.
More specifically, the code inside mrc.bin that prints the message you see is something like this:
/* Some other code exists before reaching this point */
switch (pei_data.max_ddr_freq) {
case 1600:
mrcdata.ddrfreq = 1600;
break;
case 1333:
mrcdata.ddrfreq = 1333;
break;
case 1067:
mrcdata.ddrfreq = 1067;
break;
case 800:
mrcdata.ddrfreq = 800;
break;
default:
printf("System Agent: Unsupported DDR3 frequence %d (Supported are 800, 1067, 1333, 1600)\n", ddr_freq);
/* This value is returned by mrc.bin and is handled on sdram_initialize() in raminit.c */
return -2;
}
/* Continue with memory initialization */
Note that patching out this code in the binary will not be enough. The MRC binary contains many tables with optimal calibration parameters, and these values depend on the memory frequency. It is very likely that mrc.bin only contains the values for the speeds it supports.
If you still want to overclock your memory on Haswell, I would try to change the memory timings, which are stored on an EEPROM on the DIMMs. With coreboot, you don't need to reflash the EEPROM on the sticks: you can put the modified SPD data in CBFS and make the mrc.bin use that. You can see how to do that on some other boards, which use memory-down (RAM chips soldered on the mainboard, no SPD EEPROM).
Best regards,
Angel