Bug #126
closed
*AGESA: Fix UMA calculations* breaks boot on ASRock E350M1
Added by Paul Menzel almost 7 years ago.
Updated almost 7 years ago.
Description
Since commit 61be3603f4 (AGESA: Fix UMA calculations) the ASRock E350M1 hangs during boot.
$ git bisect log
git bisect start
# bad: [837da6ade7aebe9541b5a13e40b75ab2b308ac77] libpayload: Add mouse cursor driver
git bisect bad 837da6ade7aebe9541b5a13e40b75ab2b308ac77
# good: [6c4e57487239e773f6135bb9cda4fba7f35059d0] google/gru: support 800M/928M frequency for bob
git bisect good 6c4e57487239e773f6135bb9cda4fba7f35059d0
# bad: [a038835716b3a09bd3d5ab3fd7e3d48d3c3a6f13] arch/x86/acpigen: Add additional opcodes
git bisect bad a038835716b3a09bd3d5ab3fd7e3d48d3c3a6f13
# bad: [34dba35831f8c46ea96a9049737b4a367b1b6460] rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further back
git bisect bad 34dba35831f8c46ea96a9049737b4a367b1b6460
# bad: [d906bb68c3be218046d257c6870c9636e0e198cf] cbmem_console: Improve 'cbmem -1' behavior for truncated pre-CBMEM logs
git bisect bad d906bb68c3be218046d257c6870c9636e0e198cf
# good: [fe6052c2e4090d15299435a27226a96f79d24872] src/include/device: Add PCIe root ports device ids
git bisect good fe6052c2e4090d15299435a27226a96f79d24872
# good: [4f7d536ed375d6aafc7cc5971dc51a7bc4a021fb] mb/google/eve: Update touchpad I2C timing
git bisect good 4f7d536ed375d6aafc7cc5971dc51a7bc4a021fb
# good: [ae6a4b6d3ca60fc697103cbdaaf5df84502f554e] intel/common/block/i2c: Add common block for I2C and use the same in SoCs
git bisect good ae6a4b6d3ca60fc697103cbdaaf5df84502f554e
# bad: [e87564ffe7d0636699467b776a24adffb2f11cca] binaryPI: Fix UMA calculations
git bisect bad e87564ffe7d0636699467b776a24adffb2f11cca
# good: [17bb225be7dd031b9803f33dec88e9d53e3a582f] AMD MTRR: Add common add_uma_resource_below_tolm()
git bisect good 17bb225be7dd031b9803f33dec88e9d53e3a582f
# bad: [61be3603f4b9f353e605d7b7c8d0d9f3b90f5636] AGESA: Fix UMA calculations
git bisect bad 61be3603f4b9f353e605d7b7c8d0d9f3b90f5636
# first bad commit: [61be3603f4b9f353e605d7b7c8d0d9f3b90f5636] AGESA: Fix UMA calculations
The serial console shows the following.
======= Wed Jun 28 08:03:44 2017 (adjust=86.8us)
00.000: <00>
01.051: <00>
02.755: <00>
05.027: <00>
06.163: <00>
09.002: <00>
10.138: <00>
12.978: <00>
15.250: <00>
16.954: <00>
18.658: <00>
20.930: <00>
22.633: <00>
24.905: <00>
27.177: <00>
28.881: <00>
30.585: <00>
32.857: <00>
35.696: <00>
36.832: <00>
36.867: <16>4<ac>H <ac><1a>T<10><b6>H(<fb>S$
36.867:
36.867: coreboot-4.6-146-g61be3603f4 Thu May 18 04:48:57 UTC 2017 romstage starting...
36.867: APIC 00: CPU Family_Model = 00500f20
36.870: agesawrapper_amdinitreset() returned AGESA_SUCCESS
37.032: agesawrapper_amdinitearly() returned AGESA_SUCCESS
37.033: Normal boot
37.133: agesawrapper_amdinitpost() returned AGESA_SUCCESS
37.135: Move CAR stack.
37.135: CAR disabled.
37.136: Normal boot postcar
37.136: Wiped HEAP at [10000000 - 1002ffff]
37.149: agesawrapper_amdinitenv() returned AGESA_SUCCESS
37.151: CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
37.151: CBFS: Locating 'fallback/ramstage'
37.151: CBFS: Found @ offset 31780 size 196fe
After that it hangs.
https://review.coreboot.org/19328/
Files
- Status changed from New to In Progress
- Assignee set to Kyösti Mälkki
From #coreboot@irc.freenode.net, kmalkki asked me to test the change below.
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index 4d5b9a8..fb53d0c 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -35,6 +35,16 @@ void backup_top_of_ram(uint64_t ramtop)
outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
+
+ u32 xdata = 0;
+ int xnvram_pos = 0xf8, xi;
+ for (xi = 0; xi < 4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ printk(BIOS_DEBUG, "%s: %08x\n", __func__, xdata);
}
unsigned long get_top_of_ram(void)
@@ -47,5 +57,7 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
+
+ printk(BIOS_DEBUG, "%s: %08x\n", __func__, xdata);
return (unsigned long) xdata;
}
For the archive, here is the compressed build directory.
The patch above should be run with CBMEM console disabled.
$ grep CONSOLE_CBMEM .config
# CONFIG_CONSOLE_CBMEM is not set
With the patch applied on top of commit 61be360 (AGESA: Fix UMA calculations), the messages below are logged on the serial console by readserial.py from SeaBIOS.
======= Sat Jul 15 08:24:30 2017 (adjust=86.8us)
00.000: <00>
01.136: <00>
03.976: <00>
05.112: <00>
07.951: <00>
10.223: <00>
11.927: <00>
13.631: <00>
15.903: <00>
17.607: <00>
19.878: <00>
22.150: <00>
23.854: <00>
25.558: <00>
27.830: <00>
30.670: <00>
31.806: <00>
31.840: <96>4<a8>H ci<a2>A<ec>C<a0>tnT<92>C<a1>Hh<d6>K<95><89><bd><bd><d1><b5><a2>r<b2>j<8a><a2><ba>j:<dd><92><8a><c2><ba>"<d9><02><9a><15><d1><81>R<d5><b1><81><8a><aa><02><82><b2><d2><82><a2><d2><8a><92><02><aa>E5
31.840: I<13>S<a6><13>$<ae><ab>k<17>W<ac>V<16><a4>.]X<b9><ba>ing...
31.840: APIC 00: CPU Family_Model = 00500f20
31.844: agesawrapper_amdinitreset() returned AGESA_SUCCESS
32.005: agesawrapper_amdinitearly() returned AGESA_SUCCESS
32.005: Normal boot
32.114: agesawrapper_amdinitpost() returned AGESA_SUCCESS
32.115: backup_top_of_ram: c8000000
32.117: Move CAR stack.
32.118: CAR disabled.
32.118: Normal boot postcar
32.118: Wiped HEAP at [10000000 - 1002ffff]
32.138: agesawrapper_amdinitenv() returned AGESA_SUCCESS
32.139: CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
32.139: CBFS: Locating 'fallback/ramstage'
32.140: CBFS: Found @ offset 31980 size 195eb
32.140: get_top_of_ram: c8000000
After that it hangs.
Here is the output with the patch applied on commit 17bb225 (AMD MTRR: Add common add_uma_resource_below_tolm()).
[…]
37.054: Fam14h - domain_set_resources
37.054: amsr - incoming dev = 00135460
37.054: adsr: (before) basek = 0, limitk = 11effffff.
37.054: adsr: (after) basek = 0, limitk = 47bfff, sizek = 47c000.
37.054: adsr - 0xa0000 to 0xbffff resource.
37.054: adsr: mmio_basek=00380000, basek=00000300, limitk=0047bfff
37.054: 0: mmio_basek=00380000, basek=00400000, limitk=0047bfff
37.054: adsr - mmio_basek = 380000.
37.054: backup_top_of_ram: c8000000
37.054: DOMAIN: 0000 assign_resources, bus 0 link: 0
37.054:
37.054: Fam14h - nb_set_resources
37.054:
37.054: Fam14h - create_vga_resource
37.054:
37.054: Fam14h - set_resource
[…]
(By the way the strange delay and messages in the beginning is due to the user option table (CMOS) and missing cmos.default for this board. That causes a baud rate of 3600 to be used.)
For the builds onward I unselected the user option table (CMOS).
$ grep OPTION_TABLE .config
# CONFIG_USE_OPTION_TABLE is not set
CONFIG_HAVE_OPTION_TABLE=y
Disabling time-stamp collection gives the same result.
$ grep COLLECT_TIMESTAMP .config
# CONFIG_COLLECT_TIMESTAMPS is not set
======= Sat Jul 15 10:55:16 2017 (adjust=86.8us)
00.000: <00>
00.512:
00.512:
00.512: coreboot-4.6-147-g72187d6 Sat Jul 15 06:04:12 UTC 2017 romstage starting...
00.513: APIC 00: CPU Family_Model = 00500f20
00.517: agesawrapper_amdinitreset() returned AGESA_SUCCESS
00.677: agesawrapper_amdinitearly() returned AGESA_SUCCESS
00.678: Normal boot
00.789: agesawrapper_amdinitpost() returned AGESA_SUCCESS
00.790: backup_top_of_ram: c8000000
00.792: Move CAR stack.
00.793: CAR disabled.
00.793: Normal boot postcar
00.793: Wiped HEAP at [10000000 - 1002ffff]
00.807: agesawrapper_amdinitenv() returned AGESA_SUCCESS
00.808: CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
00.808: CBFS: Locating 'fallback/ramstage'
00.809: CBFS: Found @ offset 316c0 size 1924b
00.809: get_top_of_ram: c8000000
Adding back the S3 check, like Aaron suggested, doesn’t hang at the same spot, but also doesn’t find the payload.
commit 7a1d9e8f977cbb82ec445a2d4f642b9bcdeb099a
Author: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Sat Jul 15 11:05:22 2017 +0200
src/southbridge/amd/cimx/sb800/ramtop.c: Add back s3 check
Change-Id: I084e1019c9fa55d0b8ae26681280860666abfec1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index 16d4e83..1584e3e 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -51,6 +51,8 @@ unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
+ if (acpi_get_sleep_type() != 3)
+ return 0;
for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
[…]
00.787: backup_top_of_ram: c8000000
[…]
00.999: CBFS: Locating 'fallback/payload'
00.999: CBFS: Found @ offset 55cc0 size 1007b
00.999: Loading segment from ROM address 0xffc55df8
00.999: code (compression=1)
00.999: New segment dstaddr 0xe1760 memsize 0x1e8a0 srcaddr 0xffc55e30 filesize 0x10043
00.999: Loading segment from ROM address 0xffc55e14
00.999: Entry Point 0x000ff06e
00.999: Payload being loaded at below 1MiB without region being marked as RAM usable.
00.999: Bounce Buffer at 00000000, 2090784 bytes
00.999: Could not find a bounce buffer...
00.999: Payload not loaded.
As suggested by kmalkki, removing select HAVE_ACPI_RESUME from the mainboards Kconfig, and with CBMEM console and time-stamp collection disabled, it boots to the payload.
Testing kmalkki’s patch below on top of latest commit 8c81c6a (google/fizz: Override PL2 and SysPL2 values) in the branch master doesn’t find the payload.
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 57ed83b..e2ed9cd 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -45,6 +45,9 @@ void set_late_cbmem_top(uintptr_t ramtop)
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
uintptr_t __attribute__((weak)) restore_cbmem_top(void)
{
+ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && !acpi_is_wakeup_s3())
+ return 0;
+
return restore_top_of_low_cacheable();
}
[…]
00.983: BS: BS_DEV_INIT times (us): entry 0 run 422883 exit 0
00.983: CBMEM:
00.983: failed.
00.983: Finalize devices...
00.983: Devices finalized
00.983: agesawrapper_amdinitlate() returned AGESA_SUCCESS
00.983: SB800: sb_Late_Post
00.984: agesawrapper_amdS3Save() returned AGESA_SUCCESS
00.984: Manufacturer: ef
00.984: SF: Detected W25Q32 with sector size 0x1000, total 0x400000
00.984: SF: Successfully erased 4096 bytes @ 0xffff1000
00.988: Manufacturer: ef
00.988: SF: Detected W25Q32 with sector size 0x1000, total 0x400000
00.988: SF: Successfully erased 4096 bytes @ 0xffff0000
00.991: BS: BS_POST_DEVICE times (us): entry 1508 run 3501 exit 40351
00.991: BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
00.991: Could not add CBMEM for coreboot table.
00.991: BS: BS_WRITE_TABLES times (us): entry 0 run 3571 exit 0
00.991: CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
00.991: CBFS: Locating 'fallback/payload'
00.991: CBFS: Found @ offset 55e80 size 1007b
00.991: Loading segment from ROM address 0xffc55fb8
00.991: code (compression=1)
00.991: New segment dstaddr 0xe1760 memsize 0x1e8a0 srcaddr 0xffc55ff0 filesize 0x10043
00.991: Loading segment from ROM address 0xffc55fd4
00.991: Entry Point 0x000ff06e
00.991: Payload being loaded at below 1MiB without region being marked as RAM usable.
00.992: Bounce Buffer at 00000000, 2361120 bytes
00.992: Could not find a bounce buffer...
00.991: Payload not loaded.
With kmalkki’s patch below on top of latest commit 8c81c6a (google/fizz: Override PL2 and SysPL2 values) in the branch master, it boots to the SeaBIOS payload.
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 57ed83b..6a353bd 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -45,6 +45,10 @@ void set_late_cbmem_top(uintptr_t ramtop)
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
uintptr_t __attribute__((weak)) restore_cbmem_top(void)
{
+ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && ENV_ROMSTAGE)
+ if (!acpi_is_wakeup_s3())
+ return 0;
+
return restore_top_of_low_cacheable();
}
Suspend and resume (ACPI S3) works too.
- Status changed from In Progress to Resolved
- % Done changed from 0 to 100
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