coreboot

The patch above should be run with CBMEM console disabled.

$ grep CONSOLE_CBMEM .config
# CONFIG_CONSOLE_CBMEM is not set

With the patch applied on top of commit 61be360 (AGESA: Fix UMA calculations), the messages below are logged on the serial console by readserial.py from SeaBIOS.

======= Sat Jul 15 08:24:30 2017 (adjust=86.8us)
00.000: <00>
01.136: <00>
03.976: <00>
05.112: <00>
07.951: <00>
10.223: <00>
11.927: <00>
13.631: <00>
15.903: <00>
17.607: <00>
19.878: <00>
22.150: <00>
23.854: <00>
25.558: <00>
27.830: <00>
30.670: <00>
31.806: <00>
31.840: <96>4<a8>H ci<a2>A<ec>C<a0>tnT<92>C<a1>Hh<d6>K<95><89><bd><bd><d1><b5><a2>r<b2>j<8a><a2><ba>j:<dd><92><8a><c2><ba>"<d9><02><9a><15><d1><81>R<d5><b1><81><8a><aa><02><82><b2><d2><82><a2><d2><8a><92><02><aa>E5
31.840: I<13>S<a6><13>$<ae><ab>k<17>W<ac>V<16><a4>.]X<b9><ba>ing...
31.840: APIC 00: CPU Family_Model = 00500f20
31.844: agesawrapper_amdinitreset() returned AGESA_SUCCESS
32.005: agesawrapper_amdinitearly() returned AGESA_SUCCESS
32.005: Normal boot
32.114: agesawrapper_amdinitpost() returned AGESA_SUCCESS
32.115: backup_top_of_ram: c8000000
32.117: Move CAR stack.
32.118: CAR disabled.
32.118: Normal boot postcar
32.118: Wiped HEAP at [10000000 - 1002ffff]
32.138: agesawrapper_amdinitenv() returned AGESA_SUCCESS
32.139: CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
32.139: CBFS: Locating 'fallback/ramstage'
32.140: CBFS: Found @ offset 31980 size 195eb
32.140: get_top_of_ram: c8000000

After that it hangs.

Here is the output with the patch applied on commit 17bb225 (AMD MTRR: Add common add_uma_resource_below_tolm()).

[…]
37.054: Fam14h - domain_set_resources
37.054:   amsr - incoming dev = 00135460
37.054: adsr: (before) basek = 0, limitk = 11effffff.
37.054: adsr: (after) basek = 0, limitk = 47bfff, sizek = 47c000.
37.054: adsr - 0xa0000 to 0xbffff resource.
37.054: adsr: mmio_basek=00380000, basek=00000300, limitk=0047bfff
37.054: 0: mmio_basek=00380000, basek=00400000, limitk=0047bfff
37.054:   adsr - mmio_basek = 380000.
37.054: backup_top_of_ram: c8000000
37.054: DOMAIN: 0000 assign_resources, bus 0 link: 0
37.054: 
37.054: Fam14h - nb_set_resources
37.054: 
37.054: Fam14h - create_vga_resource
37.054: 
37.054: Fam14h - set_resource
[…]

Adding back the S3 check, like Aaron suggested, doesn’t hang at the same spot, but also doesn’t find the payload.

commit 7a1d9e8f977cbb82ec445a2d4f642b9bcdeb099a
Author: Paul Menzel <pmenzel@molgen.mpg.de>
Date:   Sat Jul 15 11:05:22 2017 +0200

    src/southbridge/amd/cimx/sb800/ramtop.c: Add back s3 check

    Change-Id: I084e1019c9fa55d0b8ae26681280860666abfec1
    Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>

diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index 16d4e83..1584e3e 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -51,6 +51,8 @@ unsigned long get_top_of_ram(void)
 {
        u32 xdata = 0;
        int xnvram_pos = 0xf8, xi;
+       if (acpi_get_sleep_type() != 3)
+               return 0;
        for (xi = 0; xi < 4; xi++) {
                outb(xnvram_pos, BIOSRAM_INDEX);
                xdata &= ~(0xff << (xi * 8));

[…]
00.787: backup_top_of_ram: c8000000
[…]
00.999: CBFS: Locating 'fallback/payload'
00.999: CBFS: Found @ offset 55cc0 size 1007b
00.999: Loading segment from ROM address 0xffc55df8
00.999:   code (compression=1)
00.999:   New segment dstaddr 0xe1760 memsize 0x1e8a0 srcaddr 0xffc55e30 filesize 0x10043
00.999: Loading segment from ROM address 0xffc55e14
00.999:   Entry Point 0x000ff06e
00.999: Payload being loaded at below 1MiB without region being marked as RAM usable.
00.999: Bounce Buffer at 00000000, 2090784 bytes
00.999: Could not find a bounce buffer...
00.999: Payload not loaded.

Testing kmalkki’s patch below on top of latest commit 8c81c6a (google/fizz: Override PL2 and SysPL2 values) in the branch master doesn’t find the payload.

diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 57ed83b..e2ed9cd 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -45,6 +45,9 @@ void set_late_cbmem_top(uintptr_t ramtop)
 /* Top of CBMEM is at highest usable DRAM address below 4GiB. */
 uintptr_t __attribute__((weak)) restore_cbmem_top(void)
 {
+       if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && !acpi_is_wakeup_s3())
+               return 0;
+
        return restore_top_of_low_cacheable();
 }

[…]
00.983: BS: BS_DEV_INIT times (us): entry 0 run 422883 exit 0
00.983: CBMEM:
00.983: failed.
00.983: Finalize devices...
00.983: Devices finalized
00.983: agesawrapper_amdinitlate() returned AGESA_SUCCESS
00.983: SB800: sb_Late_Post
00.984: agesawrapper_amdS3Save() returned AGESA_SUCCESS
00.984: Manufacturer: ef
00.984: SF: Detected W25Q32 with sector size 0x1000, total 0x400000
00.984: SF: Successfully erased 4096 bytes @ 0xffff1000
00.988: Manufacturer: ef
00.988: SF: Detected W25Q32 with sector size 0x1000, total 0x400000
00.988: SF: Successfully erased 4096 bytes @ 0xffff0000
00.991: BS: BS_POST_DEVICE times (us): entry 1508 run 3501 exit 40351
00.991: BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
00.991: Could not add CBMEM for coreboot table.
00.991: BS: BS_WRITE_TABLES times (us): entry 0 run 3571 exit 0
00.991: CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
00.991: CBFS: Locating 'fallback/payload'
00.991: CBFS: Found @ offset 55e80 size 1007b
00.991: Loading segment from ROM address 0xffc55fb8
00.991:   code (compression=1)
00.991:   New segment dstaddr 0xe1760 memsize 0x1e8a0 srcaddr 0xffc55ff0 filesize 0x10043
00.991: Loading segment from ROM address 0xffc55fd4
00.991:   Entry Point 0x000ff06e
00.991: Payload being loaded at below 1MiB without region being marked as RAM usable.
00.992: Bounce Buffer at 00000000, 2361120 bytes
00.992: Could not find a bounce buffer...
00.991: Payload not loaded.

With kmalkki’s patch below on top of latest commit 8c81c6a (google/fizz: Override PL2 and SysPL2 values) in the branch master, it boots to the SeaBIOS payload.

diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 57ed83b..6a353bd 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -45,6 +45,10 @@ void set_late_cbmem_top(uintptr_t ramtop)
 /* Top of CBMEM is at highest usable DRAM address below 4GiB. */
 uintptr_t __attribute__((weak)) restore_cbmem_top(void)
 {
+       if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && ENV_ROMSTAGE)
+               if (!acpi_is_wakeup_s3())
+                       return 0;
+
        return restore_top_of_low_cacheable();
 }

Fixed: https://review.coreboot.org/c/20590/

b6a0fe5 AGESA boards: Fix regressions with LATE_CBMEM_INIT