Project

General

Profile

Actions

Feature #583

open

Allow reconfiguring PCIe slots on Asus P8Z77-V

Added by Keith Hui about 1 month ago. Updated 2 days ago.

Status:
New
Priority:
Normal
Assignee:
Category:
board support
Target version:
Start date:
11/30/2024
Due date:
% Done:

90%

Estimated time:
15.00 h
Affected versions:
Needs backport to:
Affected hardware:
mb/asus/p8z77-v
Affected OS:

Description

Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled):

  • X4: PCIEX16_3 as x4
  • X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2
  • Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061

The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:

  1. Despite our best efforts, PCIEX1_2 still doesn't work.
  2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.

This issue tracks our progress implementing this feature.


Files

autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) autoport-p8z77v-gb83fac3e1c74-dirty.tgz Bill XIE, 03/28/2025 05:01 AM
cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) cbmem-0-2-7-noPCIEX1_2.log Bill XIE, 03/28/2025 06:01 AM
p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77-v-pcielane-gpio-probe-map.png Keith Hui, 03/30/2025 01:36 AM
p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02.png Bill XIE, 03/31/2025 07:29 AM
p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-r1.02-where-to-probe.png Keith Hui, 03/31/2025 11:02 AM
p8z77v-ifd.bin (4 KB) p8z77v-ifd.bin Bill XIE, 04/17/2025 02:35 AM
p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog.log Bill XIE, 04/17/2025 02:35 AM
p8z77v-ifdprog-rdev.log (446 KB) p8z77v-ifdprog-rdev.log Bill XIE, 04/17/2025 07:10 AM
p8z77v-loop.log (167 KB) p8z77v-loop.log Bill XIE, 04/17/2025 09:23 AM
dump-me-status.diff (1.01 KB) dump-me-status.diff Bill XIE, 04/17/2025 09:52 AM
Actions #4

Updated by Bill XIE 19 days ago

Actions #5

Updated by Keith Hui 19 days ago

Attached gimped photo shows where to probe instead. The numbers are for X_QSW_SEL[#].

Actions #6

Updated by Keith Hui 9 days ago

  • % Done changed from 0 to 90
  • Estimated time set to 15.00 h
  • Affected versions main added
Actions #7

Updated by Keith Hui 9 days ago

IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.

Updated by Bill XIE 2 days ago

Keith Hui wrote in #note-7:

IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.

Actions #9

Updated by Bill XIE 2 days ago

Bill XIE wrote in #note-8:

Keith Hui wrote in #note-7:

IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.

Actions #10

Updated by Bill XIE 2 days ago

Actions #11

Updated by Bill XIE 2 days ago

Dump ME status:

Actions

Also available in: Atom PDF