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Feature #583

open

Allow reconfiguring PCIe slots on Asus P8Z77-V

Added by Keith Hui about 2 months ago. Updated 18 days ago.

Status:
New
Priority:
Normal
Assignee:
Keith Hui
Category:
board support
Target version:
none
Start date:
11/30/2024
Due date:
% Done:

90%

Estimated time:
15.00 h
Affected versions:
main
Needs backport to:
Affected hardware:
mb/asus/p8z77-v
Affected OS:

Description

Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled):

  • X4: PCIEX16_3 as x4
  • X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2
  • Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061

The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:

  1. Despite our best efforts, PCIEX1_2 still doesn't work.
  2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.

This issue tracks our progress implementing this feature.

Files

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autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) autoport-p8z77v-gb83fac3e1c74-dirty.tgz Bill XIE, 03/28/2025 05:01 AM
cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) cbmem-0-2-7-noPCIEX1_2.log Bill XIE, 03/28/2025 06:01 AM
p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77-v-pcielane-gpio-probe-map.png Keith Hui, 03/30/2025 01:36 AM
p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02.png Bill XIE, 03/31/2025 07:29 AM
p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-r1.02-where-to-probe.png Keith Hui, 03/31/2025 11:02 AM
p8z77v-ifd.bin (4 KB) p8z77v-ifd.bin Bill XIE, 04/17/2025 02:35 AM
p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog.log Bill XIE, 04/17/2025 02:35 AM
p8z77v-ifdprog-rdev.log (446 KB) p8z77v-ifdprog-rdev.log Bill XIE, 04/17/2025 07:10 AM
p8z77v-loop.log (167 KB) p8z77v-loop.log Bill XIE, 04/17/2025 09:23 AM
dump-me-status.diff (1.01 KB) dump-me-status.diff Bill XIE, 04/17/2025 09:52 AM
87334-ifd-updated.log (64 KB) 87334-ifd-updated.log Keith Hui, 04/20/2025 01:06 AM
inteltool.pciex4.log (1.58 KB) inteltool.pciex4.log Keith Hui, 04/20/2025 02:29 AM
inteltool.pciex2.log (1.58 KB) inteltool.pciex2.log Keith Hui, 04/20/2025 02:29 AM
p8z77v-leplus.pcie2x.nonvme.log (57.5 KB) p8z77v-leplus.pcie2x.nonvme.log Keith Hui, 04/20/2025 02:29 AM
p8z77v-leplus.pcie2x.nvme.log (65.3 KB) p8z77v-leplus.pcie2x.nvme.log Keith Hui, 04/20/2025 02:29 AM
p8z77v-leplus.pcie4x.nonvme.log (57.7 KB) p8z77v-leplus.pcie4x.nonvme.log Keith Hui, 04/20/2025 02:29 AM
p8z77v-leplus.pcie4x.nvme.log (59.3 KB) p8z77v-leplus.pcie4x.nvme.log Keith Hui, 04/20/2025 02:29 AM
gma-pid.diff (601 Bytes) gma-pid.diff Bill XIE, 04/22/2025 01:50 AM
p8z77v-ifdprog-me.log (194 KB) p8z77v-ifdprog-me.log Bill XIE, 04/22/2025 01:51 AM
p8z77v-goodme-2to4.log (320 KB) p8z77v-goodme-2to4.log Bill XIE, 04/22/2025 02:44 AM

Related links

https://review.coreboot.org/c/coreboot/+/85413

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 #5

Updated by Keith Hui about 1 month ago

Attached gimped photo shows where to probe instead. The numbers are for X_QSW_SEL[#].

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 #6

Updated by Keith Hui 29 days ago

  • % Done changed from 0 to 90
  • Estimated time set to 15.00 h
  • Affected versions main added
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 #7

Updated by Keith Hui 29 days ago

IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.

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 #8

Updated by Bill XIE 23 days ago

Keith Hui wrote in #note-7:

IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.

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 #9

Updated by Bill XIE 22 days ago

Bill XIE wrote in #note-8:

Keith Hui wrote in #note-7:

IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.

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 #10

Updated by Bill XIE 22 days ago

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 #11

Updated by Bill XIE 22 days ago

Dump ME status:

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 #12

Updated by Keith Hui 20 days ago

Boot log of a successful update on p8z77-v_le_plus, being developed under CB:87334.

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 #14

Updated by Bill XIE 18 days ago

IFD programming works under intact ME, but IGD gets disabled with PCI PID becoming 0xffff, observed via the attached patch.

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 #15

Updated by Bill XIE 18 days ago

With the other ME image obtained directly from the board, IGD is not disabled, and everything seems to work fine.

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