|
|
|
|
|
[NOTE ] coreboot-25.03-250-g59e4095ecfcb-dirty Mon Apr 21 05:10:24 UTC 2025 x86_32 bootblock starting (log level: 8)...
|
|
[INFO ] Timestamp - end of bootblock: 277129459
|
|
[INFO ] Timestamp - start of romstage: 291600901
|
|
[DEBUG] SMBus controller enabled
|
|
[INFO ] Detected system type: desktop
|
|
[DEBUG] Setting up static northbridge registers... done
|
|
[DEBUG] Graphics ffff not supported by this CPU/chipset.
|
|
[DEBUG] Initializing Graphics...
|
|
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='cmos_layout.bin', alloc=0x00000000(0x00000000), force_ro=true, type=-1)
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x210000.
|
|
[DEBUG] FMAP: base = 0x0 size = 0x800000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ 210200 (6225408 bytes)
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x0...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x2c, length 0x20)
|
|
[SPEW ] CBFS DEBUG: File name: 'cbfs_master_header'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x4c...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x80 (type 83, attr +0x0, data +0x30, length 0x6800)
|
|
[SPEW ] CBFS DEBUG: File name: 'cpu_microcode_blob.bin'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x68b0...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x68c0 (type 17, attr +0x2c, data +0x54, length 0x1fe6e)
|
|
[SPEW ] CBFS DEBUG: File name: 'fallback/ramstage'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x26782...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x267c0 (type 80, attr +0x0, data +0x30, length 0x7200)
|
|
[SPEW ] CBFS DEBUG: File name: 'vgaroms/seavgabios.bin'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x2d9f0...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x2da00 (type 80, attr +0x20, data +0x30, length 0xe80)
|
|
[SPEW ] CBFS DEBUG: File name: 'config'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x2e8b0...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x2e8c0 (type 80, attr +0x0, data +0x24, length 0x2d7)
|
|
[SPEW ] CBFS DEBUG: File name: 'revision'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x2ebbb...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x2ebc0 (type 80, attr +0x0, data +0x24, length 0x60)
|
|
[SPEW ] CBFS DEBUG: File name: 'build_info'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x2ec44...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x2ec80 (type 80, attr +0x0, data +0x2c, length 0x2332)
|
|
[SPEW ] CBFS DEBUG: File name: 'fallback/dsdt.aml'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x30fde...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x31000 (type 80, attr +0x20, data +0x30, length 0x4e1)
|
|
[SPEW ] CBFS DEBUG: File name: 'vbt.bin'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x31511...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x31540 (type 170, attr +0x0, data +0x28, length 0x100)
|
|
[SPEW ] CBFS DEBUG: File name: 'cmos.default'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x31668...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x31680 (type 426, attr +0x0, data +0x28, length 0x5ac)
|
|
[SPEW ] CBFS DEBUG: File name: 'cmos_layout.bin'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x31c54...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x31c80 (type 17, attr +0x2c, data +0x44, length 0x81a8)
|
|
[SPEW ] CBFS DEBUG: File name: 'fallback/postcar'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x39e6c...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x39e80 (type 32, attr +0x0, data +0x28, length 0xa9f0)
|
|
[SPEW ] CBFS DEBUG: File name: 'img/coreinfo'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x44898...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x448c0 (type 32, attr +0x0, data +0x28, length 0xc6eb)
|
|
[SPEW ] CBFS DEBUG: File name: 'img/nvramcui'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x50fd3...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x51000 (type 32, attr +0x0, data +0x2c, length 0x11c61)
|
|
[SPEW ] CBFS DEBUG: File name: 'fallback/payload'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x62c8d...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x62cc0 (type 80, attr +0x0, data +0x28, length 0x6ae)
|
|
[SPEW ] CBFS DEBUG: File name: 'payload_config'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x63396...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x633c0 (type 80, attr +0x0, data +0x2c, length 0xee)
|
|
[SPEW ] CBFS DEBUG: File name: 'payload_revision'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x634da...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x63500 (type 80, attr +0x0, data +0x28, length 0x6e2)
|
|
[SPEW ] CBFS DEBUG: File name: 'etc/grub.cfg'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x63c0a...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x63c40 (type 32, attr +0x0, data +0x24, length 0x80c95)
|
|
[SPEW ] CBFS DEBUG: File name: 'img/grub2'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0xe48f9...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0xe4900 (type 80, attr +0x0, data +0x28, length 0x8)
|
|
[SPEW ] CBFS DEBUG: File name: 'etc/sercon-port'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0xe4930...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0xe4940 (type -1, attr +0x0, data +0x1c, length 0x4f1464)
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x5d5dc0...
|
|
[SPEW ] CBFS DEBUG: Found CBFS header @0x5d5dc0 (type 1, attr +0x0, data +0x40, length 0x1a000)
|
|
[SPEW ] CBFS DEBUG: File name: 'bootblock'
|
|
[SPEW ] CBFS DEBUG: Looking for next file @0x5efe00...
|
|
[SPEW ] CBFS DEBUG: End of CBFS reached
|
|
[INFO ] CBFS: mcache @0xfeff0e00 built for 21 files, used 0x3d0 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'cmos_layout.bin' @0x31680 size 0x5ac in mcache @0xfeff0fdc
|
|
[DEBUG] Back from systemagent_early_init()
|
|
[INFO ] POST: 0x38
|
|
[INFO ] POST: 0x39
|
|
[INFO ] POST: 0x3a
|
|
[INFO ] Timestamp - before RAM initialization: 1796638646
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Requested 16MB UMA
|
|
[DEBUG] Starting native Platform init
|
|
[DEBUG] DMI: Running at X4 @ 5000MT/s
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] ECC supported: no ECC forced: no
|
|
[INFO ] ECC RAM unsupported.
|
|
[DEBUG] SPD probe channel0, slot0
|
|
[DEBUG] Not a DDR3 SPD!
|
|
[DEBUG] No valid XMP profile found.
|
|
[DEBUG] Not a DDR3 SPD!
|
|
[DEBUG] SPD probe channel0, slot1
|
|
[DEBUG] Revision : 11
|
|
[DEBUG] Type : b
|
|
[DEBUG] Key : 2
|
|
[DEBUG] Banks : 8
|
|
[DEBUG] Capacity : 4 Gb
|
|
[DEBUG] Supported voltages : 1.35V 1.5V
|
|
[DEBUG] SDRAM width : 8
|
|
[DEBUG] Bus extension : 0 bits
|
|
[DEBUG] Bus width : 64
|
|
[DEBUG] FTB timings : yes
|
|
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
|
|
[DEBUG] Thermal features : PASR ext_temp_range
|
|
[DEBUG] Thermal sensor : no
|
|
[DEBUG] Standard SDRAM : yes
|
|
[DEBUG] Rank1 Address bits : mirrored
|
|
[DEBUG] DIMM Reference card: H
|
|
[DEBUG] Manufacturer ID : 9801
|
|
[DEBUG] Part number : 99U5471-050.A00L
|
|
[DEBUG] Not a DDR3 XMP profile!
|
|
[DEBUG] No valid XMP profile found.
|
|
[DEBUG] Revision : 11
|
|
[DEBUG] Type : b
|
|
[DEBUG] Key : 2
|
|
[DEBUG] Banks : 8
|
|
[DEBUG] Capacity : 4 Gb
|
|
[DEBUG] Supported voltages : 1.35V 1.5V
|
|
[DEBUG] SDRAM width : 8
|
|
[DEBUG] Bus extension : 0 bits
|
|
[DEBUG] Bus width : 64
|
|
[DEBUG] FTB timings : yes
|
|
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
|
|
[DEBUG] Thermal features : PASR ext_temp_range
|
|
[DEBUG] Thermal sensor : no
|
|
[DEBUG] Standard SDRAM : yes
|
|
[DEBUG] Rank1 Address bits : mirrored
|
|
[DEBUG] DIMM Reference card: H
|
|
[DEBUG] Manufacturer ID : 9801
|
|
[DEBUG] Part number : 99U5471-050.A00L
|
|
[INFO ] Row addr bits : 16
|
|
[INFO ] Column addr bits : 10
|
|
[INFO ] Number of ranks : 2
|
|
[INFO ] DIMM Capacity : 8192 MB
|
|
[INFO ] CAS latencies : 6 7 8 9 10 11
|
|
[INFO ] tCKmin : 1.250 ns
|
|
[INFO ] tAAmin : 13.125 ns
|
|
[INFO ] tWRmin : 15.000 ns
|
|
[INFO ] tRCDmin : 13.125 ns
|
|
[INFO ] tRRDmin : 6.000 ns
|
|
[INFO ] tRPmin : 13.125 ns
|
|
[INFO ] tRASmin : 35.000 ns
|
|
[INFO ] tRCmin : 48.125 ns
|
|
[INFO ] tRFCmin : 260.000 ns
|
|
[INFO ] tWTRmin : 7.500 ns
|
|
[INFO ] tRTPmin : 7.500 ns
|
|
[INFO ] tFAWmin : 30.000 ns
|
|
[DEBUG] channel[0] rankmap = 0xc
|
|
[DEBUG] SPD probe channel1, slot0
|
|
[DEBUG] Not a DDR3 SPD!
|
|
[DEBUG] No valid XMP profile found.
|
|
[DEBUG] Not a DDR3 SPD!
|
|
[DEBUG] SPD probe channel1, slot1
|
|
[DEBUG] Revision : 11
|
|
[DEBUG] Type : b
|
|
[DEBUG] Key : 2
|
|
[DEBUG] Banks : 8
|
|
[DEBUG] Capacity : 4 Gb
|
|
[DEBUG] Supported voltages : 1.35V 1.5V
|
|
[DEBUG] SDRAM width : 8
|
|
[DEBUG] Bus extension : 0 bits
|
|
[DEBUG] Bus width : 64
|
|
[DEBUG] FTB timings : yes
|
|
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
|
|
[DEBUG] Thermal features : PASR ext_temp_range
|
|
[DEBUG] Thermal sensor : no
|
|
[DEBUG] Standard SDRAM : yes
|
|
[DEBUG] Rank1 Address bits : mirrored
|
|
[DEBUG] DIMM Reference card: H
|
|
[DEBUG] Manufacturer ID : 9801
|
|
[DEBUG] Part number : 99U5471-050.A00L
|
|
[DEBUG] Not a DDR3 XMP profile!
|
|
[DEBUG] No valid XMP profile found.
|
|
[DEBUG] Revision : 11
|
|
[DEBUG] Type : b
|
|
[DEBUG] Key : 2
|
|
[DEBUG] Banks : 8
|
|
[DEBUG] Capacity : 4 Gb
|
|
[DEBUG] Supported voltages : 1.35V 1.5V
|
|
[DEBUG] SDRAM width : 8
|
|
[DEBUG] Bus extension : 0 bits
|
|
[DEBUG] Bus width : 64
|
|
[DEBUG] FTB timings : yes
|
|
[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6
|
|
[DEBUG] Thermal features : PASR ext_temp_range
|
|
[DEBUG] Thermal sensor : no
|
|
[DEBUG] Standard SDRAM : yes
|
|
[DEBUG] Rank1 Address bits : mirrored
|
|
[DEBUG] DIMM Reference card: H
|
|
[DEBUG] Manufacturer ID : 9801
|
|
[DEBUG] Part number : 99U5471-050.A00L
|
|
[INFO ] Row addr bits : 16
|
|
[INFO ] Column addr bits : 10
|
|
[INFO ] Number of ranks : 2
|
|
[INFO ] DIMM Capacity : 8192 MB
|
|
[INFO ] CAS latencies : 6 7 8 9 10 11
|
|
[INFO ] tCKmin : 1.250 ns
|
|
[INFO ] tAAmin : 13.125 ns
|
|
[INFO ] tWRmin : 15.000 ns
|
|
[INFO ] tRCDmin : 13.125 ns
|
|
[INFO ] tRRDmin : 6.000 ns
|
|
[INFO ] tRPmin : 13.125 ns
|
|
[INFO ] tRASmin : 35.000 ns
|
|
[INFO ] tRCmin : 48.125 ns
|
|
[INFO ] tRFCmin : 260.000 ns
|
|
[INFO ] tWTRmin : 7.500 ns
|
|
[INFO ] tRTPmin : 7.500 ns
|
|
[INFO ] tFAWmin : 30.000 ns
|
|
[DEBUG] channel[1] rankmap = 0xc
|
|
[DEBUG] ECC is disabled
|
|
[DEBUG] Starting Ivy Bridge RAM training (full initialization).
|
|
[DEBUG] 100MHz reference clock support: yes
|
|
[DEBUG] PLL_REF100_CFG value: 0x2
|
|
[DEBUG] Trying CAS 11, tCK 320.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 800 MHz
|
|
[DEBUG] Selected CAS latency : 11T
|
|
[DEBUG] MPLL busy... done in 10 us
|
|
[DEBUG] MPLL frequency is set at : 800 MHz
|
|
[DEBUG] Selected CWL latency : 8T
|
|
[DEBUG] Selected tRCD : 11T
|
|
[DEBUG] Selected tRP : 11T
|
|
[DEBUG] Selected tRAS : 28T
|
|
[DEBUG] Selected tWR : 12T
|
|
[DEBUG] Selected tFAW : 24T
|
|
[DEBUG] Selected tRRD : 5T
|
|
[DEBUG] Selected tRTP : 6T
|
|
[DEBUG] Selected tWTR : 6T
|
|
[DEBUG] Selected tRFC : 208T
|
|
[DEBUG] XOVER CLK [c14] = c000000
|
|
[DEBUG] XOVER CMD [320c] = 4004000
|
|
[DEBUG] XOVER CLK [d14] = c000000
|
|
[DEBUG] XOVER CMD [330c] = 4004000
|
|
[DEBUG] DBP [4000] = 1c8bbb
|
|
[DEBUG] RAP [4004] = cc186465
|
|
[DEBUG] OTHP [400c] = 58b4
|
|
[DEBUG] OTHP [400c] = 58b4
|
|
[DEBUG] REFI [4298] = 6cd01860
|
|
[DEBUG] SRFTP [42a4] = 41f88200
|
|
[DEBUG] DBP [4400] = 1c8bbb
|
|
[DEBUG] RAP [4404] = cc186465
|
|
[DEBUG] OTHP [440c] = 58b4
|
|
[DEBUG] OTHP [440c] = 58b4
|
|
[DEBUG] REFI [4698] = 6cd01860
|
|
[DEBUG] SRFTP [46a4] = 41f88200
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 4
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 84a00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 7a600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 4
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] PCI(0, 0, 0)[7c] = 7f
|
|
[DEBUG] PCI(0, 0, 0)[70] = ff000000
|
|
[DEBUG] PCI(0, 0, 0)[74] = 3
|
|
[DEBUG] PCI(0, 0, 0)[78] = ff000c00
|
|
[DEBUG] Done memory map
|
|
[DEBUG] RCOMP...done
|
|
[DEBUG] COMP2 done
|
|
[DEBUG] COMP1 done
|
|
[DEBUG] FORCE RCOMP and wait 20us...done
|
|
[DEBUG] Done io registers
|
|
[DEBUG] Done jedec reset
|
|
[DEBUG] Done MRS commands
|
|
[DEBUG] rcven: 0, 2, 0: 9- 38- 68
|
|
[DEBUG] rcven: 0, 2, 1: 24- 53- 83
|
|
[DEBUG] rcven: 0, 2, 2: 44- 75- 106
|
|
[DEBUG] rcven: 0, 2, 3: 59- 90- 121
|
|
[DEBUG] rcven: 0, 2, 4: 92- 121- 23
|
|
[DEBUG] rcven: 0, 2, 5: 107- 7- 36
|
|
[DEBUG] rcven: 0, 2, 6: 0- 26- 53
|
|
[DEBUG] rcven: 0, 2, 7: 16- 46- 76
|
|
[DEBUG] 4024++;
|
|
[DEBUG] 4028++;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4028 += 2;
|
|
[DEBUG] increment 0, 2, 5
|
|
[DEBUG] increment 0, 2, 6
|
|
[DEBUG] increment 0, 2, 7
|
|
[DEBUG] 4024 += 1;
|
|
[DEBUG] 4028 += 1;
|
|
[DEBUG] lane 0: -3, 8
|
|
[DEBUG] Aval: 0, 2, 0: 70
|
|
[DEBUG] lane 1: -7, 4
|
|
[DEBUG] Aval: 0, 2, 1: 82
|
|
[DEBUG] lane 2: -4, 5
|
|
[DEBUG] Aval: 0, 2, 2: 106
|
|
[DEBUG] lane 3: -3, 5
|
|
[DEBUG] Aval: 0, 2, 3: 122
|
|
[DEBUG] lane 4: -5, 4
|
|
[DEBUG] Aval: 0, 2, 4: 151
|
|
[DEBUG] lane 5: -3, 7
|
|
[DEBUG] Aval: 0, 2, 5: 166
|
|
[DEBUG] lane 6: -1, 11
|
|
[DEBUG] Aval: 0, 2, 6: 186
|
|
[DEBUG] lane 7: -2, 7
|
|
[DEBUG] Aval: 0, 2, 7: 206
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4028 -= 1;
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4/8: 0, 2, 49, 7
|
|
[DEBUG] final results:
|
|
[DEBUG] Aval: 0, 2, 0: 6
|
|
[DEBUG] Aval: 0, 2, 1: 18
|
|
[DEBUG] Aval: 0, 2, 2: 42
|
|
[DEBUG] Aval: 0, 2, 3: 58
|
|
[DEBUG] Aval: 0, 2, 4: 87
|
|
[DEBUG] Aval: 0, 2, 5: 102
|
|
[DEBUG] Aval: 0, 2, 6: 122
|
|
[DEBUG] Aval: 0, 2, 7: 142
|
|
[DEBUG] rcven: 0, 3, 0: 8- 39- 71
|
|
[DEBUG] rcven: 0, 3, 1: 23- 54- 85
|
|
[DEBUG] rcven: 0, 3, 2: 46- 76- 107
|
|
[DEBUG] rcven: 0, 3, 3: 61- 91- 122
|
|
[DEBUG] rcven: 0, 3, 4: 91- 120- 22
|
|
[DEBUG] rcven: 0, 3, 5: 108- 11- 43
|
|
[DEBUG] rcven: 0, 3, 6: 126- 28- 58
|
|
[DEBUG] rcven: 0, 3, 7: 18- 47- 77
|
|
[DEBUG] 4024++;
|
|
[DEBUG] 4028++;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4028 += 2;
|
|
[DEBUG] increment 0, 3, 5
|
|
[DEBUG] increment 0, 3, 6
|
|
[DEBUG] increment 0, 3, 7
|
|
[DEBUG] 4024 += 1;
|
|
[DEBUG] 4028 += 1;
|
|
[DEBUG] lane 0: -5, 4
|
|
[DEBUG] Aval: 0, 3, 0: 71
|
|
[DEBUG] lane 1: -5, 4
|
|
[DEBUG] Aval: 0, 3, 1: 85
|
|
[DEBUG] lane 2: -4, 5
|
|
[DEBUG] Aval: 0, 3, 2: 107
|
|
[DEBUG] lane 3: -3, 5
|
|
[DEBUG] Aval: 0, 3, 3: 123
|
|
[DEBUG] lane 4: -3, 6
|
|
[DEBUG] Aval: 0, 3, 4: 151
|
|
[DEBUG] lane 5: -5, 5
|
|
[DEBUG] Aval: 0, 3, 5: 171
|
|
[DEBUG] lane 6: -2, 7
|
|
[DEBUG] Aval: 0, 3, 6: 188
|
|
[DEBUG] lane 7: -2, 9
|
|
[DEBUG] Aval: 0, 3, 7: 208
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4028 -= 1;
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4/8: 0, 3, 49, 7
|
|
[DEBUG] final results:
|
|
[DEBUG] Aval: 0, 3, 0: 7
|
|
[DEBUG] Aval: 0, 3, 1: 21
|
|
[DEBUG] Aval: 0, 3, 2: 43
|
|
[DEBUG] Aval: 0, 3, 3: 59
|
|
[DEBUG] Aval: 0, 3, 4: 87
|
|
[DEBUG] Aval: 0, 3, 5: 107
|
|
[DEBUG] Aval: 0, 3, 6: 124
|
|
[DEBUG] Aval: 0, 3, 7: 144
|
|
[DEBUG] rcven: 1, 2, 0: 47- 75- 104
|
|
[DEBUG] rcven: 1, 2, 1: 61- 91- 121
|
|
[DEBUG] rcven: 1, 2, 2: 84- 116- 20
|
|
[DEBUG] rcven: 1, 2, 3: 96- 127- 31
|
|
[DEBUG] rcven: 1, 2, 4: 1- 33- 66
|
|
[DEBUG] rcven: 1, 2, 5: 18- 49- 81
|
|
[DEBUG] rcven: 1, 2, 6: 36- 68- 100
|
|
[DEBUG] rcven: 1, 2, 7: 52- 84- 116
|
|
[DEBUG] 4024++;
|
|
[DEBUG] 4028++;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4028 += 2;
|
|
[DEBUG] increment 1, 2, 4
|
|
[DEBUG] increment 1, 2, 5
|
|
[DEBUG] increment 1, 2, 6
|
|
[DEBUG] increment 1, 2, 7
|
|
[DEBUG] 4024 += 1;
|
|
[DEBUG] 4028 += 1;
|
|
[DEBUG] lane 0: -2, 9
|
|
[DEBUG] Aval: 1, 2, 0: 107
|
|
[DEBUG] lane 1: -2, 6
|
|
[DEBUG] Aval: 1, 2, 1: 123
|
|
[DEBUG] lane 2: -8, 1
|
|
[DEBUG] Aval: 1, 2, 2: 145
|
|
[DEBUG] lane 3: -5, 4
|
|
[DEBUG] Aval: 1, 2, 3: 159
|
|
[DEBUG] lane 4: -9, 1
|
|
[DEBUG] Aval: 1, 2, 4: 190
|
|
[DEBUG] lane 5: -9, 1
|
|
[DEBUG] Aval: 1, 2, 5: 205
|
|
[DEBUG] lane 6: -6, 4
|
|
[DEBUG] Aval: 1, 2, 6: 227
|
|
[DEBUG] lane 7: -6, 4
|
|
[DEBUG] Aval: 1, 2, 7: 243
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4028 -= 1;
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4/8: 1, 2, 49, 7
|
|
[DEBUG] final results:
|
|
[DEBUG] Aval: 1, 2, 0: 43
|
|
[DEBUG] Aval: 1, 2, 1: 59
|
|
[DEBUG] Aval: 1, 2, 2: 81
|
|
[DEBUG] Aval: 1, 2, 3: 95
|
|
[DEBUG] Aval: 1, 2, 4: 126
|
|
[DEBUG] Aval: 1, 2, 5: 141
|
|
[DEBUG] Aval: 1, 2, 6: 163
|
|
[DEBUG] Aval: 1, 2, 7: 179
|
|
[DEBUG] rcven: 1, 3, 0: 44- 76- 109
|
|
[DEBUG] rcven: 1, 3, 1: 65- 95- 126
|
|
[DEBUG] rcven: 1, 3, 2: 84- 114- 17
|
|
[DEBUG] rcven: 1, 3, 3: 100- 1- 31
|
|
[DEBUG] rcven: 1, 3, 4: 4- 35- 66
|
|
[DEBUG] rcven: 1, 3, 5: 16- 47- 79
|
|
[DEBUG] rcven: 1, 3, 6: 42- 72- 102
|
|
[DEBUG] rcven: 1, 3, 7: 54- 84- 114
|
|
[DEBUG] 4024++;
|
|
[DEBUG] 4028++;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4024 -= 2;
|
|
[DEBUG] 4028 += 2;
|
|
[DEBUG] increment 1, 3, 3
|
|
[DEBUG] increment 1, 3, 4
|
|
[DEBUG] increment 1, 3, 5
|
|
[DEBUG] increment 1, 3, 6
|
|
[DEBUG] increment 1, 3, 7
|
|
[DEBUG] 4024 += 1;
|
|
[DEBUG] 4028 += 1;
|
|
[DEBUG] lane 0: -7, 4
|
|
[DEBUG] Aval: 1, 3, 0: 108
|
|
[DEBUG] lane 1: -7, 3
|
|
[DEBUG] Aval: 1, 3, 1: 124
|
|
[DEBUG] lane 2: -7, 4
|
|
[DEBUG] Aval: 1, 3, 2: 144
|
|
[DEBUG] lane 3: -4, 5
|
|
[DEBUG] Aval: 1, 3, 3: 159
|
|
[DEBUG] lane 4: -6, 5
|
|
[DEBUG] Aval: 1, 3, 4: 194
|
|
[DEBUG] lane 5: -7, 4
|
|
[DEBUG] Aval: 1, 3, 5: 206
|
|
[DEBUG] lane 6: -4, 6
|
|
[DEBUG] Aval: 1, 3, 6: 231
|
|
[DEBUG] lane 7: -7, 5
|
|
[DEBUG] Aval: 1, 3, 7: 241
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4028 -= 1;
|
|
[DEBUG] 4024 += 0;
|
|
[DEBUG] 4028 += 0;
|
|
[DEBUG] 4/8: 1, 3, 49, 7
|
|
[DEBUG] final results:
|
|
[DEBUG] Aval: 1, 3, 0: 44
|
|
[DEBUG] Aval: 1, 3, 1: 60
|
|
[DEBUG] Aval: 1, 3, 2: 80
|
|
[DEBUG] Aval: 1, 3, 3: 95
|
|
[DEBUG] Aval: 1, 3, 4: 130
|
|
[DEBUG] Aval: 1, 3, 5: 142
|
|
[DEBUG] Aval: 1, 3, 6: 167
|
|
[DEBUG] Aval: 1, 3, 7: 177
|
|
[DEBUG] discover falling edges:
|
|
[DEBUG] [4eb0] = 300
|
|
[DEBUG] eval 0, 2, 0: 42
|
|
[DEBUG] eval 0, 2, 1: 39
|
|
[DEBUG] eval 0, 2, 2: 41
|
|
[DEBUG] eval 0, 2, 3: 41
|
|
[DEBUG] eval 0, 2, 4: 39
|
|
[DEBUG] eval 0, 2, 5: 40
|
|
[DEBUG] eval 0, 2, 6: 39
|
|
[DEBUG] eval 0, 2, 7: 41
|
|
[DEBUG] eval 0, 3, 0: 41
|
|
[DEBUG] eval 0, 3, 1: 40
|
|
[DEBUG] eval 0, 3, 2: 41
|
|
[DEBUG] eval 0, 3, 3: 40
|
|
[DEBUG] eval 0, 3, 4: 40
|
|
[DEBUG] eval 0, 3, 5: 39
|
|
[DEBUG] eval 0, 3, 6: 40
|
|
[DEBUG] eval 0, 3, 7: 41
|
|
[DEBUG] eval 1, 2, 0: 43
|
|
[DEBUG] eval 1, 2, 1: 43
|
|
[DEBUG] eval 1, 2, 2: 43
|
|
[DEBUG] eval 1, 2, 3: 43
|
|
[DEBUG] eval 1, 2, 4: 41
|
|
[DEBUG] eval 1, 2, 5: 42
|
|
[DEBUG] eval 1, 2, 6: 41
|
|
[DEBUG] eval 1, 2, 7: 42
|
|
[DEBUG] eval 1, 3, 0: 44
|
|
[DEBUG] eval 1, 3, 1: 42
|
|
[DEBUG] eval 1, 3, 2: 42
|
|
[DEBUG] eval 1, 3, 3: 41
|
|
[DEBUG] eval 1, 3, 4: 41
|
|
[DEBUG] eval 1, 3, 5: 41
|
|
[DEBUG] eval 1, 3, 6: 41
|
|
[DEBUG] eval 1, 3, 7: 41
|
|
[DEBUG] discover rising edges:
|
|
[DEBUG] [4eb0] = 200
|
|
[DEBUG] eval 0, 2, 0: 40
|
|
[DEBUG] eval 0, 2, 1: 39
|
|
[DEBUG] eval 0, 2, 2: 40
|
|
[DEBUG] eval 0, 2, 3: 41
|
|
[DEBUG] eval 0, 2, 4: 39
|
|
[DEBUG] eval 0, 2, 5: 38
|
|
[DEBUG] eval 0, 2, 6: 37
|
|
[DEBUG] eval 0, 2, 7: 39
|
|
[DEBUG] eval 0, 3, 0: 39
|
|
[DEBUG] eval 0, 3, 1: 38
|
|
[DEBUG] eval 0, 3, 2: 39
|
|
[DEBUG] eval 0, 3, 3: 41
|
|
[DEBUG] eval 0, 3, 4: 39
|
|
[DEBUG] eval 0, 3, 5: 38
|
|
[DEBUG] eval 0, 3, 6: 38
|
|
[DEBUG] eval 0, 3, 7: 39
|
|
[DEBUG] eval 1, 2, 0: 43
|
|
[DEBUG] eval 1, 2, 1: 40
|
|
[DEBUG] eval 1, 2, 2: 42
|
|
[DEBUG] eval 1, 2, 3: 43
|
|
[DEBUG] eval 1, 2, 4: 41
|
|
[DEBUG] eval 1, 2, 5: 41
|
|
[DEBUG] eval 1, 2, 6: 39
|
|
[DEBUG] eval 1, 2, 7: 43
|
|
[DEBUG] eval 1, 3, 0: 41
|
|
[DEBUG] eval 1, 3, 1: 41
|
|
[DEBUG] eval 1, 3, 2: 42
|
|
[DEBUG] eval 1, 3, 3: 41
|
|
[DEBUG] eval 1, 3, 4: 41
|
|
[DEBUG] eval 1, 3, 5: 42
|
|
[DEBUG] eval 1, 3, 6: 41
|
|
[DEBUG] eval 1, 3, 7: 43
|
|
[DEBUG] CPE
|
|
[DEBUG] tx_dqs: 0, 2, 0: 68- 97- 126
|
|
[DEBUG] tx_dqs: 0, 2, 1: 91- 122- 26
|
|
[DEBUG] tx_dqs: 0, 2, 2: 121- 24- 56
|
|
[DEBUG] tx_dqs: 0, 2, 3: 5- 36- 67
|
|
[DEBUG] tx_dqs: 0, 2, 4: 32- 63- 94
|
|
[DEBUG] tx_dqs: 0, 2, 5: 41- 72- 104
|
|
[DEBUG] tx_dqs: 0, 2, 6: 49- 80- 112
|
|
[DEBUG] tx_dqs: 0, 2, 7: 57- 88- 120
|
|
[DEBUG] tx_dqs: 0, 3, 0: 64- 94- 124
|
|
[DEBUG] tx_dqs: 0, 3, 1: 95- 126- 30
|
|
[DEBUG] tx_dqs: 0, 3, 2: 117- 22- 55
|
|
[DEBUG] tx_dqs: 0, 3, 3: 9- 39- 69
|
|
[DEBUG] tx_dqs: 0, 3, 4: 32- 63- 95
|
|
[DEBUG] tx_dqs: 0, 3, 5: 44- 74- 104
|
|
[DEBUG] tx_dqs: 0, 3, 6: 51- 82- 113
|
|
[DEBUG] tx_dqs: 0, 3, 7: 57- 87- 118
|
|
[DEBUG] tx_dqs: 1, 2, 0: 70- 95- 121
|
|
[DEBUG] tx_dqs: 1, 2, 1: 85- 118- 24
|
|
[DEBUG] tx_dqs: 1, 2, 2: 115- 20- 54
|
|
[DEBUG] tx_dqs: 1, 2, 3: 5- 35- 66
|
|
[DEBUG] tx_dqs: 1, 2, 4: 30- 61- 92
|
|
[DEBUG] tx_dqs: 1, 2, 5: 44- 75- 106
|
|
[DEBUG] tx_dqs: 1, 2, 6: 42- 73- 104
|
|
[DEBUG] tx_dqs: 1, 2, 7: 60- 91- 123
|
|
[DEBUG] tx_dqs: 1, 3, 0: 67- 97- 0
|
|
[DEBUG] tx_dqs: 1, 3, 1: 92- 123- 26
|
|
[DEBUG] tx_dqs: 1, 3, 2: 121- 23- 54
|
|
[DEBUG] tx_dqs: 1, 3, 3: 3- 34- 66
|
|
[DEBUG] tx_dqs: 1, 3, 4: 33- 64- 95
|
|
[DEBUG] tx_dqs: 1, 3, 5: 47- 78- 110
|
|
[DEBUG] tx_dqs: 1, 3, 6: 54- 84- 114
|
|
[DEBUG] tx_dqs: 1, 3, 7: 64- 94- 125
|
|
[DEBUG] CPF
|
|
[DEBUG] tx_dq: 0, 2, 0: 8- 35- 63
|
|
[DEBUG] tx_dq: 0, 2, 1: 29- 56- 84
|
|
[DEBUG] tx_dq: 0, 2, 2: 56- 85- 114
|
|
[DEBUG] tx_dq: 0, 2, 3: 6- 33- 60
|
|
[DEBUG] tx_dq: 0, 2, 4: 33- 61- 89
|
|
[DEBUG] tx_dq: 0, 2, 5: 46- 74- 102
|
|
[DEBUG] tx_dq: 0, 2, 6: 54- 81- 108
|
|
[DEBUG] tx_dq: 0, 2, 7: 60- 88- 116
|
|
[DEBUG] tx_dq: 0, 3, 0: 3- 30- 57
|
|
[DEBUG] tx_dq: 0, 3, 1: 32- 59- 87
|
|
[DEBUG] tx_dq: 0, 3, 2: 52- 81- 110
|
|
[DEBUG] tx_dq: 0, 3, 3: 11- 37- 64
|
|
[DEBUG] tx_dq: 0, 3, 4: 34- 61- 89
|
|
[DEBUG] tx_dq: 0, 3, 5: 49- 76- 104
|
|
[DEBUG] tx_dq: 0, 3, 6: 56- 83- 110
|
|
[DEBUG] tx_dq: 0, 3, 7: 60- 87- 115
|
|
[DEBUG] tx_dq: 1, 2, 0: 6- 34- 62
|
|
[DEBUG] tx_dq: 1, 2, 1: 25- 51- 78
|
|
[DEBUG] tx_dq: 1, 2, 2: 56- 82- 108
|
|
[DEBUG] tx_dq: 1, 2, 3: 6- 33- 61
|
|
[DEBUG] tx_dq: 1, 2, 4: 31- 59- 87
|
|
[DEBUG] tx_dq: 1, 2, 5: 47- 71- 96
|
|
[DEBUG] tx_dq: 1, 2, 6: 44- 71- 98
|
|
[DEBUG] tx_dq: 1, 2, 7: 63- 89- 116
|
|
[DEBUG] tx_dq: 1, 3, 0: 4- 31- 59
|
|
[DEBUG] tx_dq: 1, 3, 1: 32- 58- 85
|
|
[DEBUG] tx_dq: 1, 3, 2: 62- 87- 113
|
|
[DEBUG] tx_dq: 1, 3, 3: 4- 31- 59
|
|
[DEBUG] tx_dq: 1, 3, 4: 36- 62- 89
|
|
[DEBUG] tx_dq: 1, 3, 5: 49- 75- 102
|
|
[DEBUG] tx_dq: 1, 3, 6: 56- 83- 110
|
|
[DEBUG] tx_dq: 1, 3, 7: 4- 30- 56
|
|
[DEBUG] High adjust 0:0000ffffffffffff
|
|
[DEBUG] Bval+: 0, 2, 0, 68 -> 196
|
|
[DEBUG] High adjust 1:0000ffffffffffff
|
|
[DEBUG] Bval+: 0, 2, 1, 91 -> 219
|
|
[DEBUG] High adjust 2:0000ffffffffffff
|
|
[DEBUG] Bval+: 0, 2, 2, 121 -> 249
|
|
[DEBUG] High adjust 3:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 2, 3, 5 -> 261
|
|
[DEBUG] High adjust 4:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 2, 4, 32 -> 288
|
|
[DEBUG] High adjust 5:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 2, 5, 41 -> 297
|
|
[DEBUG] High adjust 6:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 2, 6, 49 -> 305
|
|
[DEBUG] High adjust 7:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 2, 7, 57 -> 313
|
|
[DEBUG] High adjust 0:0000ffffffffffff
|
|
[DEBUG] Bval+: 0, 3, 0, 64 -> 192
|
|
[DEBUG] High adjust 1:0000ffffffffffff
|
|
[DEBUG] Bval+: 0, 3, 1, 95 -> 223
|
|
[DEBUG] High adjust 2:0000ffffffffffff
|
|
[DEBUG] Bval+: 0, 3, 2, 117 -> 245
|
|
[DEBUG] High adjust 3:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 3, 3, 9 -> 265
|
|
[DEBUG] High adjust 4:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 3, 4, 32 -> 288
|
|
[DEBUG] High adjust 5:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 3, 5, 44 -> 300
|
|
[DEBUG] High adjust 6:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 3, 6, 51 -> 307
|
|
[DEBUG] High adjust 7:00000000ffffffff
|
|
[DEBUG] Bval+: 0, 3, 7, 57 -> 313
|
|
[DEBUG] High adjust 0:0000ffffffffffff
|
|
[DEBUG] Bval+: 1, 2, 0, 70 -> 198
|
|
[DEBUG] High adjust 1:0000ffffffffffff
|
|
[DEBUG] Bval+: 1, 2, 1, 85 -> 213
|
|
[DEBUG] High adjust 2:0000ffffffffffff
|
|
[DEBUG] Bval+: 1, 2, 2, 115 -> 243
|
|
[DEBUG] High adjust 3:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 2, 3, 5 -> 261
|
|
[DEBUG] High adjust 4:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 2, 4, 30 -> 286
|
|
[DEBUG] High adjust 5:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 2, 5, 44 -> 300
|
|
[DEBUG] High adjust 6:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 2, 6, 42 -> 298
|
|
[DEBUG] High adjust 7:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 2, 7, 60 -> 316
|
|
[DEBUG] High adjust 0:0000ffffffffffff
|
|
[DEBUG] Bval+: 1, 3, 0, 67 -> 195
|
|
[DEBUG] High adjust 1:0000ffffffffffff
|
|
[DEBUG] Bval+: 1, 3, 1, 92 -> 220
|
|
[DEBUG] High adjust 2:0000ffffffffffff
|
|
[DEBUG] Bval+: 1, 3, 2, 121 -> 249
|
|
[DEBUG] High adjust 3:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 3, 3, 3 -> 259
|
|
[DEBUG] High adjust 4:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 3, 4, 33 -> 289
|
|
[DEBUG] High adjust 5:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 3, 5, 47 -> 303
|
|
[DEBUG] High adjust 6:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 3, 6, 54 -> 310
|
|
[DEBUG] High adjust 7:00000000ffffffff
|
|
[DEBUG] Bval+: 1, 3, 7, 64 -> 320
|
|
[DEBUG] CP5a
|
|
[DEBUG] CP5b
|
|
[DEBUG] Trying cmd_stretch 0 on channel 0
|
|
[DEBUG] cmd_stretch: 0, 2: 78- 124- 170
|
|
[DEBUG] cmd_stretch: 0, 3: 76- 123- 170
|
|
[DEBUG] Using CMD rate 1T on channel 0
|
|
[DEBUG] Trying cmd_stretch 0 on channel 1
|
|
[DEBUG] cmd_stretch: 1, 2: 80- 125- 171
|
|
[DEBUG] cmd_stretch: 1, 3: 78- 122- 167
|
|
[DEBUG] Using CMD rate 1T on channel 1
|
|
[DEBUG] CP5c
|
|
[DEBUG] discover falling edges aggressive:
|
|
[DEBUG] [4eb0] = 300
|
|
[DEBUG] [3000] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 2, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 0, 2, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 2, 0: 15- 40- 66, 28- 53
|
|
[DEBUG] edges: 0, 2, 0: 15- 40- 66, 28- 53
|
|
[DEBUG] edges: 0, 2, 0: 13- 37- 62, 26- 49
|
|
[DEBUG] edges: 0, 2, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 2, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 0, 2, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 2, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 2, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 2, 0: 14- 39- 64, 27- 51
|
|
[DEBUG] edges: 0, 2, 0: 14- 39- 64, 27- 51
|
|
[DEBUG] edges: 0, 2, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 2, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 2, 0: 14- 37- 61, 27- 48
|
|
[DEBUG] edges: 0, 2, 0: 16- 41- 67, 29- 54
|
|
[DEBUG] edges: 0, 2, 0: 15- 41- 67, 28- 54
|
|
[DEBUG] edges: 0, 2, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 2, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 2, 0: 16- 38- 60, 29- 47
|
|
[DEBUG] edges: 0, 2, 0: 15- 37- 60, 28- 47
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 2, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 2, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 2, 0: 16- 41- 66, 29- 53
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 2, 0: 13- 37- 62, 26- 49
|
|
[DEBUG] edges: 0, 2, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] [3000] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 2, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 0, 2, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 0, 2, 1: 20- 41- 63, 25- 58
|
|
[DEBUG] edges: 0, 2, 1: 20- 41- 62, 25- 57
|
|
[DEBUG] edges: 0, 2, 1: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 0, 2, 1: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 2, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 0, 2, 1: 18- 36- 55, 23- 50
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 2, 1: 22- 40- 59, 27- 54
|
|
[DEBUG] edges: 0, 2, 1: 19- 39- 59, 24- 54
|
|
[DEBUG] edges: 0, 2, 1: 21- 41- 62, 26- 57
|
|
[DEBUG] edges: 0, 2, 1: 20- 40- 61, 25- 56
|
|
[DEBUG] edges: 0, 2, 1: 17- 39- 61, 22- 56
|
|
[DEBUG] edges: 0, 2, 1: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 2, 1: 18- 39- 60, 23- 55
|
|
[DEBUG] edges: 0, 2, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 2, 1: 22- 42- 62, 27- 57
|
|
[DEBUG] edges: 0, 2, 1: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 1: 21- 42- 64, 26- 59
|
|
[DEBUG] edges: 0, 2, 1: 20- 41- 63, 25- 58
|
|
[DEBUG] edges: 0, 2, 1: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 2, 1: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 2, 1: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 2, 1: 17- 36- 56, 22- 51
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 2, 1: 22- 42- 63, 27- 58
|
|
[DEBUG] edges: 0, 2, 1: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 2, 1: 21- 42- 63, 26- 58
|
|
[DEBUG] edges: 0, 2, 1: 19- 41- 63, 24- 58
|
|
[DEBUG] edges: 0, 2, 1: 17- 39- 62, 22- 57
|
|
[DEBUG] edges: 0, 2, 1: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 0, 2, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 2, 1: 18- 39- 61, 23- 56
|
|
[DEBUG] [3000] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 2, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 2, 2: 20- 41- 62, 25- 57
|
|
[DEBUG] edges: 0, 2, 2: 20- 41- 62, 25- 57
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 2, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 2, 2: 19- 37- 55, 24- 50
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 2, 2: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 0, 2, 2: 18- 37- 57, 23- 52
|
|
[DEBUG] edges: 0, 2, 2: 21- 40- 59, 26- 54
|
|
[DEBUG] edges: 0, 2, 2: 20- 40- 60, 25- 55
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 2, 2: 20- 38- 56, 25- 51
|
|
[DEBUG] edges: 0, 2, 2: 20- 38- 56, 25- 51
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 2, 2: 21- 40- 60, 26- 55
|
|
[DEBUG] edges: 0, 2, 2: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 2, 2: 21- 42- 63, 26- 58
|
|
[DEBUG] edges: 0, 2, 2: 21- 41- 62, 26- 57
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 2: 18- 34- 51, 23- 46
|
|
[DEBUG] edges: 0, 2, 2: 21- 37- 54, 26- 49
|
|
[DEBUG] edges: 0, 2, 2: 21- 37- 54, 26- 49
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 2, 2: 21- 41- 62, 26- 57
|
|
[DEBUG] edges: 0, 2, 2: 19- 37- 56, 24- 51
|
|
[DEBUG] edges: 0, 2, 2: 20- 41- 63, 25- 58
|
|
[DEBUG] edges: 0, 2, 2: 20- 39- 59, 25- 54
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 2, 2: 18- 38- 58, 23- 53
|
|
[DEBUG] edges: 0, 2, 2: 21- 39- 57, 26- 52
|
|
[DEBUG] edges: 0, 2, 2: 21- 40- 59, 26- 54
|
|
[DEBUG] CPA
|
|
[DEBUG] [3000] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 3, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 63, 27- 50
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 0, 3, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 3, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 0, 3, 0: 13- 37- 62, 26- 49
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 3, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 3, 0: 15- 40- 65, 28- 52
|
|
[DEBUG] edges: 0, 3, 0: 15- 40- 65, 28- 52
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 14- 39- 64, 27- 51
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 3, 0: 16- 40- 65, 29- 52
|
|
[DEBUG] edges: 0, 3, 0: 14- 39- 64, 27- 51
|
|
[DEBUG] edges: 0, 3, 0: 15- 40- 65, 28- 52
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 3, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 3, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 0, 3, 0: 14- 39- 64, 27- 51
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 3, 0: 13- 38- 63, 26- 50
|
|
[DEBUG] edges: 0, 3, 0: 16- 39- 63, 29- 50
|
|
[DEBUG] edges: 0, 3, 0: 14- 39- 64, 27- 51
|
|
[DEBUG] [3000] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 3, 1: 20- 39- 59, 25- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 38- 60, 22- 55
|
|
[DEBUG] edges: 0, 3, 1: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 1: 19- 39- 59, 24- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 0, 3, 1: 18- 36- 55, 23- 50
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 3, 1: 22- 41- 61, 27- 56
|
|
[DEBUG] edges: 0, 3, 1: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 1: 20- 40- 61, 25- 56
|
|
[DEBUG] edges: 0, 3, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 0, 3, 1: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 0, 3, 1: 19- 37- 55, 24- 50
|
|
[DEBUG] edges: 0, 3, 1: 18- 40- 62, 23- 57
|
|
[DEBUG] edges: 0, 3, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 3, 1: 21- 41- 62, 26- 57
|
|
[DEBUG] edges: 0, 3, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 3, 1: 20- 40- 61, 25- 56
|
|
[DEBUG] edges: 0, 3, 1: 20- 40- 61, 25- 56
|
|
[DEBUG] edges: 0, 3, 1: 17- 39- 61, 22- 56
|
|
[DEBUG] edges: 0, 3, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 39- 61, 22- 56
|
|
[DEBUG] edges: 0, 3, 1: 17- 38- 59, 22- 54
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 3, 1: 22- 42- 62, 27- 57
|
|
[DEBUG] edges: 0, 3, 1: 19- 39- 59, 24- 54
|
|
[DEBUG] edges: 0, 3, 1: 20- 41- 62, 25- 57
|
|
[DEBUG] edges: 0, 3, 1: 19- 39- 59, 24- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 39- 61, 22- 56
|
|
[DEBUG] edges: 0, 3, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 3, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 39- 62, 22- 57
|
|
[DEBUG] [3000] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 3, 2: 18- 37- 57, 23- 52
|
|
[DEBUG] edges: 0, 3, 2: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 0, 3, 2: 19- 39- 59, 24- 54
|
|
[DEBUG] edges: 0, 3, 2: 20- 39- 59, 25- 54
|
|
[DEBUG] edges: 0, 3, 2: 19- 37- 56, 24- 51
|
|
[DEBUG] edges: 0, 3, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 3, 2: 20- 38- 57, 25- 52
|
|
[DEBUG] edges: 0, 3, 2: 18- 38- 58, 23- 53
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 3, 2: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 2: 19- 39- 60, 24- 55
|
|
[DEBUG] edges: 0, 3, 2: 21- 40- 59, 26- 54
|
|
[DEBUG] edges: 0, 3, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 3, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 3, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 2: 19- 39- 60, 24- 55
|
|
[DEBUG] edges: 0, 3, 2: 18- 37- 57, 23- 52
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 3, 2: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 3, 2: 20- 40- 60, 25- 55
|
|
[DEBUG] edges: 0, 3, 2: 20- 40- 60, 25- 55
|
|
[DEBUG] edges: 0, 3, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 3, 2: 18- 36- 55, 23- 50
|
|
[DEBUG] edges: 0, 3, 2: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 0, 3, 2: 18- 37- 56, 23- 51
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 3, 2: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 2: 18- 39- 61, 23- 56
|
|
[DEBUG] edges: 0, 3, 2: 19- 41- 63, 24- 58
|
|
[DEBUG] edges: 0, 3, 2: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 0, 3, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 3, 2: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 3, 2: 20- 40- 61, 25- 56
|
|
[DEBUG] edges: 0, 3, 2: 18- 38- 59, 23- 54
|
|
[DEBUG] CPA
|
|
[DEBUG] [3100] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 2, 0: 19- 41- 63, 32- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 41- 66, 30- 53
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 2, 0: 16- 37- 59, 29- 46
|
|
[DEBUG] edges: 1, 2, 0: 17- 37- 57, 30- 44
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 2, 0: 18- 40- 63, 31- 50
|
|
[DEBUG] edges: 1, 2, 0: 20- 41- 63, 33- 50
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 64, 31- 51
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 65, 31- 52
|
|
[DEBUG] edges: 1, 2, 0: 18- 40- 62, 31- 49
|
|
[DEBUG] edges: 1, 2, 0: 19- 39- 60, 32- 47
|
|
[DEBUG] edges: 1, 2, 0: 16- 36- 57, 29- 44
|
|
[DEBUG] edges: 1, 2, 0: 17- 37- 57, 30- 44
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 2, 0: 19- 40- 62, 32- 49
|
|
[DEBUG] edges: 1, 2, 0: 19- 41- 64, 32- 51
|
|
[DEBUG] edges: 1, 2, 0: 18- 40- 63, 31- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 41- 65, 30- 52
|
|
[DEBUG] edges: 1, 2, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] edges: 1, 2, 0: 19- 41- 63, 32- 50
|
|
[DEBUG] edges: 1, 2, 0: 16- 37- 58, 29- 45
|
|
[DEBUG] edges: 1, 2, 0: 17- 38- 59, 30- 46
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 64, 31- 51
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 65, 31- 52
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 64, 31- 51
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 65, 31- 52
|
|
[DEBUG] edges: 1, 2, 0: 18- 41- 64, 31- 51
|
|
[DEBUG] edges: 1, 2, 0: 18- 38- 59, 31- 46
|
|
[DEBUG] edges: 1, 2, 0: 16- 38- 60, 29- 47
|
|
[DEBUG] edges: 1, 2, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] [3100] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 2, 1: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 2, 1: 24- 43- 62, 29- 57
|
|
[DEBUG] edges: 1, 2, 1: 24- 43- 62, 29- 57
|
|
[DEBUG] edges: 1, 2, 1: 23- 43- 63, 28- 58
|
|
[DEBUG] edges: 1, 2, 1: 23- 40- 58, 28- 53
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] edges: 1, 2, 1: 20- 38- 56, 25- 51
|
|
[DEBUG] edges: 1, 2, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 2, 1: 26- 44- 62, 31- 57
|
|
[DEBUG] edges: 1, 2, 1: 27- 43- 60, 32- 55
|
|
[DEBUG] edges: 1, 2, 1: 26- 43- 61, 31- 56
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 1: 22- 37- 53, 27- 48
|
|
[DEBUG] edges: 1, 2, 1: 23- 37- 52, 28- 47
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 2, 1: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 2, 1: 25- 43- 62, 30- 57
|
|
[DEBUG] edges: 1, 2, 1: 24- 43- 62, 29- 57
|
|
[DEBUG] edges: 1, 2, 1: 24- 42- 61, 29- 56
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 1: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 1, 2, 1: 23- 38- 54, 28- 49
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 2, 1: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 2, 1: 25- 44- 63, 30- 58
|
|
[DEBUG] edges: 1, 2, 1: 25- 44- 63, 30- 58
|
|
[DEBUG] edges: 1, 2, 1: 24- 43- 63, 29- 58
|
|
[DEBUG] edges: 1, 2, 1: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 2, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 1: 20- 38- 57, 25- 52
|
|
[DEBUG] edges: 1, 2, 1: 22- 41- 60, 27- 55
|
|
[DEBUG] [3100] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 2, 2: 23- 41- 59, 28- 54
|
|
[DEBUG] edges: 1, 2, 2: 25- 42- 59, 30- 54
|
|
[DEBUG] edges: 1, 2, 2: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 2, 2: 24- 44- 64, 29- 59
|
|
[DEBUG] edges: 1, 2, 2: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 2, 2: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 2, 2: 23- 39- 55, 28- 50
|
|
[DEBUG] edges: 1, 2, 2: 23- 37- 52, 28- 47
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 2, 2: 25- 41- 57, 30- 52
|
|
[DEBUG] edges: 1, 2, 2: 28- 43- 58, 33- 53
|
|
[DEBUG] edges: 1, 2, 2: 27- 44- 62, 32- 57
|
|
[DEBUG] edges: 1, 2, 2: 25- 42- 60, 30- 55
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 2, 2: 27- 41- 55, 32- 50
|
|
[DEBUG] edges: 1, 2, 2: 23- 37- 52, 28- 47
|
|
[DEBUG] edges: 1, 2, 2: 23- 38- 53, 28- 48
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 2, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 2, 2: 28- 44- 60, 33- 55
|
|
[DEBUG] edges: 1, 2, 2: 26- 42- 58, 31- 53
|
|
[DEBUG] edges: 1, 2, 2: 25- 43- 62, 30- 57
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 2, 2: 27- 42- 57, 32- 52
|
|
[DEBUG] edges: 1, 2, 2: 23- 38- 54, 28- 49
|
|
[DEBUG] edges: 1, 2, 2: 23- 38- 53, 28- 48
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 2, 2: 24- 42- 61, 29- 56
|
|
[DEBUG] edges: 1, 2, 2: 26- 43- 61, 31- 56
|
|
[DEBUG] edges: 1, 2, 2: 26- 43- 61, 31- 56
|
|
[DEBUG] edges: 1, 2, 2: 25- 42- 60, 30- 55
|
|
[DEBUG] edges: 1, 2, 2: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 2: 26- 40- 55, 31- 50
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] CPA
|
|
[DEBUG] [3100] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] edges: 1, 3, 0: 18- 40- 63, 31- 50
|
|
[DEBUG] edges: 1, 3, 0: 18- 41- 64, 31- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 61, 30- 48
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 61, 30- 48
|
|
[DEBUG] edges: 1, 3, 0: 16- 38- 61, 29- 48
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 3, 0: 17- 41- 65, 30- 52
|
|
[DEBUG] edges: 1, 3, 0: 19- 39- 60, 32- 47
|
|
[DEBUG] edges: 1, 3, 0: 19- 41- 63, 32- 50
|
|
[DEBUG] edges: 1, 3, 0: 18- 40- 62, 31- 49
|
|
[DEBUG] edges: 1, 3, 0: 18- 39- 60, 31- 47
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 59, 30- 46
|
|
[DEBUG] edges: 1, 3, 0: 16- 38- 60, 29- 47
|
|
[DEBUG] edges: 1, 3, 0: 17- 37- 58, 30- 45
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 3, 0: 19- 39- 60, 32- 47
|
|
[DEBUG] edges: 1, 3, 0: 19- 40- 62, 32- 49
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 59, 30- 46
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 59, 30- 46
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 3, 0: 17- 41- 65, 30- 52
|
|
[DEBUG] edges: 1, 3, 0: 18- 39- 61, 31- 48
|
|
[DEBUG] edges: 1, 3, 0: 19- 41- 63, 32- 50
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 61, 30- 48
|
|
[DEBUG] edges: 1, 3, 0: 18- 39- 61, 31- 48
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] [3100] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 3, 1: 23- 41- 60, 28- 55
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 59, 30- 54
|
|
[DEBUG] edges: 1, 3, 1: 23- 40- 58, 28- 53
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 1: 23- 40- 57, 28- 52
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 3, 1: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 3, 1: 28- 42- 56, 33- 51
|
|
[DEBUG] edges: 1, 3, 1: 25- 40- 56, 30- 51
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 55, 28- 50
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 1: 26- 43- 60, 31- 55
|
|
[DEBUG] edges: 1, 3, 1: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 1: 23- 40- 57, 28- 52
|
|
[DEBUG] edges: 1, 3, 1: 22- 38- 55, 27- 50
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 3, 1: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 60, 30- 55
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 60, 30- 55
|
|
[DEBUG] edges: 1, 3, 1: 23- 41- 60, 28- 55
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] edges: 1, 3, 1: 21- 40- 59, 26- 54
|
|
[DEBUG] edges: 1, 3, 1: 21- 40- 59, 26- 54
|
|
[DEBUG] [3100] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 3, 2: 21- 40- 59, 26- 54
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 2: 25- 41- 57, 30- 52
|
|
[DEBUG] edges: 1, 3, 2: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 3, 2: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 2: 22- 38- 54, 27- 49
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 3, 2: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 3, 2: 27- 39- 52, 32- 47
|
|
[DEBUG] edges: 1, 3, 2: 28- 44- 61, 33- 56
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 3, 2: 25- 40- 55, 30- 50
|
|
[DEBUG] edges: 1, 3, 2: 26- 39- 53, 31- 48
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 54, 29- 49
|
|
[DEBUG] edges: 1, 3, 2: 23- 38- 54, 28- 49
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 3, 2: 27- 41- 55, 32- 50
|
|
[DEBUG] edges: 1, 3, 2: 27- 41- 55, 32- 50
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 3, 2: 26- 40- 55, 31- 50
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 3, 2: 23- 38- 54, 28- 49
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 3, 2: 23- 41- 59, 28- 54
|
|
[DEBUG] edges: 1, 3, 2: 25- 40- 56, 30- 51
|
|
[DEBUG] edges: 1, 3, 2: 27- 43- 59, 32- 54
|
|
[DEBUG] edges: 1, 3, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 2: 25- 40- 55, 30- 50
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 2: 23- 39- 56, 28- 51
|
|
[DEBUG] CPA
|
|
[DEBUG] discover rising edges aggressive:
|
|
[DEBUG] [4eb0] = 200
|
|
[DEBUG] [3000] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 2, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 0, 2, 0: 12- 38- 64, 25- 51
|
|
[DEBUG] edges: 0, 2, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] edges: 0, 2, 0: 15- 37- 60, 28- 47
|
|
[DEBUG] edges: 0, 2, 0: 10- 36- 63, 23- 50
|
|
[DEBUG] edges: 0, 2, 0: 9- 34- 60, 22- 47
|
|
[DEBUG] edges: 0, 2, 0: 11- 36- 62, 24- 49
|
|
[DEBUG] edges: 0, 2, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 2, 0: 13- 38- 63, 26- 50
|
|
[DEBUG] edges: 0, 2, 0: 13- 37- 61, 26- 48
|
|
[DEBUG] edges: 0, 2, 0: 14- 37- 61, 27- 48
|
|
[DEBUG] edges: 0, 2, 0: 12- 38- 64, 25- 51
|
|
[DEBUG] edges: 0, 2, 0: 10- 33- 57, 23- 44
|
|
[DEBUG] edges: 0, 2, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] edges: 0, 2, 0: 13- 39- 65, 26- 52
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 2, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 0, 2, 0: 13- 37- 61, 26- 48
|
|
[DEBUG] edges: 0, 2, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 0, 2, 0: 15- 37- 59, 28- 46
|
|
[DEBUG] edges: 0, 2, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] edges: 0, 2, 0: 11- 35- 60, 24- 47
|
|
[DEBUG] edges: 0, 2, 0: 12- 36- 60, 25- 47
|
|
[DEBUG] edges: 0, 2, 0: 13- 37- 62, 26- 49
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 2, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 0, 2, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 2, 0: 13- 36- 59, 26- 46
|
|
[DEBUG] edges: 0, 2, 0: 12- 35- 59, 25- 46
|
|
[DEBUG] edges: 0, 2, 0: 11- 37- 64, 24- 51
|
|
[DEBUG] edges: 0, 2, 0: 10- 35- 61, 23- 48
|
|
[DEBUG] edges: 0, 2, 0: 11- 34- 58, 24- 45
|
|
[DEBUG] edges: 0, 2, 0: 13- 37- 62, 26- 49
|
|
[DEBUG] [3000] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 2, 1: 21- 39- 57, 26- 52
|
|
[DEBUG] edges: 0, 2, 1: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 2, 1: 18- 38- 58, 23- 53
|
|
[DEBUG] edges: 0, 2, 1: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 0, 2, 1: 15- 37- 59, 20- 54
|
|
[DEBUG] edges: 0, 2, 1: 16- 36- 56, 21- 51
|
|
[DEBUG] edges: 0, 2, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 0, 2, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 2, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 0, 2, 1: 19- 39- 60, 24- 55
|
|
[DEBUG] edges: 0, 2, 1: 19- 37- 56, 24- 51
|
|
[DEBUG] edges: 0, 2, 1: 20- 38- 56, 25- 51
|
|
[DEBUG] edges: 0, 2, 1: 15- 37- 60, 20- 55
|
|
[DEBUG] edges: 0, 2, 1: 15- 35- 56, 20- 51
|
|
[DEBUG] edges: 0, 2, 1: 16- 37- 58, 21- 53
|
|
[DEBUG] edges: 0, 2, 1: 17- 39- 61, 22- 56
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 2, 1: 23- 41- 59, 28- 54
|
|
[DEBUG] edges: 0, 2, 1: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 1: 20- 38- 57, 25- 52
|
|
[DEBUG] edges: 0, 2, 1: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 0, 2, 1: 16- 36- 57, 21- 52
|
|
[DEBUG] edges: 0, 2, 1: 17- 36- 55, 22- 50
|
|
[DEBUG] edges: 0, 2, 1: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 2, 1: 18- 37- 57, 23- 52
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 2, 1: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 0, 2, 1: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 1: 18- 36- 55, 23- 50
|
|
[DEBUG] edges: 0, 2, 1: 19- 37- 55, 24- 50
|
|
[DEBUG] edges: 0, 2, 1: 16- 37- 59, 21- 54
|
|
[DEBUG] edges: 0, 2, 1: 16- 36- 56, 21- 51
|
|
[DEBUG] edges: 0, 2, 1: 17- 36- 55, 22- 50
|
|
[DEBUG] edges: 0, 2, 1: 18- 38- 58, 23- 53
|
|
[DEBUG] [3000] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 2, 2: 15- 37- 59, 20- 54
|
|
[DEBUG] edges: 0, 2, 2: 16- 37- 59, 21- 54
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 2: 16- 37- 58, 21- 53
|
|
[DEBUG] edges: 0, 2, 2: 15- 35- 56, 20- 51
|
|
[DEBUG] edges: 0, 2, 2: 16- 37- 58, 21- 53
|
|
[DEBUG] edges: 0, 2, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 2, 2: 21- 40- 60, 26- 55
|
|
[DEBUG] edges: 0, 2, 2: 18- 39- 61, 23- 56
|
|
[DEBUG] edges: 0, 2, 2: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 2, 2: 20- 38- 57, 25- 52
|
|
[DEBUG] edges: 0, 2, 2: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 2, 2: 16- 36- 57, 21- 52
|
|
[DEBUG] edges: 0, 2, 2: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 2, 2: 20- 40- 61, 25- 56
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 2, 2: 22- 41- 61, 27- 56
|
|
[DEBUG] edges: 0, 2, 2: 18- 39- 60, 23- 55
|
|
[DEBUG] edges: 0, 2, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 2, 2: 18- 39- 60, 23- 55
|
|
[DEBUG] edges: 0, 2, 2: 17- 39- 61, 22- 56
|
|
[DEBUG] edges: 0, 2, 2: 16- 36- 56, 21- 51
|
|
[DEBUG] edges: 0, 2, 2: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 2, 2: 20- 41- 62, 25- 57
|
|
[DEBUG] edges: 0, 2, 2: 17- 38- 60, 22- 55
|
|
[DEBUG] edges: 0, 2, 2: 17- 38- 60, 22- 55
|
|
[DEBUG] edges: 0, 2, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 2, 2: 17- 38- 60, 22- 55
|
|
[DEBUG] edges: 0, 2, 2: 16- 37- 58, 21- 53
|
|
[DEBUG] edges: 0, 2, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 2, 2: 20- 40- 60, 25- 55
|
|
[DEBUG] CPA
|
|
[DEBUG] [3000] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 3, 0: 11- 35- 60, 24- 47
|
|
[DEBUG] edges: 0, 3, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 3, 0: 11- 36- 61, 24- 48
|
|
[DEBUG] edges: 0, 3, 0: 10- 34- 59, 23- 46
|
|
[DEBUG] edges: 0, 3, 0: 12- 34- 57, 25- 44
|
|
[DEBUG] edges: 0, 3, 0: 12- 36- 60, 25- 47
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 3, 0: 12- 36- 61, 25- 48
|
|
[DEBUG] edges: 0, 3, 0: 13- 38- 63, 26- 50
|
|
[DEBUG] edges: 0, 3, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 0, 3, 0: 12- 37- 63, 25- 50
|
|
[DEBUG] edges: 0, 3, 0: 11- 35- 59, 24- 46
|
|
[DEBUG] edges: 0, 3, 0: 13- 37- 61, 26- 48
|
|
[DEBUG] edges: 0, 3, 0: 12- 37- 63, 25- 50
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 3, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 0, 3, 0: 13- 37- 62, 26- 49
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 62, 27- 49
|
|
[DEBUG] edges: 0, 3, 0: 14- 38- 63, 27- 50
|
|
[DEBUG] edges: 0, 3, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] edges: 0, 3, 0: 12- 35- 59, 25- 46
|
|
[DEBUG] edges: 0, 3, 0: 13- 36- 60, 26- 47
|
|
[DEBUG] edges: 0, 3, 0: 13- 37- 61, 26- 48
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 3, 0: 15- 38- 61, 28- 48
|
|
[DEBUG] edges: 0, 3, 0: 13- 36- 59, 26- 46
|
|
[DEBUG] edges: 0, 3, 0: 13- 37- 61, 26- 48
|
|
[DEBUG] edges: 0, 3, 0: 12- 37- 62, 25- 49
|
|
[DEBUG] edges: 0, 3, 0: 12- 38- 64, 25- 51
|
|
[DEBUG] edges: 0, 3, 0: 12- 36- 61, 25- 48
|
|
[DEBUG] edges: 0, 3, 0: 12- 35- 58, 25- 45
|
|
[DEBUG] edges: 0, 3, 0: 12- 37- 63, 25- 50
|
|
[DEBUG] [3000] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 3, 1: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 1: 21- 39- 58, 26- 53
|
|
[DEBUG] edges: 0, 3, 1: 16- 36- 57, 21- 52
|
|
[DEBUG] edges: 0, 3, 1: 16- 36- 56, 21- 51
|
|
[DEBUG] edges: 0, 3, 1: 16- 35- 55, 21- 50
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 57, 22- 52
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 3, 1: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 1: 19- 39- 60, 24- 55
|
|
[DEBUG] edges: 0, 3, 1: 21- 40- 60, 26- 55
|
|
[DEBUG] edges: 0, 3, 1: 16- 37- 59, 21- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 3, 1: 16- 36- 56, 21- 51
|
|
[DEBUG] edges: 0, 3, 1: 17- 37- 58, 22- 53
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 3, 1: 22- 40- 59, 27- 54
|
|
[DEBUG] edges: 0, 3, 1: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 3, 1: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 0, 3, 1: 20- 39- 59, 25- 54
|
|
[DEBUG] edges: 0, 3, 1: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 0, 3, 1: 18- 37- 57, 23- 52
|
|
[DEBUG] edges: 0, 3, 1: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 3, 1: 18- 37- 57, 23- 52
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 3, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 0, 3, 1: 19- 37- 55, 24- 50
|
|
[DEBUG] edges: 0, 3, 1: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 3, 1: 18- 38- 58, 23- 53
|
|
[DEBUG] edges: 0, 3, 1: 16- 38- 60, 21- 55
|
|
[DEBUG] edges: 0, 3, 1: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 3, 1: 17- 35- 54, 22- 49
|
|
[DEBUG] edges: 0, 3, 1: 17- 38- 59, 22- 54
|
|
[DEBUG] [3000] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 0, 3, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 3, 2: 15- 36- 57, 20- 52
|
|
[DEBUG] edges: 0, 3, 2: 16- 36- 57, 21- 52
|
|
[DEBUG] edges: 0, 3, 2: 19- 39- 59, 24- 54
|
|
[DEBUG] edges: 0, 3, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 2: 15- 36- 57, 20- 52
|
|
[DEBUG] edges: 0, 3, 2: 17- 36- 55, 22- 50
|
|
[DEBUG] edges: 0, 3, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 0, 3, 2: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 2: 18- 39- 60, 23- 55
|
|
[DEBUG] edges: 0, 3, 2: 18- 38- 58, 23- 53
|
|
[DEBUG] edges: 0, 3, 2: 20- 40- 60, 25- 55
|
|
[DEBUG] edges: 0, 3, 2: 18- 38- 58, 23- 53
|
|
[DEBUG] edges: 0, 3, 2: 17- 36- 56, 22- 51
|
|
[DEBUG] edges: 0, 3, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 0, 3, 2: 18- 39- 61, 23- 56
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 0, 3, 2: 19- 40- 61, 24- 56
|
|
[DEBUG] edges: 0, 3, 2: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 0, 3, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 2: 18- 40- 63, 23- 58
|
|
[DEBUG] edges: 0, 3, 2: 18- 39- 60, 23- 55
|
|
[DEBUG] edges: 0, 3, 2: 16- 36- 56, 21- 51
|
|
[DEBUG] edges: 0, 3, 2: 19- 37- 55, 24- 50
|
|
[DEBUG] edges: 0, 3, 2: 19- 37- 56, 24- 51
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 0, 3, 2: 19- 39- 60, 24- 55
|
|
[DEBUG] edges: 0, 3, 2: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 0, 3, 2: 17- 38- 60, 22- 55
|
|
[DEBUG] edges: 0, 3, 2: 18- 38- 59, 23- 54
|
|
[DEBUG] edges: 0, 3, 2: 17- 37- 58, 22- 53
|
|
[DEBUG] edges: 0, 3, 2: 16- 37- 59, 21- 54
|
|
[DEBUG] edges: 0, 3, 2: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 0, 3, 2: 19- 39- 59, 24- 54
|
|
[DEBUG] CPA
|
|
[DEBUG] [3100] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 2, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 1, 2, 0: 12- 36- 60, 25- 47
|
|
[DEBUG] edges: 1, 2, 0: 16- 39- 63, 29- 50
|
|
[DEBUG] edges: 1, 2, 0: 15- 38- 61, 28- 48
|
|
[DEBUG] edges: 1, 2, 0: 13- 38- 63, 26- 50
|
|
[DEBUG] edges: 1, 2, 0: 14- 37- 60, 27- 47
|
|
[DEBUG] edges: 1, 2, 0: 13- 38- 64, 26- 51
|
|
[DEBUG] edges: 1, 2, 0: 16- 39- 63, 29- 50
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 37- 57, 30- 44
|
|
[DEBUG] edges: 1, 2, 0: 19- 41- 63, 32- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 38- 59, 30- 46
|
|
[DEBUG] edges: 1, 2, 0: 16- 39- 63, 29- 50
|
|
[DEBUG] edges: 1, 2, 0: 16- 36- 57, 29- 44
|
|
[DEBUG] edges: 1, 2, 0: 15- 37- 59, 28- 46
|
|
[DEBUG] edges: 1, 2, 0: 17- 38- 59, 30- 46
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 39- 61, 30- 48
|
|
[DEBUG] edges: 1, 2, 0: 19- 40- 61, 32- 48
|
|
[DEBUG] edges: 1, 2, 0: 17- 37- 57, 30- 44
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] edges: 1, 2, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 1, 2, 0: 16- 38- 60, 29- 47
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 2, 0: 16- 37- 59, 29- 46
|
|
[DEBUG] edges: 1, 2, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] edges: 1, 2, 0: 17- 37- 57, 30- 44
|
|
[DEBUG] edges: 1, 2, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 1, 2, 0: 17- 37- 57, 30- 44
|
|
[DEBUG] edges: 1, 2, 0: 14- 38- 63, 27- 50
|
|
[DEBUG] edges: 1, 2, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] [3100] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 2, 1: 20- 40- 60, 25- 55
|
|
[DEBUG] edges: 1, 2, 1: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 1, 2, 1: 22- 40- 58, 27- 53
|
|
[DEBUG] edges: 1, 2, 1: 20- 38- 57, 25- 52
|
|
[DEBUG] edges: 1, 2, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 1, 2, 1: 21- 38- 55, 26- 50
|
|
[DEBUG] edges: 1, 2, 1: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 1, 2, 1: 21- 40- 59, 26- 54
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 2, 1: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 2, 1: 24- 39- 54, 29- 49
|
|
[DEBUG] edges: 1, 2, 1: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 2, 1: 23- 38- 54, 28- 49
|
|
[DEBUG] edges: 1, 2, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 2, 1: 23- 39- 55, 28- 50
|
|
[DEBUG] edges: 1, 2, 1: 21- 38- 55, 26- 50
|
|
[DEBUG] edges: 1, 2, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 2, 1: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 2, 1: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 2, 1: 26- 41- 56, 31- 51
|
|
[DEBUG] edges: 1, 2, 1: 23- 38- 54, 28- 49
|
|
[DEBUG] edges: 1, 2, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 2, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 2, 1: 21- 39- 57, 26- 52
|
|
[DEBUG] edges: 1, 2, 1: 24- 40- 56, 29- 51
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 2, 1: 24- 43- 62, 29- 57
|
|
[DEBUG] edges: 1, 2, 1: 23- 39- 55, 28- 50
|
|
[DEBUG] edges: 1, 2, 1: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 2, 1: 21- 38- 55, 26- 50
|
|
[DEBUG] edges: 1, 2, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 2, 1: 23- 39- 55, 28- 50
|
|
[DEBUG] edges: 1, 2, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 1, 2, 1: 23- 42- 62, 28- 57
|
|
[DEBUG] [3100] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 2, 2: 21- 41- 61, 26- 56
|
|
[DEBUG] edges: 1, 2, 2: 17- 37- 57, 22- 52
|
|
[DEBUG] edges: 1, 2, 2: 20- 39- 59, 25- 54
|
|
[DEBUG] edges: 1, 2, 2: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 2, 2: 17- 38- 59, 22- 54
|
|
[DEBUG] edges: 1, 2, 2: 20- 38- 56, 25- 51
|
|
[DEBUG] edges: 1, 2, 2: 18- 39- 60, 23- 55
|
|
[DEBUG] edges: 1, 2, 2: 21- 41- 61, 26- 56
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 2, 2: 25- 43- 62, 30- 57
|
|
[DEBUG] edges: 1, 2, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 2, 2: 24- 43- 63, 29- 58
|
|
[DEBUG] edges: 1, 2, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 2, 2: 23- 41- 59, 28- 54
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 2, 2: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 1, 2, 2: 24- 41- 59, 29- 54
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 2, 2: 23- 41- 59, 28- 54
|
|
[DEBUG] edges: 1, 2, 2: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 1, 2, 2: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 2, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 2, 2: 22- 39- 56, 27- 51
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 2, 2: 19- 38- 57, 24- 52
|
|
[DEBUG] edges: 1, 2, 2: 23- 41- 59, 28- 54
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 2, 2: 25- 44- 63, 30- 58
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 2, 2: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 2, 2: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 2, 2: 23- 42- 62, 28- 57
|
|
[DEBUG] edges: 1, 2, 2: 24- 39- 55, 29- 50
|
|
[DEBUG] edges: 1, 2, 2: 21- 40- 59, 26- 54
|
|
[DEBUG] edges: 1, 2, 2: 24- 42- 61, 29- 56
|
|
[DEBUG] CPA
|
|
[DEBUG] [3100] = 0x00000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 1, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 1, 3, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 1, 3, 0: 15- 39- 63, 28- 50
|
|
[DEBUG] edges: 1, 3, 0: 15- 39- 64, 28- 51
|
|
[DEBUG] edges: 1, 3, 0: 15- 38- 61, 28- 48
|
|
[DEBUG] edges: 1, 3, 0: 15- 38- 62, 28- 49
|
|
[DEBUG] edges: 1, 3, 0: 16- 39- 63, 29- 50
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 3, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 1, 3, 0: 19- 40- 61, 32- 48
|
|
[DEBUG] edges: 1, 3, 0: 19- 41- 64, 32- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 61, 30- 48
|
|
[DEBUG] edges: 1, 3, 0: 16- 37- 58, 29- 45
|
|
[DEBUG] edges: 1, 3, 0: 16- 38- 60, 29- 47
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] edges: 1, 3, 0: 19- 42- 65, 32- 52
|
|
[DEBUG] edges: 1, 3, 0: 19- 41- 63, 32- 50
|
|
[DEBUG] edges: 1, 3, 0: 17- 38- 60, 30- 47
|
|
[DEBUG] edges: 1, 3, 0: 17- 41- 65, 30- 52
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] edges: 1, 3, 0: 16- 39- 62, 29- 49
|
|
[DEBUG] edges: 1, 3, 0: 16- 38- 60, 29- 47
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 3, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 64, 30- 51
|
|
[DEBUG] edges: 1, 3, 0: 17- 39- 62, 30- 49
|
|
[DEBUG] edges: 1, 3, 0: 16- 40- 64, 29- 51
|
|
[DEBUG] edges: 1, 3, 0: 16- 38- 61, 29- 48
|
|
[DEBUG] edges: 1, 3, 0: 15- 37- 59, 28- 46
|
|
[DEBUG] edges: 1, 3, 0: 17- 40- 63, 30- 50
|
|
[DEBUG] [3100] = 0x0c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 3, 1: 20- 40- 61, 25- 56
|
|
[DEBUG] edges: 1, 3, 1: 20- 39- 58, 25- 53
|
|
[DEBUG] edges: 1, 3, 1: 22- 40- 59, 27- 54
|
|
[DEBUG] edges: 1, 3, 1: 21- 40- 59, 26- 54
|
|
[DEBUG] edges: 1, 3, 1: 20- 39- 59, 25- 54
|
|
[DEBUG] edges: 1, 3, 1: 21- 39- 58, 26- 53
|
|
[DEBUG] edges: 1, 3, 1: 21- 39- 57, 26- 52
|
|
[DEBUG] edges: 1, 3, 1: 22- 40- 59, 27- 54
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 3, 1: 24- 43- 63, 29- 58
|
|
[DEBUG] edges: 1, 3, 1: 25- 41- 58, 30- 53
|
|
[DEBUG] edges: 1, 3, 1: 24- 43- 63, 29- 58
|
|
[DEBUG] edges: 1, 3, 1: 22- 40- 58, 27- 53
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] edges: 1, 3, 1: 22- 39- 57, 27- 52
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 55, 28- 50
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 60, 30- 55
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 59, 30- 54
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 59, 30- 54
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 59, 30- 54
|
|
[DEBUG] edges: 1, 3, 1: 24- 40- 56, 29- 51
|
|
[DEBUG] edges: 1, 3, 1: 23- 39- 56, 28- 51
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 3, 1: 23- 42- 61, 28- 56
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 58, 29- 53
|
|
[DEBUG] edges: 1, 3, 1: 25- 42- 60, 30- 55
|
|
[DEBUG] edges: 1, 3, 1: 22- 39- 57, 27- 52
|
|
[DEBUG] edges: 1, 3, 1: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 3, 1: 22- 39- 57, 27- 52
|
|
[DEBUG] edges: 1, 3, 1: 21- 38- 55, 26- 50
|
|
[DEBUG] edges: 1, 3, 1: 23- 42- 61, 28- 56
|
|
[DEBUG] [3100] = 0x2c000000
|
|
[DEBUG] using pattern 0
|
|
[DEBUG] edges: 1, 3, 2: 17- 39- 62, 22- 57
|
|
[DEBUG] edges: 1, 3, 2: 17- 39- 62, 22- 57
|
|
[DEBUG] edges: 1, 3, 2: 20- 40- 60, 25- 55
|
|
[DEBUG] edges: 1, 3, 2: 22- 39- 57, 27- 52
|
|
[DEBUG] edges: 1, 3, 2: 17- 39- 62, 22- 57
|
|
[DEBUG] edges: 1, 3, 2: 19- 38- 58, 24- 53
|
|
[DEBUG] edges: 1, 3, 2: 18- 37- 56, 23- 51
|
|
[DEBUG] edges: 1, 3, 2: 20- 40- 61, 25- 56
|
|
[DEBUG] using pattern 1
|
|
[DEBUG] edges: 1, 3, 2: 23- 42- 61, 28- 56
|
|
[DEBUG] edges: 1, 3, 2: 23- 40- 58, 28- 53
|
|
[DEBUG] edges: 1, 3, 2: 24- 44- 64, 29- 59
|
|
[DEBUG] edges: 1, 3, 2: 24- 42- 60, 29- 55
|
|
[DEBUG] edges: 1, 3, 2: 23- 42- 61, 28- 56
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 2: 21- 38- 56, 26- 51
|
|
[DEBUG] edges: 1, 3, 2: 24- 42- 60, 29- 55
|
|
[DEBUG] using pattern 2
|
|
[DEBUG] edges: 1, 3, 2: 21- 40- 60, 26- 55
|
|
[DEBUG] edges: 1, 3, 2: 22- 42- 62, 27- 57
|
|
[DEBUG] edges: 1, 3, 2: 23- 41- 59, 28- 54
|
|
[DEBUG] edges: 1, 3, 2: 24- 42- 61, 29- 56
|
|
[DEBUG] edges: 1, 3, 2: 23- 41- 60, 28- 55
|
|
[DEBUG] edges: 1, 3, 2: 23- 40- 57, 28- 52
|
|
[DEBUG] edges: 1, 3, 2: 20- 37- 55, 25- 50
|
|
[DEBUG] edges: 1, 3, 2: 23- 41- 60, 28- 55
|
|
[DEBUG] using pattern 3
|
|
[DEBUG] edges: 1, 3, 2: 24- 43- 62, 29- 57
|
|
[DEBUG] edges: 1, 3, 2: 25- 43- 61, 30- 56
|
|
[DEBUG] edges: 1, 3, 2: 25- 44- 64, 30- 59
|
|
[DEBUG] edges: 1, 3, 2: 24- 41- 59, 29- 54
|
|
[DEBUG] edges: 1, 3, 2: 23- 42- 62, 28- 57
|
|
[DEBUG] edges: 1, 3, 2: 24- 40- 57, 29- 52
|
|
[DEBUG] edges: 1, 3, 2: 21- 39- 57, 26- 52
|
|
[DEBUG] edges: 1, 3, 2: 24- 43- 62, 29- 57
|
|
[DEBUG] CPA
|
|
[DEBUG] Aggressive write training:
|
|
[DEBUG] tx_dq: 0, 2, 0: 8- 30- 52, 22- 38
|
|
[DEBUG] tx_dq: 0, 2, 0: 30- 53- 76, 44- 62
|
|
[DEBUG] tx_dq: 0, 2, 0: 61- 85- 109, 75- 95
|
|
[DEBUG] tx_dq: 0, 2, 0: 9- 33- 57, 23- 43
|
|
[DEBUG] tx_dq: 0, 2, 0: 36- 59- 83, 50- 69
|
|
[DEBUG] tx_dq: 0, 2, 0: 48- 70- 92, 62- 78
|
|
[DEBUG] tx_dq: 0, 2, 0: 55- 78- 101, 69- 87
|
|
[DEBUG] tx_dq: 0, 2, 0: 64- 86- 109, 78- 95
|
|
[DEBUG] tx_dq: 0, 3, 0: 2- 25- 48, 16- 34
|
|
[DEBUG] tx_dq: 0, 3, 0: 34- 56- 79, 48- 65
|
|
[DEBUG] tx_dq: 0, 3, 0: 56- 80- 104, 70- 90
|
|
[DEBUG] tx_dq: 0, 3, 0: 14- 38- 62, 28- 48
|
|
[DEBUG] tx_dq: 0, 3, 0: 36- 59- 83, 50- 69
|
|
[DEBUG] tx_dq: 0, 3, 0: 51- 73- 95, 65- 81
|
|
[DEBUG] tx_dq: 0, 3, 0: 57- 80- 103, 71- 89
|
|
[DEBUG] tx_dq: 0, 3, 0: 64- 87- 110, 78- 96
|
|
[DEBUG] tx_dq: 0, 2, 0: 9- 30- 51, 23- 37
|
|
[DEBUG] tx_dq: 0, 2, 0: 29- 52- 75, 43- 61
|
|
[DEBUG] tx_dq: 0, 2, 0: 63- 85- 107, 77- 93
|
|
[DEBUG] tx_dq: 0, 2, 0: 9- 32- 56, 23- 42
|
|
[DEBUG] tx_dq: 0, 2, 0: 37- 59- 82, 51- 68
|
|
[DEBUG] tx_dq: 0, 2, 0: 52- 72- 92, 66- 78
|
|
[DEBUG] tx_dq: 0, 2, 0: 56- 77- 99, 70- 85
|
|
[DEBUG] tx_dq: 0, 2, 0: 63- 85- 108, 77- 94
|
|
[DEBUG] tx_dq: 0, 3, 0: 4- 25- 47, 18- 33
|
|
[DEBUG] tx_dq: 0, 3, 0: 32- 55- 79, 46- 65
|
|
[DEBUG] tx_dq: 0, 3, 0: 56- 79- 103, 70- 89
|
|
[DEBUG] tx_dq: 0, 3, 0: 12- 37- 62, 26- 48
|
|
[DEBUG] tx_dq: 0, 3, 0: 36- 59- 82, 50- 68
|
|
[DEBUG] tx_dq: 0, 3, 0: 53- 73- 94, 67- 80
|
|
[DEBUG] tx_dq: 0, 3, 0: 56- 79- 102, 70- 88
|
|
[DEBUG] tx_dq: 0, 3, 0: 62- 84- 106, 76- 92
|
|
[DEBUG] tx_dq: 0, 2, 0: 7- 29- 51, 21- 37
|
|
[DEBUG] tx_dq: 0, 2, 0: 32- 53- 74, 46- 60
|
|
[DEBUG] tx_dq: 0, 2, 0: 60- 84- 108, 74- 94
|
|
[DEBUG] tx_dq: 0, 2, 0: 8- 32- 56, 22- 42
|
|
[DEBUG] tx_dq: 0, 2, 0: 36- 59- 82, 50- 68
|
|
[DEBUG] tx_dq: 0, 2, 0: 51- 71- 91, 65- 77
|
|
[DEBUG] tx_dq: 0, 2, 0: 56- 77- 99, 70- 85
|
|
[DEBUG] tx_dq: 0, 2, 0: 66- 87- 108, 80- 94
|
|
[DEBUG] tx_dq: 0, 3, 0: 1- 24- 47, 15- 33
|
|
[DEBUG] tx_dq: 0, 3, 0: 34- 56- 79, 48- 65
|
|
[DEBUG] tx_dq: 0, 3, 0: 53- 77- 102, 67- 88
|
|
[DEBUG] tx_dq: 0, 3, 0: 11- 36- 61, 25- 47
|
|
[DEBUG] tx_dq: 0, 3, 0: 35- 58- 82, 49- 68
|
|
[DEBUG] tx_dq: 0, 3, 0: 51- 72- 94, 65- 80
|
|
[DEBUG] tx_dq: 0, 3, 0: 57- 79- 101, 71- 87
|
|
[DEBUG] tx_dq: 0, 3, 0: 65- 85- 106, 79- 92
|
|
[DEBUG] tx_dq: 0, 2, 0: 8- 30- 52, 22- 38
|
|
[DEBUG] tx_dq: 0, 2, 0: 33- 53- 74, 47- 60
|
|
[DEBUG] tx_dq: 0, 2, 0: 63- 85- 108, 77- 94
|
|
[DEBUG] tx_dq: 0, 2, 0: 10- 33- 56, 24- 42
|
|
[DEBUG] tx_dq: 0, 2, 0: 36- 59- 82, 50- 68
|
|
[DEBUG] tx_dq: 0, 2, 0: 48- 70- 92, 62- 78
|
|
[DEBUG] tx_dq: 0, 2, 0: 56- 77- 99, 70- 85
|
|
[DEBUG] tx_dq: 0, 2, 0: 63- 86- 109, 77- 95
|
|
[DEBUG] tx_dq: 0, 3, 0: 2- 24- 47, 16- 33
|
|
[DEBUG] tx_dq: 0, 3, 0: 36- 57- 78, 50- 64
|
|
[DEBUG] tx_dq: 0, 3, 0: 56- 79- 103, 70- 89
|
|
[DEBUG] tx_dq: 0, 3, 0: 15- 38- 62, 29- 48
|
|
[DEBUG] tx_dq: 0, 3, 0: 35- 58- 82, 49- 68
|
|
[DEBUG] tx_dq: 0, 3, 0: 49- 72- 95, 63- 81
|
|
[DEBUG] tx_dq: 0, 3, 0: 57- 79- 102, 71- 88
|
|
[DEBUG] tx_dq: 0, 3, 0: 60- 84- 108, 74- 94
|
|
[DEBUG] tx_dq: 1, 2, 0: 9- 30- 51, 23- 37
|
|
[DEBUG] tx_dq: 1, 2, 0: 26- 46- 66, 40- 52
|
|
[DEBUG] tx_dq: 1, 2, 0: 57- 78- 100, 71- 86
|
|
[DEBUG] tx_dq: 1, 2, 0: 9- 32- 55, 23- 41
|
|
[DEBUG] tx_dq: 1, 2, 0: 33- 54- 75, 47- 61
|
|
[DEBUG] tx_dq: 1, 2, 0: 48- 68- 89, 62- 75
|
|
[DEBUG] tx_dq: 1, 2, 0: 48- 68- 89, 62- 75
|
|
[DEBUG] tx_dq: 1, 2, 0: 65- 85- 106, 79- 92
|
|
[DEBUG] tx_dq: 1, 3, 0: 7- 27- 48, 21- 34
|
|
[DEBUG] tx_dq: 1, 3, 0: 33- 53- 73, 47- 59
|
|
[DEBUG] tx_dq: 1, 3, 0: 63- 84- 105, 77- 91
|
|
[DEBUG] tx_dq: 1, 3, 0: 8- 30- 53, 22- 39
|
|
[DEBUG] tx_dq: 1, 3, 0: 38- 59- 80, 52- 66
|
|
[DEBUG] tx_dq: 1, 3, 0: 52- 72- 93, 66- 79
|
|
[DEBUG] tx_dq: 1, 3, 0: 57- 79- 102, 71- 88
|
|
[DEBUG] tx_dq: 1, 3, 0: 7- 28- 50, 21- 36
|
|
[DEBUG] tx_dq: 1, 2, 0: 10- 30- 50, 24- 36
|
|
[DEBUG] tx_dq: 1, 2, 0: 29- 46- 64, 43- 50
|
|
[DEBUG] tx_dq: 1, 2, 0: 56- 77- 98, 70- 84
|
|
[DEBUG] tx_dq: 1, 2, 0: 11- 32- 54, 25- 40
|
|
[DEBUG] tx_dq: 1, 2, 0: 35- 55- 76, 49- 62
|
|
[DEBUG] tx_dq: 1, 2, 0: 51- 70- 89, 65- 75
|
|
[DEBUG] tx_dq: 1, 2, 0: 50- 69- 88, 64- 74
|
|
[DEBUG] tx_dq: 1, 2, 0: 69- 87- 106, 83- 92
|
|
[DEBUG] tx_dq: 1, 3, 0: 6- 26- 47, 20- 33
|
|
[DEBUG] tx_dq: 1, 3, 0: 34- 53- 72, 48- 58
|
|
[DEBUG] tx_dq: 1, 3, 0: 60- 81- 103, 74- 89
|
|
[DEBUG] tx_dq: 1, 3, 0: 7- 29- 52, 21- 38
|
|
[DEBUG] tx_dq: 1, 3, 0: 39- 60- 81, 53- 67
|
|
[DEBUG] tx_dq: 1, 3, 0: 53- 73- 94, 67- 80
|
|
[DEBUG] tx_dq: 1, 3, 0: 59- 80- 102, 73- 88
|
|
[DEBUG] tx_dq: 1, 3, 0: 8- 28- 48, 22- 34
|
|
[DEBUG] tx_dq: 1, 2, 0: 13- 32- 51, 27- 37
|
|
[DEBUG] tx_dq: 1, 2, 0: 25- 45- 66, 39- 52
|
|
[DEBUG] tx_dq: 1, 2, 0: 57- 78- 99, 71- 85
|
|
[DEBUG] tx_dq: 1, 2, 0: 8- 31- 54, 22- 40
|
|
[DEBUG] tx_dq: 1, 2, 0: 34- 55- 76, 48- 62
|
|
[DEBUG] tx_dq: 1, 2, 0: 48- 68- 88, 62- 74
|
|
[DEBUG] tx_dq: 1, 2, 0: 49- 69- 89, 63- 75
|
|
[DEBUG] tx_dq: 1, 2, 0: 66- 86- 106, 80- 92
|
|
[DEBUG] tx_dq: 1, 3, 0: 9- 28- 48, 23- 34
|
|
[DEBUG] tx_dq: 1, 3, 0: 31- 52- 73, 45- 59
|
|
[DEBUG] tx_dq: 1, 3, 0: 61- 82- 104, 75- 90
|
|
[DEBUG] tx_dq: 1, 3, 0: 5- 27- 50, 19- 36
|
|
[DEBUG] tx_dq: 1, 3, 0: 38- 59- 80, 52- 66
|
|
[DEBUG] tx_dq: 1, 3, 0: 53- 73- 94, 67- 80
|
|
[DEBUG] tx_dq: 1, 3, 0: 58- 80- 102, 72- 88
|
|
[DEBUG] tx_dq: 1, 3, 0: 4- 26- 48, 18- 34
|
|
[DEBUG] tx_dq: 1, 2, 0: 10- 30- 51, 24- 37
|
|
[DEBUG] tx_dq: 1, 2, 0: 27- 46- 66, 41- 52
|
|
[DEBUG] tx_dq: 1, 2, 0: 59- 78- 98, 73- 84
|
|
[DEBUG] tx_dq: 1, 2, 0: 10- 32- 54, 24- 40
|
|
[DEBUG] tx_dq: 1, 2, 0: 33- 54- 76, 47- 62
|
|
[DEBUG] tx_dq: 1, 2, 0: 52- 70- 88, 66- 74
|
|
[DEBUG] tx_dq: 1, 2, 0: 48- 68- 89, 62- 75
|
|
[DEBUG] tx_dq: 1, 2, 0: 64- 85- 106, 78- 92
|
|
[DEBUG] tx_dq: 1, 3, 0: 8- 27- 47, 22- 33
|
|
[DEBUG] tx_dq: 1, 3, 0: 33- 53- 73, 47- 59
|
|
[DEBUG] tx_dq: 1, 3, 0: 64- 83- 102, 78- 88
|
|
[DEBUG] tx_dq: 1, 3, 0: 9- 30- 51, 23- 37
|
|
[DEBUG] tx_dq: 1, 3, 0: 39- 59- 80, 53- 66
|
|
[DEBUG] tx_dq: 1, 3, 0: 56- 75- 94, 70- 80
|
|
[DEBUG] tx_dq: 1, 3, 0: 56- 79- 103, 70- 89
|
|
[DEBUG] tx_dq: 1, 3, 0: 5- 26- 48, 19- 34
|
|
[DEBUG] tx_dq: 0, 2, 1: 10- 29- 48, 15- 43
|
|
[DEBUG] tx_dq: 0, 2, 1: 34- 52- 71, 39- 66
|
|
[DEBUG] tx_dq: 0, 2, 1: 65- 84- 103, 70- 98
|
|
[DEBUG] tx_dq: 0, 2, 1: 14- 33- 53, 19- 48
|
|
[DEBUG] tx_dq: 0, 2, 1: 40- 59- 79, 45- 74
|
|
[DEBUG] tx_dq: 0, 2, 1: 53- 70- 87, 58- 82
|
|
[DEBUG] tx_dq: 0, 2, 1: 58- 77- 96, 63- 91
|
|
[DEBUG] tx_dq: 0, 2, 1: 67- 85- 104, 72- 99
|
|
[DEBUG] tx_dq: 0, 3, 1: 6- 25- 45, 11- 40
|
|
[DEBUG] tx_dq: 0, 3, 1: 38- 56- 74, 43- 69
|
|
[DEBUG] tx_dq: 0, 3, 1: 60- 79- 99, 65- 94
|
|
[DEBUG] tx_dq: 0, 3, 1: 18- 37- 57, 23- 52
|
|
[DEBUG] tx_dq: 0, 3, 1: 40- 59- 79, 45- 74
|
|
[DEBUG] tx_dq: 0, 3, 1: 55- 72- 89, 60- 84
|
|
[DEBUG] tx_dq: 0, 3, 1: 62- 80- 98, 67- 93
|
|
[DEBUG] tx_dq: 0, 3, 1: 67- 85- 104, 72- 99
|
|
[DEBUG] tx_dq: 0, 2, 1: 12- 29- 47, 17- 42
|
|
[DEBUG] tx_dq: 0, 2, 1: 33- 52- 71, 38- 66
|
|
[DEBUG] tx_dq: 0, 2, 1: 66- 84- 103, 71- 98
|
|
[DEBUG] tx_dq: 0, 2, 1: 15- 33- 52, 20- 47
|
|
[DEBUG] tx_dq: 0, 2, 1: 41- 59- 78, 46- 73
|
|
[DEBUG] tx_dq: 0, 2, 1: 56- 71- 87, 61- 82
|
|
[DEBUG] tx_dq: 0, 2, 1: 59- 77- 95, 64- 90
|
|
[DEBUG] tx_dq: 0, 2, 1: 67- 85- 103, 72- 98
|
|
[DEBUG] tx_dq: 0, 3, 1: 8- 25- 43, 13- 38
|
|
[DEBUG] tx_dq: 0, 3, 1: 36- 54- 73, 41- 68
|
|
[DEBUG] tx_dq: 0, 3, 1: 61- 80- 99, 66- 94
|
|
[DEBUG] tx_dq: 0, 3, 1: 17- 36- 56, 22- 51
|
|
[DEBUG] tx_dq: 0, 3, 1: 41- 59- 78, 46- 73
|
|
[DEBUG] tx_dq: 0, 3, 1: 57- 72- 88, 62- 83
|
|
[DEBUG] tx_dq: 0, 3, 1: 60- 78- 96, 65- 91
|
|
[DEBUG] tx_dq: 0, 3, 1: 66- 84- 103, 71- 98
|
|
[DEBUG] tx_dq: 0, 2, 1: 11- 29- 47, 16- 42
|
|
[DEBUG] tx_dq: 0, 2, 1: 36- 53- 71, 41- 66
|
|
[DEBUG] tx_dq: 0, 2, 1: 65- 84- 103, 70- 98
|
|
[DEBUG] tx_dq: 0, 2, 1: 13- 33- 53, 18- 48
|
|
[DEBUG] tx_dq: 0, 2, 1: 41- 59- 78, 46- 73
|
|
[DEBUG] tx_dq: 0, 2, 1: 56- 71- 87, 61- 82
|
|
[DEBUG] tx_dq: 0, 2, 1: 61- 77- 93, 66- 88
|
|
[DEBUG] tx_dq: 0, 2, 1: 71- 87- 103, 76- 98
|
|
[DEBUG] tx_dq: 0, 3, 1: 4- 22- 41, 9- 36
|
|
[DEBUG] tx_dq: 0, 3, 1: 39- 55- 72, 44- 67
|
|
[DEBUG] tx_dq: 0, 3, 1: 58- 78- 98, 63- 93
|
|
[DEBUG] tx_dq: 0, 3, 1: 16- 36- 56, 21- 51
|
|
[DEBUG] tx_dq: 0, 3, 1: 40- 59- 78, 45- 73
|
|
[DEBUG] tx_dq: 0, 3, 1: 56- 71- 87, 61- 82
|
|
[DEBUG] tx_dq: 0, 3, 1: 61- 78- 95, 66- 90
|
|
[DEBUG] tx_dq: 0, 3, 1: 69- 85- 101, 74- 96
|
|
[DEBUG] tx_dq: 0, 2, 1: 12- 29- 47, 17- 42
|
|
[DEBUG] tx_dq: 0, 2, 1: 38- 54- 71, 43- 66
|
|
[DEBUG] tx_dq: 0, 2, 1: 68- 86- 104, 73- 99
|
|
[DEBUG] tx_dq: 0, 2, 1: 15- 34- 53, 20- 48
|
|
[DEBUG] tx_dq: 0, 2, 1: 40- 59- 78, 45- 73
|
|
[DEBUG] tx_dq: 0, 2, 1: 52- 69- 87, 57- 82
|
|
[DEBUG] tx_dq: 0, 2, 1: 60- 77- 94, 65- 89
|
|
[DEBUG] tx_dq: 0, 2, 1: 67- 85- 103, 72- 98
|
|
[DEBUG] tx_dq: 0, 3, 1: 6- 24- 42, 11- 37
|
|
[DEBUG] tx_dq: 0, 3, 1: 40- 56- 73, 45- 68
|
|
[DEBUG] tx_dq: 0, 3, 1: 61- 80- 99, 66- 94
|
|
[DEBUG] tx_dq: 0, 3, 1: 19- 37- 56, 24- 51
|
|
[DEBUG] tx_dq: 0, 3, 1: 40- 59- 78, 45- 73
|
|
[DEBUG] tx_dq: 0, 3, 1: 54- 71- 88, 59- 83
|
|
[DEBUG] tx_dq: 0, 3, 1: 61- 78- 96, 66- 91
|
|
[DEBUG] tx_dq: 0, 3, 1: 65- 84- 103, 70- 98
|
|
[DEBUG] tx_dq: 1, 2, 1: 13- 30- 47, 18- 42
|
|
[DEBUG] tx_dq: 1, 2, 1: 31- 47- 63, 36- 58
|
|
[DEBUG] tx_dq: 1, 2, 1: 61- 78- 95, 66- 90
|
|
[DEBUG] tx_dq: 1, 2, 1: 13- 31- 50, 18- 45
|
|
[DEBUG] tx_dq: 1, 2, 1: 38- 54- 71, 43- 66
|
|
[DEBUG] tx_dq: 1, 2, 1: 51- 68- 86, 56- 81
|
|
[DEBUG] tx_dq: 1, 2, 1: 50- 67- 84, 55- 79
|
|
[DEBUG] tx_dq: 1, 2, 1: 69- 85- 102, 74- 97
|
|
[DEBUG] tx_dq: 1, 3, 1: 11- 27- 44, 16- 39
|
|
[DEBUG] tx_dq: 1, 3, 1: 38- 54- 71, 43- 66
|
|
[DEBUG] tx_dq: 1, 3, 1: 66- 83- 100, 71- 95
|
|
[DEBUG] tx_dq: 1, 3, 1: 12- 29- 47, 17- 42
|
|
[DEBUG] tx_dq: 1, 3, 1: 42- 58- 75, 47- 70
|
|
[DEBUG] tx_dq: 1, 3, 1: 56- 72- 88, 61- 83
|
|
[DEBUG] tx_dq: 1, 3, 1: 63- 80- 97, 68- 92
|
|
[DEBUG] tx_dq: 1, 3, 1: 10- 28- 46, 15- 41
|
|
[DEBUG] tx_dq: 1, 2, 1: 14- 30- 46, 19- 41
|
|
[DEBUG] tx_dq: 1, 2, 1: 33- 46- 60, 38- 55
|
|
[DEBUG] tx_dq: 1, 2, 1: 60- 77- 94, 65- 89
|
|
[DEBUG] tx_dq: 1, 2, 1: 16- 32- 48, 21- 43
|
|
[DEBUG] tx_dq: 1, 2, 1: 40- 56- 72, 45- 67
|
|
[DEBUG] tx_dq: 1, 2, 1: 56- 69- 83, 61- 78
|
|
[DEBUG] tx_dq: 1, 2, 1: 56- 69- 83, 61- 78
|
|
[DEBUG] tx_dq: 1, 2, 1: 73- 87- 102, 78- 97
|
|
[DEBUG] tx_dq: 1, 3, 1: 10- 26- 43, 15- 38
|
|
[DEBUG] tx_dq: 1, 3, 1: 39- 53- 67, 44- 62
|
|
[DEBUG] tx_dq: 1, 3, 1: 64- 80- 97, 69- 92
|
|
[DEBUG] tx_dq: 1, 3, 1: 11- 29- 47, 16- 42
|
|
[DEBUG] tx_dq: 1, 3, 1: 43- 59- 75, 48- 70
|
|
[DEBUG] tx_dq: 1, 3, 1: 57- 72- 87, 62- 82
|
|
[DEBUG] tx_dq: 1, 3, 1: 64- 80- 96, 69- 91
|
|
[DEBUG] tx_dq: 1, 3, 1: 12- 27- 43, 17- 38
|
|
[DEBUG] tx_dq: 1, 2, 1: 17- 31- 46, 22- 41
|
|
[DEBUG] tx_dq: 1, 2, 1: 30- 46- 62, 35- 57
|
|
[DEBUG] tx_dq: 1, 2, 1: 62- 78- 94, 67- 89
|
|
[DEBUG] tx_dq: 1, 2, 1: 13- 30- 47, 18- 42
|
|
[DEBUG] tx_dq: 1, 2, 1: 40- 55- 71, 45- 66
|
|
[DEBUG] tx_dq: 1, 2, 1: 51- 67- 84, 56- 79
|
|
[DEBUG] tx_dq: 1, 2, 1: 54- 68- 83, 59- 78
|
|
[DEBUG] tx_dq: 1, 2, 1: 71- 86- 102, 76- 97
|
|
[DEBUG] tx_dq: 1, 3, 1: 13- 27- 42, 18- 37
|
|
[DEBUG] tx_dq: 1, 3, 1: 34- 50- 67, 39- 62
|
|
[DEBUG] tx_dq: 1, 3, 1: 65- 81- 98, 70- 93
|
|
[DEBUG] tx_dq: 1, 3, 1: 9- 27- 45, 14- 40
|
|
[DEBUG] tx_dq: 1, 3, 1: 41- 58- 75, 46- 70
|
|
[DEBUG] tx_dq: 1, 3, 1: 57- 71- 86, 62- 81
|
|
[DEBUG] tx_dq: 1, 3, 1: 63- 79- 96, 68- 91
|
|
[DEBUG] tx_dq: 1, 3, 1: 9- 26- 43, 14- 38
|
|
[DEBUG] tx_dq: 1, 2, 1: 14- 29- 45, 19- 40
|
|
[DEBUG] tx_dq: 1, 2, 1: 32- 47- 63, 37- 58
|
|
[DEBUG] tx_dq: 1, 2, 1: 63- 78- 93, 68- 88
|
|
[DEBUG] tx_dq: 1, 2, 1: 15- 31- 48, 20- 43
|
|
[DEBUG] tx_dq: 1, 2, 1: 39- 55- 71, 44- 66
|
|
[DEBUG] tx_dq: 1, 2, 1: 56- 69- 82, 61- 77
|
|
[DEBUG] tx_dq: 1, 2, 1: 51- 67- 83, 56- 78
|
|
[DEBUG] tx_dq: 1, 2, 1: 69- 85- 102, 74- 97
|
|
[DEBUG] tx_dq: 1, 3, 1: 11- 26- 41, 16- 36
|
|
[DEBUG] tx_dq: 1, 3, 1: 38- 53- 69, 43- 64
|
|
[DEBUG] tx_dq: 1, 3, 1: 66- 80- 95, 71- 90
|
|
[DEBUG] tx_dq: 1, 3, 1: 15- 30- 46, 20- 41
|
|
[DEBUG] tx_dq: 1, 3, 1: 42- 58- 75, 47- 70
|
|
[DEBUG] tx_dq: 1, 3, 1: 59- 73- 87, 64- 82
|
|
[DEBUG] tx_dq: 1, 3, 1: 60- 78- 97, 65- 92
|
|
[DEBUG] tx_dq: 1, 3, 1: 9- 26- 43, 14- 38
|
|
[DEBUG] tx_dq: 0, 2, 2: 6- 27- 48, 11- 43
|
|
[DEBUG] tx_dq: 0, 2, 2: 29- 50- 71, 34- 66
|
|
[DEBUG] tx_dq: 0, 2, 2: 60- 82- 104, 65- 99
|
|
[DEBUG] tx_dq: 0, 2, 2: 8- 30- 52, 13- 47
|
|
[DEBUG] tx_dq: 0, 2, 2: 37- 57- 78, 42- 73
|
|
[DEBUG] tx_dq: 0, 2, 2: 49- 68- 87, 54- 82
|
|
[DEBUG] tx_dq: 0, 2, 2: 55- 75- 95, 60- 90
|
|
[DEBUG] tx_dq: 0, 2, 2: 63- 82- 102, 68- 97
|
|
[DEBUG] tx_dq: 0, 3, 2: 4- 23- 43, 9- 38
|
|
[DEBUG] tx_dq: 0, 3, 2: 34- 53- 72, 39- 67
|
|
[DEBUG] tx_dq: 0, 3, 2: 57- 78- 99, 62- 94
|
|
[DEBUG] tx_dq: 0, 3, 2: 14- 35- 56, 19- 51
|
|
[DEBUG] tx_dq: 0, 3, 2: 38- 57- 77, 43- 72
|
|
[DEBUG] tx_dq: 0, 3, 2: 50- 69- 88, 55- 83
|
|
[DEBUG] tx_dq: 0, 3, 2: 57- 77- 97, 62- 92
|
|
[DEBUG] tx_dq: 0, 3, 2: 62- 82- 103, 67- 98
|
|
[DEBUG] tx_dq: 0, 2, 2: 9- 27- 45, 14- 40
|
|
[DEBUG] tx_dq: 0, 2, 2: 29- 48- 68, 34- 63
|
|
[DEBUG] tx_dq: 0, 2, 2: 61- 82- 103, 66- 98
|
|
[DEBUG] tx_dq: 0, 2, 2: 10- 30- 51, 15- 46
|
|
[DEBUG] tx_dq: 0, 2, 2: 38- 57- 77, 43- 72
|
|
[DEBUG] tx_dq: 0, 2, 2: 51- 68- 86, 56- 81
|
|
[DEBUG] tx_dq: 0, 2, 2: 56- 74- 93, 61- 88
|
|
[DEBUG] tx_dq: 0, 2, 2: 63- 82- 102, 68- 97
|
|
[DEBUG] tx_dq: 0, 3, 2: 3- 21- 40, 8- 35
|
|
[DEBUG] tx_dq: 0, 3, 2: 32- 51- 71, 37- 66
|
|
[DEBUG] tx_dq: 0, 3, 2: 56- 76- 97, 61- 92
|
|
[DEBUG] tx_dq: 0, 3, 2: 13- 34- 56, 18- 51
|
|
[DEBUG] tx_dq: 0, 3, 2: 38- 57- 77, 43- 72
|
|
[DEBUG] tx_dq: 0, 3, 2: 52- 69- 87, 57- 82
|
|
[DEBUG] tx_dq: 0, 3, 2: 56- 75- 95, 61- 90
|
|
[DEBUG] tx_dq: 0, 3, 2: 63- 81- 100, 68- 95
|
|
[DEBUG] tx_dq: 0, 2, 2: 8- 27- 47, 13- 42
|
|
[DEBUG] tx_dq: 0, 2, 2: 33- 50- 68, 38- 63
|
|
[DEBUG] tx_dq: 0, 2, 2: 61- 82- 103, 66- 98
|
|
[DEBUG] tx_dq: 0, 2, 2: 9- 30- 52, 14- 47
|
|
[DEBUG] tx_dq: 0, 2, 2: 37- 57- 77, 42- 72
|
|
[DEBUG] tx_dq: 0, 2, 2: 51- 68- 86, 56- 81
|
|
[DEBUG] tx_dq: 0, 2, 2: 56- 74- 93, 61- 88
|
|
[DEBUG] tx_dq: 0, 2, 2: 66- 84- 102, 71- 97
|
|
[DEBUG] tx_dq: 0, 3, 2: 2- 21- 41, 7- 36
|
|
[DEBUG] tx_dq: 0, 3, 2: 35- 53- 71, 40- 66
|
|
[DEBUG] tx_dq: 0, 3, 2: 56- 76- 97, 61- 92
|
|
[DEBUG] tx_dq: 0, 3, 2: 13- 35- 57, 18- 52
|
|
[DEBUG] tx_dq: 0, 3, 2: 36- 56- 76, 41- 71
|
|
[DEBUG] tx_dq: 0, 3, 2: 52- 69- 87, 57- 82
|
|
[DEBUG] tx_dq: 0, 3, 2: 57- 76- 95, 62- 90
|
|
[DEBUG] tx_dq: 0, 3, 2: 64- 82- 101, 69- 96
|
|
[DEBUG] tx_dq: 0, 2, 2: 8- 27- 46, 13- 41
|
|
[DEBUG] tx_dq: 0, 2, 2: 32- 49- 67, 37- 62
|
|
[DEBUG] tx_dq: 0, 2, 2: 63- 83- 103, 68- 98
|
|
[DEBUG] tx_dq: 0, 2, 2: 12- 32- 52, 17- 47
|
|
[DEBUG] tx_dq: 0, 2, 2: 37- 57- 77, 42- 72
|
|
[DEBUG] tx_dq: 0, 2, 2: 48- 67- 86, 53- 81
|
|
[DEBUG] tx_dq: 0, 2, 2: 56- 74- 93, 61- 88
|
|
[DEBUG] tx_dq: 0, 2, 2: 64- 83- 103, 69- 98
|
|
[DEBUG] tx_dq: 0, 3, 2: 3- 22- 41, 8- 36
|
|
[DEBUG] tx_dq: 0, 3, 2: 36- 53- 71, 41- 66
|
|
[DEBUG] tx_dq: 0, 3, 2: 57- 77- 97, 62- 92
|
|
[DEBUG] tx_dq: 0, 3, 2: 16- 36- 56, 21- 51
|
|
[DEBUG] tx_dq: 0, 3, 2: 37- 57- 77, 42- 72
|
|
[DEBUG] tx_dq: 0, 3, 2: 50- 68- 87, 55- 82
|
|
[DEBUG] tx_dq: 0, 3, 2: 56- 76- 96, 61- 91
|
|
[DEBUG] tx_dq: 0, 3, 2: 62- 81- 101, 67- 96
|
|
[DEBUG] tx_dq: 1, 2, 2: 8- 26- 45, 13- 40
|
|
[DEBUG] tx_dq: 1, 2, 2: 26- 42- 59, 31- 54
|
|
[DEBUG] tx_dq: 1, 2, 2: 58- 76- 95, 63- 90
|
|
[DEBUG] tx_dq: 1, 2, 2: 7- 28- 50, 12- 45
|
|
[DEBUG] tx_dq: 1, 2, 2: 34- 51- 69, 39- 64
|
|
[DEBUG] tx_dq: 1, 2, 2: 50- 65- 81, 55- 76
|
|
[DEBUG] tx_dq: 1, 2, 2: 48- 65- 83, 53- 78
|
|
[DEBUG] tx_dq: 1, 2, 2: 65- 82- 100, 70- 95
|
|
[DEBUG] tx_dq: 1, 3, 2: 8- 25- 42, 13- 37
|
|
[DEBUG] tx_dq: 1, 3, 2: 34- 49- 65, 39- 60
|
|
[DEBUG] tx_dq: 1, 3, 2: 64- 80- 97, 69- 92
|
|
[DEBUG] tx_dq: 1, 3, 2: 8- 27- 47, 13- 42
|
|
[DEBUG] tx_dq: 1, 3, 2: 39- 56- 73, 44- 68
|
|
[DEBUG] tx_dq: 1, 3, 2: 51- 68- 86, 56- 81
|
|
[DEBUG] tx_dq: 1, 3, 2: 58- 76- 95, 63- 90
|
|
[DEBUG] tx_dq: 1, 3, 2: 5- 25- 45, 10- 40
|
|
[DEBUG] tx_dq: 1, 2, 2: 9- 26- 43, 14- 38
|
|
[DEBUG] tx_dq: 1, 2, 2: 28- 43- 58, 33- 53
|
|
[DEBUG] tx_dq: 1, 2, 2: 55- 73- 92, 60- 87
|
|
[DEBUG] tx_dq: 1, 2, 2: 8- 27- 47, 13- 42
|
|
[DEBUG] tx_dq: 1, 2, 2: 35- 51- 68, 40- 63
|
|
[DEBUG] tx_dq: 1, 2, 2: 50- 65- 81, 55- 76
|
|
[DEBUG] tx_dq: 1, 2, 2: 50- 66- 83, 55- 78
|
|
[DEBUG] tx_dq: 1, 2, 2: 68- 83- 99, 73- 94
|
|
[DEBUG] tx_dq: 1, 3, 2: 5- 22- 40, 10- 35
|
|
[DEBUG] tx_dq: 1, 3, 2: 33- 48- 63, 38- 58
|
|
[DEBUG] tx_dq: 1, 3, 2: 59- 77- 95, 64- 90
|
|
[DEBUG] tx_dq: 1, 3, 2: 6- 26- 46, 11- 41
|
|
[DEBUG] tx_dq: 1, 3, 2: 39- 55- 72, 44- 67
|
|
[DEBUG] tx_dq: 1, 3, 2: 51- 67- 84, 56- 79
|
|
[DEBUG] tx_dq: 1, 3, 2: 58- 76- 95, 63- 90
|
|
[DEBUG] tx_dq: 1, 3, 2: 6- 24- 42, 11- 37
|
|
[DEBUG] tx_dq: 1, 2, 2: 11- 27- 43, 16- 38
|
|
[DEBUG] tx_dq: 1, 2, 2: 27- 42- 58, 32- 53
|
|
[DEBUG] tx_dq: 1, 2, 2: 59- 75- 92, 64- 87
|
|
[DEBUG] tx_dq: 1, 2, 2: 8- 27- 47, 13- 42
|
|
[DEBUG] tx_dq: 1, 2, 2: 35- 52- 69, 40- 64
|
|
[DEBUG] tx_dq: 1, 2, 2: 49- 64- 80, 54- 75
|
|
[DEBUG] tx_dq: 1, 2, 2: 48- 65- 83, 53- 78
|
|
[DEBUG] tx_dq: 1, 2, 2: 67- 83- 99, 72- 94
|
|
[DEBUG] tx_dq: 1, 3, 2: 9- 24- 40, 14- 35
|
|
[DEBUG] tx_dq: 1, 3, 2: 32- 48- 64, 37- 59
|
|
[DEBUG] tx_dq: 1, 3, 2: 63- 79- 96, 68- 91
|
|
[DEBUG] tx_dq: 1, 3, 2: 5- 25- 45, 10- 40
|
|
[DEBUG] tx_dq: 1, 3, 2: 38- 55- 73, 43- 68
|
|
[DEBUG] tx_dq: 1, 3, 2: 53- 68- 84, 58- 79
|
|
[DEBUG] tx_dq: 1, 3, 2: 57- 75- 94, 62- 89
|
|
[DEBUG] tx_dq: 1, 3, 2: 4- 23- 43, 9- 38
|
|
[DEBUG] tx_dq: 1, 2, 2: 9- 26- 44, 14- 39
|
|
[DEBUG] tx_dq: 1, 2, 2: 28- 43- 59, 33- 54
|
|
[DEBUG] tx_dq: 1, 2, 2: 58- 75- 92, 63- 87
|
|
[DEBUG] tx_dq: 1, 2, 2: 8- 27- 47, 13- 42
|
|
[DEBUG] tx_dq: 1, 2, 2: 34- 51- 69, 39- 64
|
|
[DEBUG] tx_dq: 1, 2, 2: 54- 67- 81, 59- 76
|
|
[DEBUG] tx_dq: 1, 2, 2: 47- 64- 82, 52- 77
|
|
[DEBUG] tx_dq: 1, 2, 2: 66- 82- 99, 71- 94
|
|
[DEBUG] tx_dq: 1, 3, 2: 7- 23- 40, 12- 35
|
|
[DEBUG] tx_dq: 1, 3, 2: 33- 49- 65, 38- 60
|
|
[DEBUG] tx_dq: 1, 3, 2: 62- 78- 95, 67- 90
|
|
[DEBUG] tx_dq: 1, 3, 2: 8- 26- 44, 13- 39
|
|
[DEBUG] tx_dq: 1, 3, 2: 39- 56- 73, 44- 68
|
|
[DEBUG] tx_dq: 1, 3, 2: 55- 70- 85, 60- 80
|
|
[DEBUG] tx_dq: 1, 3, 2: 56- 75- 95, 61- 90
|
|
[DEBUG] tx_dq: 1, 3, 2: 6- 25- 44, 11- 39
|
|
[DEBUG] CPB
|
|
[DEBUG] tx_dq 0, 2, 0: 30
|
|
[DEBUG] tx_dq 0, 2, 1: 53
|
|
[DEBUG] tx_dq 0, 2, 2: 85
|
|
[DEBUG] tx_dq 0, 2, 3: 33
|
|
[DEBUG] tx_dq 0, 2, 4: 59
|
|
[DEBUG] tx_dq 0, 2, 5: 71
|
|
[DEBUG] tx_dq 0, 2, 6: 77
|
|
[DEBUG] tx_dq 0, 2, 7: 87
|
|
[DEBUG] tx_dq 0, 3, 0: 25
|
|
[DEBUG] tx_dq 0, 3, 1: 57
|
|
[DEBUG] tx_dq 0, 3, 2: 79
|
|
[DEBUG] tx_dq 0, 3, 3: 38
|
|
[DEBUG] tx_dq 0, 3, 4: 59
|
|
[DEBUG] tx_dq 0, 3, 5: 73
|
|
[DEBUG] tx_dq 0, 3, 6: 79
|
|
[DEBUG] tx_dq 0, 3, 7: 85
|
|
[DEBUG] tx_dq 1, 2, 0: 31
|
|
[DEBUG] tx_dq 1, 2, 1: 46
|
|
[DEBUG] tx_dq 1, 2, 2: 78
|
|
[DEBUG] tx_dq 1, 2, 3: 32
|
|
[DEBUG] tx_dq 1, 2, 4: 55
|
|
[DEBUG] tx_dq 1, 2, 5: 70
|
|
[DEBUG] tx_dq 1, 2, 6: 69
|
|
[DEBUG] tx_dq 1, 2, 7: 87
|
|
[DEBUG] tx_dq 1, 3, 0: 28
|
|
[DEBUG] tx_dq 1, 3, 1: 53
|
|
[DEBUG] tx_dq 1, 3, 2: 83
|
|
[DEBUG] tx_dq 1, 3, 3: 29
|
|
[DEBUG] tx_dq 1, 3, 4: 59
|
|
[DEBUG] tx_dq 1, 3, 5: 74
|
|
[DEBUG] tx_dq 1, 3, 6: 80
|
|
[DEBUG] tx_dq 1, 3, 7: 28
|
|
[DEBUG] normalize 0, 2, 8: mat 142
|
|
[DEBUG] normalize 0, 2, 8: delta -5
|
|
[DEBUG] normalize 0, 3, 8: mat 144
|
|
[DEBUG] normalize 0, 3, 8: delta -5
|
|
[DEBUG] normalize 1, 2, 8: mat 179
|
|
[DEBUG] normalize 1, 2, 8: delta -5
|
|
[DEBUG] normalize 1, 3, 8: mat 177
|
|
[DEBUG] normalize 1, 3, 8: delta -5
|
|
[DEBUG] OTHP [400c] = 58b4
|
|
[DEBUG] OTHP [440c] = 58b4
|
|
[DEBUG] t123: 1767, 6000, 6120
|
|
[NOTE ] ME: FWS2: 0x161f0126
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x3
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x1
|
|
[NOTE ] ME: MFS failure : 0x0
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x1f
|
|
[NOTE ] ME: Current PM event: 0x6
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[INFO ] Timestamp - waiting for ME acknowledgment of raminit: 30716602488
|
|
[INFO ] Timestamp - finished waiting for ME response: 30741789510
|
|
[NOTE ] ME: FWS2: 0x16500126
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x3
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x1
|
|
[NOTE ] ME: MFS failure : 0x0
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x50
|
|
[NOTE ] ME: Current PM event: 0x6
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: Continue to boot
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : NO
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Normal
|
|
[DEBUG] ME: Current Operation State : M0 with UMA
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : uKernel Phase
|
|
[DEBUG] ME: Power Management Event : Pseudo-global reset
|
|
[DEBUG] ME: Progress Phase State : Unknown 0x00
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1596 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00630020):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 8192 MB width x8 dual rank
|
|
[DEBUG] DIMMB 0 MB width x8 single rank, selected
|
|
[DEBUG] memcfg channel[1] config (00630020):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 8192 MB width x8 dual rank
|
|
[DEBUG] DIMMB 0 MB width x8 single rank, selected
|
|
[INFO ] Timestamp - after RAM initialization: 31313739589
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 00000004 to 0890
|
|
[DEBUG] read 03040003 from 0894
|
|
[DEBUG] wrote 00001000 to 0890
|
|
[DEBUG] read 09300024 from 0894
|
|
[DEBUG] read 00000000 from 0880
|
|
[DEBUG] wrote 00000000 to 0880
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 9f to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 44 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 001740ef from 07f0
|
|
[DEBUG] read 00 from 07f4
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] SF: Got idcode: ef 40 17 00 00
|
|
[INFO ] Manufacturer: ef
|
|
[INFO ] SF: Detected ef 4017 with sector size 0x1000, total 0x800000
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[SPEW ] PP: 0xfefef462 => cmd = { 0x02 0x200000 } chunk_len = 2
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200000 to 07e8
|
|
[DEBUG] wrote 05 to 07f0
|
|
[DEBUG] wrote 00 to 07f1
|
|
[DEBUG] wrote 41 to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] SF: : Successfully programmed 2 bytes @ 0x200000
|
|
[SPEW ] PP: 0xfefef4fe => cmd = { 0x02 0x200002 } chunk_len = 2
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200002 to 07e8
|
|
[DEBUG] wrote 6a to 07f0
|
|
[DEBUG] wrote 00 to 07f1
|
|
[DEBUG] wrote 41 to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] SF: : Successfully programmed 2 bytes @ 0x200002
|
|
[SPEW ] PP: 0xfefef49c => cmd = { 0x02 0x200050 } chunk_len = 20
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200050 to 07e8
|
|
[DEBUG] wrote 6443524d to 07f0
|
|
[DEBUG] wrote 00000634 to 07f4
|
|
[DEBUG] wrote 285799c8 to 07f8
|
|
[DEBUG] wrote 4ce1de47 to 07fc
|
|
[DEBUG] wrote 00000005 to 0800
|
|
[DEBUG] wrote 53 to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] SF: : Successfully programmed 20 bytes @ 0x200050
|
|
[SPEW ] PP: 0xfefef90c => cmd = { 0x02 0x200064 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200064 to 07e8
|
|
[DEBUG] wrote 3093fed3 to 07f0
|
|
[DEBUG] wrote 7482fed3 to 07f4
|
|
[DEBUG] wrote 000306a9 to 07f8
|
|
[DEBUG] wrote 00000085 to 07fc
|
|
[DEBUG] wrote 00000006 to 0800
|
|
[DEBUG] wrote 000000fc to 0804
|
|
[DEBUG] wrote 00000140 to 0808
|
|
[DEBUG] wrote 00000d20 to 080c
|
|
[DEBUG] wrote 0000000c to 0810
|
|
[DEBUG] wrote 0000000b to 0814
|
|
[DEBUG] wrote 00000005 to 0818
|
|
[DEBUG] wrote 0000000b to 081c
|
|
[DEBUG] wrote 0000001c to 0820
|
|
[DEBUG] wrote 000000d0 to 0824
|
|
[DEBUG] wrote 00000006 to 0828
|
|
[DEBUG] wrote 00000006 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefef94c => cmd = { 0x02 0x2000a4 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002000a4 to 07e8
|
|
[DEBUG] wrote 00000018 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 0000080b to 07fc
|
|
[DEBUG] wrote 00001860 to 0800
|
|
[DEBUG] wrote 0000000c to 0804
|
|
[DEBUG] wrote 00000008 to 0808
|
|
[DEBUG] wrote 00000006 to 080c
|
|
[DEBUG] wrote 00000004 to 0810
|
|
[DEBUG] wrote 00000014 to 0814
|
|
[DEBUG] wrote 00000005 to 0818
|
|
[DEBUG] wrote 00000008 to 081c
|
|
[DEBUG] wrote 0c0c0193 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00630020 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefef98c => cmd = { 0x02 0x2000e4 } chunk_len = 28
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002000e4 to 07e8
|
|
[DEBUG] wrote 00630020 to 07f0
|
|
[DEBUG] wrote 00002000 to 07f4
|
|
[DEBUG] wrote 00002000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 0000000c to 0804
|
|
[DEBUG] wrote 0000000f to 0808
|
|
[DEBUG] wrote 5b to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefef9a8 => cmd = { 0x02 0x200100 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200100 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000008 to 07f4
|
|
[DEBUG] wrote 0000000d to 07f8
|
|
[DEBUG] wrote 00000005 to 07fc
|
|
[DEBUG] wrote 00000005 to 0800
|
|
[DEBUG] wrote 0000000e to 0804
|
|
[DEBUG] wrote 00000005 to 0808
|
|
[DEBUG] wrote 00000005 to 080c
|
|
[DEBUG] wrote 00000001 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000001 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefef9e8 => cmd = { 0x02 0x200140 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200140 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000001 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefa28 => cmd = { 0x02 0x200180 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200180 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefa68 => cmd = { 0x02 0x2001c0 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002001c0 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefaa8 => cmd = { 0x02 0x200200 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200200 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000228 to 0820
|
|
[DEBUG] wrote fffffffd to 0824
|
|
[DEBUG] wrote 27270006 to 0828
|
|
[DEBUG] wrote 0000001e to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefae8 => cmd = { 0x02 0x200240 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200240 to 07e8
|
|
[DEBUG] wrote 000000c4 to 07f0
|
|
[DEBUG] wrote 26240012 to 07f4
|
|
[DEBUG] wrote 00000035 to 07f8
|
|
[DEBUG] wrote 000000db to 07fc
|
|
[DEBUG] wrote 2825002a to 0800
|
|
[DEBUG] wrote 00000055 to 0804
|
|
[DEBUG] wrote 000000f9 to 0808
|
|
[DEBUG] wrote 2725003a to 080c
|
|
[DEBUG] wrote 00000021 to 0810
|
|
[DEBUG] wrote 00000105 to 0814
|
|
[DEBUG] wrote 26250057 to 0818
|
|
[DEBUG] wrote 0000003b to 081c
|
|
[DEBUG] wrote 00000120 to 0820
|
|
[DEBUG] wrote 24220066 to 0824
|
|
[DEBUG] wrote 00000047 to 0828
|
|
[DEBUG] wrote 00000129 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefb28 => cmd = { 0x02 0x200280 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200280 to 07e8
|
|
[DEBUG] wrote 2623007a to 07f0
|
|
[DEBUG] wrote 0000004d to 07f4
|
|
[DEBUG] wrote 00000131 to 07f8
|
|
[DEBUG] wrote 2525008e to 07fc
|
|
[DEBUG] wrote 00000057 to 0800
|
|
[DEBUG] wrote 00000139 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000228 to 0814
|
|
[DEBUG] wrote fffffffc to 0818
|
|
[DEBUG] wrote 27260007 to 081c
|
|
[DEBUG] wrote 00000019 to 0820
|
|
[DEBUG] wrote 000000c0 to 0824
|
|
[DEBUG] wrote 27240015 to 0828
|
|
[DEBUG] wrote 00000039 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefb68 => cmd = { 0x02 0x2002c0 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002002c0 to 07e8
|
|
[DEBUG] wrote 000000df to 07f0
|
|
[DEBUG] wrote 2725002b to 07f4
|
|
[DEBUG] wrote 0000004f to 07f8
|
|
[DEBUG] wrote 000000f5 to 07fc
|
|
[DEBUG] wrote 2726003b to 0800
|
|
[DEBUG] wrote 00000026 to 0804
|
|
[DEBUG] wrote 00000109 to 0808
|
|
[DEBUG] wrote 26240057 to 080c
|
|
[DEBUG] wrote 0000003b to 0810
|
|
[DEBUG] wrote 00000120 to 0814
|
|
[DEBUG] wrote 2423006b to 0818
|
|
[DEBUG] wrote 00000049 to 081c
|
|
[DEBUG] wrote 0000012c to 0820
|
|
[DEBUG] wrote 2723007c to 0824
|
|
[DEBUG] wrote 0000004f to 0828
|
|
[DEBUG] wrote 00000133 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefba8 => cmd = { 0x02 0x200300 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200300 to 07e8
|
|
[DEBUG] wrote 26240090 to 07f0
|
|
[DEBUG] wrote 00000055 to 07f4
|
|
[DEBUG] wrote 00000139 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefbe8 => cmd = { 0x02 0x200340 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200340 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefc28 => cmd = { 0x02 0x200380 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200380 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefc68 => cmd = { 0x02 0x2003c0 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002003c0 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefca8 => cmd = { 0x02 0x200400 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200400 to 07e8
|
|
[DEBUG] wrote 00000228 to 07f0
|
|
[DEBUG] wrote fffffffe to 07f4
|
|
[DEBUG] wrote 2828002b to 07f8
|
|
[DEBUG] wrote 0000001f to 07fc
|
|
[DEBUG] wrote 000000c6 to 0800
|
|
[DEBUG] wrote 2925003b to 0804
|
|
[DEBUG] wrote 0000002e to 0808
|
|
[DEBUG] wrote 000000d5 to 080c
|
|
[DEBUG] wrote 29270051 to 0810
|
|
[DEBUG] wrote 0000004e to 0814
|
|
[DEBUG] wrote 000000f3 to 0818
|
|
[DEBUG] wrote 2925005f to 081c
|
|
[DEBUG] wrote 00000020 to 0820
|
|
[DEBUG] wrote 00000105 to 0824
|
|
[DEBUG] wrote 2827007e to 0828
|
|
[DEBUG] wrote 00000037 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefce8 => cmd = { 0x02 0x200440 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200440 to 07e8
|
|
[DEBUG] wrote 0000011e to 07f0
|
|
[DEBUG] wrote 2725008d to 07f4
|
|
[DEBUG] wrote 00000046 to 07f8
|
|
[DEBUG] wrote 0000012c to 07fc
|
|
[DEBUG] wrote 242500a3 to 0800
|
|
[DEBUG] wrote 00000045 to 0804
|
|
[DEBUG] wrote 0000012a to 0808
|
|
[DEBUG] wrote 252600b3 to 080c
|
|
[DEBUG] wrote 00000057 to 0810
|
|
[DEBUG] wrote 0000013c to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000228 to 0824
|
|
[DEBUG] wrote fffffffb to 0828
|
|
[DEBUG] wrote 2827002c to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefd28 => cmd = { 0x02 0x200480 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200480 to 07e8
|
|
[DEBUG] wrote 0000001c to 07f0
|
|
[DEBUG] wrote 000000c3 to 07f4
|
|
[DEBUG] wrote 2828003c to 07f8
|
|
[DEBUG] wrote 00000035 to 07fc
|
|
[DEBUG] wrote 000000dc to 0800
|
|
[DEBUG] wrote 29290050 to 0804
|
|
[DEBUG] wrote 00000053 to 0808
|
|
[DEBUG] wrote 000000f9 to 080c
|
|
[DEBUG] wrote 2726005f to 0810
|
|
[DEBUG] wrote 0000001d to 0814
|
|
[DEBUG] wrote 00000103 to 0818
|
|
[DEBUG] wrote 26280082 to 081c
|
|
[DEBUG] wrote 0000003b to 0820
|
|
[DEBUG] wrote 00000121 to 0824
|
|
[DEBUG] wrote 2627008e to 0828
|
|
[DEBUG] wrote 0000004a to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefd68 => cmd = { 0x02 0x2004c0 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002004c0 to 07e8
|
|
[DEBUG] wrote 0000012f to 07f0
|
|
[DEBUG] wrote 262500a7 to 07f4
|
|
[DEBUG] wrote 00000050 to 07f8
|
|
[DEBUG] wrote 00000136 to 07fc
|
|
[DEBUG] wrote 252600b1 to 0800
|
|
[DEBUG] wrote 0000001c to 0804
|
|
[DEBUG] wrote 00000140 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefda8 => cmd = { 0x02 0x200500 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200500 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00030000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefde8 => cmd = { 0x02 0x200540 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200540 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 0000000b to 0804
|
|
[DEBUG] wrote 00000002 to 0808
|
|
[DEBUG] wrote 000000fc to 080c
|
|
[DEBUG] wrote 000011e7 to 0810
|
|
[DEBUG] wrote 0a100208 to 0814
|
|
[DEBUG] wrote 00002000 to 0818
|
|
[DEBUG] wrote 00000140 to 081c
|
|
[DEBUG] wrote 00000d20 to 0820
|
|
[DEBUG] wrote 00000f00 to 0824
|
|
[DEBUG] wrote 00000d20 to 0828
|
|
[DEBUG] wrote 00000600 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefe28 => cmd = { 0x02 0x200580 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200580 to 07e8
|
|
[DEBUG] wrote 00000d20 to 07f0
|
|
[DEBUG] wrote 00002300 to 07f4
|
|
[DEBUG] wrote 00003020 to 07f8
|
|
[DEBUG] wrote 00010400 to 07fc
|
|
[DEBUG] wrote 00000780 to 0800
|
|
[DEBUG] wrote 00000780 to 0804
|
|
[DEBUG] wrote 00001e00 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00070000 to 0810
|
|
[DEBUG] wrote 000305dc to 0814
|
|
[DEBUG] wrote 39399801 to 0818
|
|
[DEBUG] wrote 37343555 to 081c
|
|
[DEBUG] wrote 35302d31 to 0820
|
|
[DEBUG] wrote 30412e30 to 0824
|
|
[DEBUG] wrote 13004c30 to 0828
|
|
[DEBUG] wrote 0034a530 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefe68 => cmd = { 0x02 0x2005c0 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 002005c0 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00000000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 00000000 to 081c
|
|
[DEBUG] wrote 00000000 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00000000 to 0828
|
|
[DEBUG] wrote 00000000 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefea8 => cmd = { 0x02 0x200600 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200600 to 07e8
|
|
[DEBUG] wrote 00000000 to 07f0
|
|
[DEBUG] wrote 00000000 to 07f4
|
|
[DEBUG] wrote 00000000 to 07f8
|
|
[DEBUG] wrote 00000000 to 07fc
|
|
[DEBUG] wrote 00030000 to 0800
|
|
[DEBUG] wrote 00000000 to 0804
|
|
[DEBUG] wrote 00000000 to 0808
|
|
[DEBUG] wrote 00000000 to 080c
|
|
[DEBUG] wrote 00000000 to 0810
|
|
[DEBUG] wrote 00000000 to 0814
|
|
[DEBUG] wrote 00000000 to 0818
|
|
[DEBUG] wrote 0000000b to 081c
|
|
[DEBUG] wrote 00000002 to 0820
|
|
[DEBUG] wrote 000000fc to 0824
|
|
[DEBUG] wrote 000011e7 to 0828
|
|
[DEBUG] wrote 0a100208 to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefefee8 => cmd = { 0x02 0x200640 } chunk_len = 64
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200640 to 07e8
|
|
[DEBUG] wrote 00002000 to 07f0
|
|
[DEBUG] wrote 00000140 to 07f4
|
|
[DEBUG] wrote 00000d20 to 07f8
|
|
[DEBUG] wrote 00000f00 to 07fc
|
|
[DEBUG] wrote 00000d20 to 0800
|
|
[DEBUG] wrote 00000600 to 0804
|
|
[DEBUG] wrote 00000d20 to 0808
|
|
[DEBUG] wrote 00002300 to 080c
|
|
[DEBUG] wrote 00003020 to 0810
|
|
[DEBUG] wrote 00010400 to 0814
|
|
[DEBUG] wrote 00000780 to 0818
|
|
[DEBUG] wrote 00000780 to 081c
|
|
[DEBUG] wrote 00001e00 to 0820
|
|
[DEBUG] wrote 00000000 to 0824
|
|
[DEBUG] wrote 00070000 to 0828
|
|
[DEBUG] wrote 000305dc to 082c
|
|
[DEBUG] wrote 7f to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] PP: 0xfefeff28 => cmd = { 0x02 0x200680 } chunk_len = 24
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 06 to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0001 to 0876
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 0006 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 02 to 0878
|
|
[DEBUG] read 0001 from 0876
|
|
[DEBUG] wrote 0003 to 0876
|
|
[DEBUG] read 0006 from 0874
|
|
[DEBUG] wrote 00200680 to 07e8
|
|
[DEBUG] wrote 39399801 to 07f0
|
|
[DEBUG] wrote 37343555 to 07f4
|
|
[DEBUG] wrote 35302d31 to 07f8
|
|
[DEBUG] wrote 30412e30 to 07fc
|
|
[DEBUG] wrote 11004c30 to 0800
|
|
[DEBUG] wrote 0051f130 to 0804
|
|
[DEBUG] wrote 57 to 0872
|
|
[DEBUG] wrote 06 to 0871
|
|
[DEBUG] read 0484 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] wrote 0000 to 0874
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 05 to 0878
|
|
[DEBUG] read 0003 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 40 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 80 from 07f0
|
|
[DEBUG] wrote 0000 to 0874
|
|
[SPEW ] SF: : Successfully programmed 1588 bytes @ 0x200064
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ffdb000
|
|
[INFO ] POST: 0x3b
|
|
[INFO ] POST: 0x3c
|
|
[INFO ] POST: 0x3d
|
|
[INFO ] POST: 0x3f
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 1: 0x80300000 0x100000
|
|
[DEBUG] Subregion 2: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='fallback/postcar', alloc=0xfffe77e0(0xfefeff7c), force_ro=false, type=-1)
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x31c80 size 0x81a8 in mcache @0xfeff1004
|
|
[SPEW ] CBFS DEBUG: Decompressing 33192 bytes from 'fallback/postcar' to 0x7ffccfc0 with algo 0
|
|
[DEBUG] Loading module at 0x7ffcd000 with entry 0x7ffcd031. filesize: 0x77c8 memsize: 0xdb20
|
|
[DEBUG] Processing 616 relocs. Offset value of 0x7dfcd000
|
|
[INFO ] Timestamp - end of romstage: 46257144456
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 14648 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.03-250-g59e4095ecfcb-dirty Mon Apr 21 05:10:24 UTC 2025 x86_32 postcar starting (log level: 7)...
|
|
[INFO ] Timestamp - start of postcar: 46333434444
|
|
[INFO ] Timestamp - end of postcar: 46348470937
|
|
[DEBUG] Normal boot
|
|
[INFO ] Timestamp - starting to load ramstage: 46370539067
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x68c0 size 0x1fe6e in mcache @0x7ffdc05c
|
|
[INFO ] Timestamp - starting LZMA decompress (ignore for x86): 46411163666
|
|
[INFO ] Timestamp - finished LZMA decompress (ignore for x86): 46556656506
|
|
[DEBUG] Loading module at 0x7fe79000 with entry 0x7fe79000. filesize: 0x43768 memsize: 0x152878
|
|
[DEBUG] Processing 6504 relocs. Offset value of 0x7be79000
|
|
[INFO ] Timestamp - finished loading ramstage: 46622169319
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 75 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.03-250-g59e4095ecfcb-dirty Mon Apr 21 05:10:24 UTC 2025 x86_32 ramstage starting (log level: 7)...
|
|
[INFO ] POST: 0x39
|
|
[INFO ] Timestamp - start of ramstage: 46701556145
|
|
[INFO ] POST: 0x6f
|
|
[DEBUG] Normal boot
|
|
[INFO ] POST: 0x70
|
|
[DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 3 ms
|
|
[INFO ] POST: 0x71
|
|
[INFO ] Timestamp - early chipset initialization: 46764486580
|
|
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 9 ms
|
|
[INFO ] POST: 0x72
|
|
[INFO ] Timestamp - device enumeration: 46809322733
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:00:00.0 [8086/0150] enabled
|
|
[DEBUG] PCI: 00:00:01.0 [8086/0151] enabled
|
|
[INFO ] PCI: Static device PCI: 00:00:01.1 not found, disabling it.
|
|
[DEBUG] PCI: 00:00:01.2 [0000/0000] hidden
|
|
[INFO ] PCI: Static device PCI: 00:00:02.0 not found, disabling it.
|
|
[DEBUG] PCI: 00:00:04.0 [0000/0000] hidden
|
|
[DEBUG] PCI: 00:00:06.0 [0000/0000] hidden
|
|
[DEBUG] PCI: 00:00:14.0 [8086/1e31] enabled
|
|
[DEBUG] PCI: 00:00:16.0 [8086/1e3a] enabled
|
|
[DEBUG] PCI: 00:00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:00:16.1 [8086/1e3b] disabled No operations
|
|
[DEBUG] PCI: 00:00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:00:16.3: Disabling device
|
|
[DEBUG] PCI: 00:00:19.0 [8086/1503] enabled
|
|
[DEBUG] PCI: 00:00:1a.0 [8086/1e2d] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/1e20] enabled
|
|
[DEBUG] PCI: 00:00:1c.0: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.0 [8086/1e10] enabled
|
|
[DEBUG] PCI: 00:00:1c.1: Found a downstream device
|
|
[INFO ] PCI: Static device PCI: 00:00:1c.1 not found, disabling it.
|
|
[DEBUG] PCI: 00:00:1c.2: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.2 [8086/1e14] disabled
|
|
[DEBUG] PCI: 00:00:1c.3: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.3 [8086/1e16] enabled
|
|
[DEBUG] PCI: 00:00:1c.4: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.4 [8086/1e18] enabled
|
|
[DEBUG] PCI: 00:00:1c.5: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.5 [8086/1e1a] disabled
|
|
[DEBUG] PCI: 00:00:1c.6: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.6 [8086/1e1c] disabled
|
|
[DEBUG] PCI: 00:00:1c.7: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.7 [8086/1e1e] enabled
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/1e26] enabled
|
|
[DEBUG] PCI: 00:00:1e.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.0 [8086/244e] disabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/1e44] enabled
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/1e00] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/1e22] enabled
|
|
[DEBUG] PCI: 00:00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.5 [8086/1e08] disabled No operations
|
|
[DEBUG] PCI: 00:00:1f.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.6 [8086/1e24] disabled No operations
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:00:01.1
|
|
[WARN ] PCI: 00:00:02.0
|
|
[WARN ] PCI: 00:00:1c.1
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:00:01.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[INFO ] POST: 0x24
|
|
[INFO ] POST: 0x25
|
|
[INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 19 msecs
|
|
[DEBUG] PCI: 00:00:01.2 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:01.2 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:04.0 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:04.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:06.0 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:06.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:02:00.0 subordinate bus PCI Express
|
|
[DEBUG] PCI: 00:02:00.0 [12d8/2304] enabled
|
|
[DEBUG] PCI: 00:02:00.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:03:01.0 subordinate bus PCI Express
|
|
[DEBUG] PCI: 00:03:01.0 [12d8/2304] enabled
|
|
[DEBUG] PCI: 00:03:02.0 subordinate bus PCI Express
|
|
[DEBUG] PCI: 00:03:02.0 [12d8/2304] enabled
|
|
[DEBUG] PCI: 00:03:01.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 04
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:04:00.0 [1b21/0612] enabled
|
|
[INFO ] POST: 0x25
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[INFO ] ASPM: Enabled None
|
|
[DEBUG] PCI: 00:04:00.0: No LTR support
|
|
[DEBUG] scan_bus: bus PCI: 00:03:01.0 finished in 32 msecs
|
|
[DEBUG] PCI: 00:03:02.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 05
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:05:00.0 [1b6f/7023] enabled
|
|
[INFO ] POST: 0x25
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled None
|
|
[DEBUG] PCI: 00:05:00.0: No LTR support
|
|
[DEBUG] scan_bus: bus PCI: 00:03:02.0 finished in 27 msecs
|
|
[INFO ] POST: 0x25
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[INFO ] ASPM: Enabled None
|
|
[INFO ] PCIe: Common Clock Configuration already enabled
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[INFO ] ASPM: Enabled None
|
|
[DEBUG] scan_bus: bus PCI: 00:02:00.0 finished in 137 msecs
|
|
[INFO ] POST: 0x25
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[INFO ] ASPM: Enabled None
|
|
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 189 msecs
|
|
[DEBUG] PCI: 00:00:1c.3 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 06
|
|
[INFO ] POST: 0x24
|
|
[INFO ] Disabling ASPM for PCI: 00:06:00.0 [1b21/0611]
|
|
[INFO ] Setting AHCI mode for PCI: 00:06:00.0 [1b21/0611]
|
|
[DEBUG] PCI: 00:06:00.0 [1b21/0611] enabled
|
|
[INFO ] POST: 0x25
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[DEBUG] PCI: 00:06:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 49 msecs
|
|
[DEBUG] PCI: 00:00:1c.4 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 07
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:07:00.0 subordinate PCI
|
|
[DEBUG] PCI: 00:07:00.0 [1b21/1080] enabled
|
|
[DEBUG] PCI: 00:07:00.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 08
|
|
[INFO ] POST: 0x24
|
|
[INFO ] POST: 0x25
|
|
[DEBUG] scan_bus: bus PCI: 00:07:00.0 finished in 10 msecs
|
|
[INFO ] POST: 0x25
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[INFO ] ASPM: Enabled None
|
|
[DEBUG] PCI: 00:07:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.4: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.4 finished in 61 msecs
|
|
[DEBUG] PCI: 00:00:1c.7 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 09
|
|
[INFO ] POST: 0x24
|
|
[DEBUG] PCI: 00:09:00.0 [1b21/1042] enabled
|
|
[INFO ] POST: 0x25
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] PCIE CLK PM is not supported by endpoint
|
|
[INFO ] ASPM: Enabled None
|
|
[DEBUG] PCI: 00:09:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.7: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.7 finished in 41 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[DEBUG] PNP: 002e.1 disabled
|
|
[DEBUG] PNP: 002e.2 enabled
|
|
[DEBUG] PNP: 002e.3 disabled
|
|
[DEBUG] PNP: 002e.5 enabled
|
|
[DEBUG] PNP: 002e.6 disabled
|
|
[DEBUG] PNP: 002e.7 disabled
|
|
[DEBUG] PNP: 002e.8 disabled
|
|
[DEBUG] PNP: 002e.108 enabled
|
|
[DEBUG] PNP: 002e.109 enabled
|
|
[DEBUG] PNP: 002e.209 enabled
|
|
[DEBUG] PNP: 002e.309 enabled
|
|
[DEBUG] PNP: 002e.509 enabled
|
|
[DEBUG] PNP: 002e.a enabled
|
|
[DEBUG] PNP: 002e.b enabled
|
|
[DEBUG] PNP: 002e.d disabled
|
|
[DEBUG] PNP: 002e.e disabled
|
|
[DEBUG] PNP: 002e.f disabled
|
|
[DEBUG] PNP: 002e.14 disabled
|
|
[DEBUG] PNP: 002e.16 disabled
|
|
[DEBUG] PNP: 0c31.0 enabled
|
|
[DEBUG] PNP: 002e.308 enabled
|
|
[DEBUG] PNP: 002e.409 enabled
|
|
[DEBUG] PNP: 002e.609 enabled
|
|
[DEBUG] PNP: 002e.709 enabled
|
|
[DEBUG] PNP: 002e.9 enabled
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 84 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
|
|
[INFO ] POST: 0x25
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 795 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 813 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 833 ms
|
|
[DEBUG] BM-LOCKDOWN: Enabling boot media protection scheme 'readonly' using CTRL...
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 00000004 to 0890
|
|
[DEBUG] read 03040003 from 0894
|
|
[DEBUG] wrote 00001000 to 0890
|
|
[DEBUG] read 09300024 from 0894
|
|
[DEBUG] read 00000000 from 0880
|
|
[DEBUG] wrote 00000000 to 0880
|
|
[DEBUG] read 0080 from 0870
|
|
[DEBUG] wrote 000c to 0870
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 9f to 0878
|
|
[DEBUG] read 0000 from 0876
|
|
[DEBUG] wrote 0000 to 0876
|
|
[DEBUG] read 0000 from 0874
|
|
[DEBUG] wrote 00000000 to 07e8
|
|
[DEBUG] wrote 44 to 0872
|
|
[DEBUG] wrote 02 to 0871
|
|
[DEBUG] read 0084 from 0870
|
|
[DEBUG] wrote 0004 to 0870
|
|
[DEBUG] read 001740ef from 07f0
|
|
[DEBUG] read 00 from 07f4
|
|
[DEBUG] wrote 0000 to 0874
|
|
[INFO ] Manufacturer: ef
|
|
[INFO ] SF: Detected ef 4017 with sector size 0x1000, total 0x800000
|
|
[INFO ] spi_flash_protect: FPR 0 is enabled for range 0x00000000-0x007fffff
|
|
[INFO ] BM-LOCKDOWN: Enabled bootmedia protection
|
|
[DEBUG] BS: BS_DEV_RESOURCES entry times (exec / console): 0 / 104 ms
|
|
[INFO ] POST: 0x73
|
|
[INFO ] Timestamp - device configuration: 49575226573
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x47a600000 TOLUD 0x84a00000 TOM 0x400000000
|
|
[DEBUG] MEBASE 0x3ff000000
|
|
[DEBUG] IGD decoded, subtracting 64M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 14246M
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[DEBUG] PCI: 00:03:01.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
|
|
[DEBUG] PCI: 00:04:00.0 20 * [0x0 - 0x1f] io
|
|
[DEBUG] PCI: 00:04:00.0 10 * [0x20 - 0x27] io
|
|
[DEBUG] PCI: 00:04:00.0 18 * [0x28 - 0x2f] io
|
|
[DEBUG] PCI: 00:04:00.0 14 * [0x30 - 0x33] io
|
|
[DEBUG] PCI: 00:04:00.0 1c * [0x34 - 0x37] io
|
|
[DEBUG] PCI: 00:03:01.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:03:02.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
|
|
[DEBUG] PCI: 00:03:02.0 io: size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
[DEBUG] PCI: 00:02:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
|
|
[DEBUG] PCI: 00:03:01.0 1c * [0x0 - 0xfff] io
|
|
[DEBUG] PCI: 00:02:00.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:02:00.0 1c * [0x0 - 0xfff] io
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:03:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:04:00.0 30 * [0x0 - 0xffff] mem
|
|
[DEBUG] PCI: 00:04:00.0 24 * [0x10000 - 0x101ff] mem
|
|
[DEBUG] PCI: 00:03:01.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:03:02.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:05:00.0 10 * [0x0 - 0x7fff] mem
|
|
[DEBUG] PCI: 00:03:02.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:02:00.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:03:01.0 20 * [0x0 - 0xfffff] mem
|
|
[DEBUG] PCI: 00:03:02.0 20 * [0x100000 - 0x1fffff] mem
|
|
[DEBUG] PCI: 00:02:00.0 mem: size: 200000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:02:00.0 20 * [0x0 - 0x1fffff] mem
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 200000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:03:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:03:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:03:02.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:03:02.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:02:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:02:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:06:00.0 20 * [0x0 - 0x1f] io
|
|
[DEBUG] PCI: 00:06:00.0 10 * [0x20 - 0x27] io
|
|
[DEBUG] PCI: 00:06:00.0 18 * [0x28 - 0x2f] io
|
|
[DEBUG] PCI: 00:06:00.0 14 * [0x30 - 0x33] io
|
|
[DEBUG] PCI: 00:06:00.0 1c * [0x34 - 0x37] io
|
|
[DEBUG] PCI: 00:00:1c.3 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:06:00.0 24 * [0x0 - 0x1ff] mem
|
|
[DEBUG] PCI: 00:00:1c.3 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.7 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.7 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.7 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:09:00.0 10 * [0x0 - 0x7fff] mem
|
|
[DEBUG] PCI: 00:00:1c.7 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.b 62 base 00000000 limit 00000001 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: f000, Tag: 100
|
|
[DEBUG] PCI: 00:00:1c.0 1c * [0xf000 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:00:1c.3 1c * [0xe000 - 0xefff] limit: efff io
|
|
[DEBUG] PCI: 00:00:19.0 18 * [0xdfe0 - 0xdfff] limit: dfff io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0xdfc0 - 0xdfdf] limit: dfdf io
|
|
[ERROR] Resource didn't fit!!!
|
|
[DEBUG] PNP: 002e.308 60 * size: 0x8 limit: fff io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0xdfb8 - 0xdfbf] limit: dfbf io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0xdfb0 - 0xdfb7] limit: dfb7 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0xdfac - 0xdfaf] limit: dfaf io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0xdfa8 - 0xdfab] limit: dfab io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 100000000 limit 47a5fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 80000000 limit 849fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base fed90000 limit fed90fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base fed91000 limit fed91fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 84a00000, Size: 6b600000, Tag: 200
|
|
[INFO ] * Base: 47a600000, Size: b85a00000, Tag: 200
|
|
[DEBUG] PCI: 00:00:1c.0 20 * [0xefe00000 - 0xefffffff] limit: efffffff mem
|
|
[DEBUG] PCI: 00:00:1c.3 20 * [0xefd00000 - 0xefdfffff] limit: efdfffff mem
|
|
[DEBUG] PCI: 00:00:1c.7 20 * [0xefc00000 - 0xefcfffff] limit: efcfffff mem
|
|
[DEBUG] PCI: 00:00:19.0 10 * [0xefbe0000 - 0xefbfffff] limit: efbfffff mem
|
|
[DEBUG] PCI: 00:00:14.0 10 * [0xefbd0000 - 0xefbdffff] limit: efbdffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0xefbcc000 - 0xefbcffff] limit: efbcffff mem
|
|
[DEBUG] PCI: 00:00:19.0 14 * [0xefbcb000 - 0xefbcbfff] limit: efbcbfff mem
|
|
[DEBUG] PCI: 00:00:1f.2 24 * [0xefbca000 - 0xefbca7ff] limit: efbca7ff mem
|
|
[DEBUG] PCI: 00:00:1a.0 10 * [0xefbc9000 - 0xefbc93ff] limit: efbc93ff mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 * [0xefbc8000 - 0xefbc83ff] limit: efbc83ff mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 * [0xefbc7000 - 0xefbc70ff] limit: efbc70ff mem
|
|
[DEBUG] PCI: 00:00:16.0 10 * [0xefbc6000 - 0xefbc600f] limit: efbc600f mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 00:02:00.0 1c * [0xf000 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:02:00.0 20 * [0xefe00000 - 0xefffffff] limit: efffffff mem
|
|
[DEBUG] PCI: 00:03:01.0 1c * [0xf000 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:03:01.0 20 * [0xefe00000 - 0xefefffff] limit: efefffff mem
|
|
[DEBUG] PCI: 00:03:02.0 20 * [0xeff00000 - 0xefffffff] limit: efffffff mem
|
|
[DEBUG] PCI: 00:04:00.0 10 * [0xf020 - 0xf027] limit: f027 io
|
|
[DEBUG] PCI: 00:04:00.0 14 * [0xf030 - 0xf033] limit: f033 io
|
|
[DEBUG] PCI: 00:04:00.0 18 * [0xf028 - 0xf02f] limit: f02f io
|
|
[DEBUG] PCI: 00:04:00.0 1c * [0xf034 - 0xf037] limit: f037 io
|
|
[DEBUG] PCI: 00:04:00.0 20 * [0xf000 - 0xf01f] limit: f01f io
|
|
[DEBUG] PCI: 00:04:00.0 24 * [0xefe10000 - 0xefe101ff] limit: efe101ff mem
|
|
[DEBUG] PCI: 00:04:00.0 30 * [0xefe00000 - 0xefe0ffff] limit: efe0ffff mem
|
|
[DEBUG] PCI: 00:05:00.0 10 * [0xeff00000 - 0xeff07fff] limit: eff07fff mem
|
|
[DEBUG] PCI: 00:06:00.0 10 * [0xe020 - 0xe027] limit: e027 io
|
|
[DEBUG] PCI: 00:06:00.0 14 * [0xe030 - 0xe033] limit: e033 io
|
|
[DEBUG] PCI: 00:06:00.0 18 * [0xe028 - 0xe02f] limit: e02f io
|
|
[DEBUG] PCI: 00:06:00.0 1c * [0xe034 - 0xe037] limit: e037 io
|
|
[DEBUG] PCI: 00:06:00.0 20 * [0xe000 - 0xe01f] limit: e01f io
|
|
[DEBUG] PCI: 00:06:00.0 24 * [0xefd00000 - 0xefd001ff] limit: efd001ff mem
|
|
[DEBUG] PCI: 00:09:00.0 10 * [0xefc00000 - 0xefc07fff] limit: efc07fff mem
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000efbd0000 - 0x00000000efbdffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000efbc6000 - 0x00000000efbc600f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:00:19.0 10 <- [0x00000000efbe0000 - 0x00000000efbfffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:00:19.0 14 <- [0x00000000efbcb000 - 0x00000000efbcbfff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000dfe0 - 0x000000000000dfff] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000efbc9000 - 0x00000000efbc93ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000efbcc000 - 0x00000000efbcffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000efe00000 - 0x00000000efffffff] size 0x00200000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PCI: 00:02:00.0 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 bus 03 io
|
|
[DEBUG] PCI: 00:02:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
|
|
[DEBUG] PCI: 00:02:00.0 20 <- [0x00000000efe00000 - 0x00000000efffffff] size 0x00200000 gran 0x14 seg 00 bus 03 mem
|
|
[DEBUG] PCI: 00:03:01.0 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 bus 04 io
|
|
[DEBUG] PCI: 00:03:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem
|
|
[DEBUG] PCI: 00:03:01.0 20 <- [0x00000000efe00000 - 0x00000000efefffff] size 0x00100000 gran 0x14 seg 00 bus 04 mem
|
|
[DEBUG] PCI: 00:04:00.0 10 <- [0x000000000000f020 - 0x000000000000f027] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:04:00.0 14 <- [0x000000000000f030 - 0x000000000000f033] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:04:00.0 18 <- [0x000000000000f028 - 0x000000000000f02f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:04:00.0 1c <- [0x000000000000f034 - 0x000000000000f037] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:04:00.0 20 <- [0x000000000000f000 - 0x000000000000f01f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:04:00.0 24 <- [0x00000000efe10000 - 0x00000000efe101ff] size 0x00000200 gran 0x09 mem
|
|
[DEBUG] PCI: 00:04:00.0 30 <- [0x00000000efe00000 - 0x00000000efe0ffff] size 0x00010000 gran 0x10 romem
|
|
[DEBUG] PCI: 00:03:02.0 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c seg 00 bus 05 io
|
|
[DEBUG] PCI: 00:03:02.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 prefmem
|
|
[DEBUG] PCI: 00:03:02.0 20 <- [0x00000000eff00000 - 0x00000000efffffff] size 0x00100000 gran 0x14 seg 00 bus 05 mem
|
|
[DEBUG] PCI: 00:05:00.0 10 <- [0x00000000eff00000 - 0x00000000eff07fff] size 0x00008000 gran 0x0f mem64
|
|
[DEBUG] PCI: 00:00:1c.3 1c <- [0x000000000000e000 - 0x000000000000efff] size 0x00001000 gran 0x0c seg 00 bus 06 io
|
|
[DEBUG] PCI: 00:00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 06 prefmem
|
|
[DEBUG] PCI: 00:00:1c.3 20 <- [0x00000000efd00000 - 0x00000000efdfffff] size 0x00100000 gran 0x14 seg 00 bus 06 mem
|
|
[DEBUG] PCI: 00:06:00.0 10 <- [0x000000000000e020 - 0x000000000000e027] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:06:00.0 14 <- [0x000000000000e030 - 0x000000000000e033] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:06:00.0 18 <- [0x000000000000e028 - 0x000000000000e02f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:06:00.0 1c <- [0x000000000000e034 - 0x000000000000e037] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:06:00.0 20 <- [0x000000000000e000 - 0x000000000000e01f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:06:00.0 24 <- [0x00000000efd00000 - 0x00000000efd001ff] size 0x00000200 gran 0x09 mem
|
|
[DEBUG] PCI: 00:00:1c.4 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 07 io
|
|
[DEBUG] PCI: 00:00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 07 prefmem
|
|
[DEBUG] PCI: 00:00:1c.4 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 07 mem
|
|
[DEBUG] PCI: 00:07:00.0 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c seg 00 bus 08 io
|
|
[DEBUG] PCI: 00:07:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 08 prefmem
|
|
[DEBUG] PCI: 00:07:00.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 08 mem
|
|
[DEBUG] PCI: 00:00:1c.7 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 09 io
|
|
[DEBUG] PCI: 00:00:1c.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 09 prefmem
|
|
[DEBUG] PCI: 00:00:1c.7 20 <- [0x00000000efc00000 - 0x00000000efcfffff] size 0x00100000 gran 0x14 seg 00 bus 09 mem
|
|
[DEBUG] PCI: 00:09:00.0 10 <- [0x00000000efc00000 - 0x00000000efc07fff] size 0x00008000 gran 0x0f mem64
|
|
[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000efbc8000 - 0x00000000efbc83ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.5 f0 <- [0x0000000000000082 - 0x0000000000000081] size 0x00000000 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.209 e0 <- [0x00000000000000df - 0x00000000000000de] size 0x00000000 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.509 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.509 f5 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.a e3 <- [0x0000000000000004 - 0x0000000000000003] size 0x00000000 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.a e7 <- [0x0000000000000011 - 0x0000000000000010] size 0x00000000 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.a f2 <- [0x000000000000005d - 0x000000000000005d] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.b 60 <- [0x0000000000000290 - 0x0000000000000291] size 0x00000002 gran 0x01 io
|
|
[DEBUG] PNP: 002e.b 62 <- [0x0000000000000000 - 0x0000000000000001] size 0x00000002 gran 0x01 io
|
|
[DEBUG] PNP: 002e.b 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq
|
|
[NOTE ] PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.308 60 io size: 0x0000000008 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.609 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.609 f5 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000dfb8 - 0x000000000000dfbf] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000dfac - 0x000000000000dfaf] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000dfb0 - 0x000000000000dfb7] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000dfa8 - 0x000000000000dfab] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000dfc0 - 0x000000000000dfdf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000efbca000 - 0x00000000efbca7ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000efbc7000 - 0x00000000efbc70ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1801 ms
|
|
[INFO ] POST: 0x74
|
|
[INFO ] Timestamp - device enable: 54826629724
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:01.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:01.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:01.0 cmd <- 00
|
|
[DEBUG] PCI: 00:00:14.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:14.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:16.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:19.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1a.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1c.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1c.3 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.3 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1c.3 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1c.4 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.4 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1c.4 cmd <- 100
|
|
[DEBUG] PCI: 00:00:1c.7 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.7 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1c.7 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 1043/84ca
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 00:02:00.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:02:00.0 cmd <- 07
|
|
[DEBUG] PCI: 00:03:01.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:03:01.0 cmd <- 07
|
|
[DEBUG] PCI: 00:03:02.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:03:02.0 cmd <- 06
|
|
[DEBUG] PCI: 00:04:00.0 cmd <- 03
|
|
[DEBUG] PCI: 00:05:00.0 cmd <- 02
|
|
[DEBUG] PCI: 00:06:00.0 cmd <- 03
|
|
[DEBUG] PCI: 00:07:00.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:07:00.0 cmd <- 00
|
|
[DEBUG] PCI: 00:09:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 217 ms
|
|
[DEBUG] read 6000 from 07e4
|
|
[DEBUG] wrote 00000004 to 0890
|
|
[DEBUG] read 03040003 from 0894
|
|
[DEBUG] wrote 00001000 to 0890
|
|
[DEBUG] read 09300024 from 0894
|
|
[DEBUG] read 00000000 from 0880
|
|
[DEBUG] wrote 00000000 to 0880
|
|
[DEBUG] BS: BS_DEV_INIT entry times (exec / console): 0 / 25 ms
|
|
[INFO ] POST: 0x75
|
|
[INFO ] Timestamp - device initialization: 55566728559
|
|
[INFO ] Initializing devices...
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[INFO ] LAPIC 0x0 switched to X2APIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000047a5fffff size 0x37a600000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 1/4.
|
|
[DEBUG] MTRR: WB selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000000f80000000 type 0
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[INFO ] POST: 0x93
|
|
[DEBUG] CPU has 4 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[DEBUG] microcode: sig=0x306a9 pf=0x2 revision=0x21
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x6800 in mcache @0x7ffdc02c
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
|
|
[INFO ] LAPIC 0x0 in X2APIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[INFO ] LAPIC 0x2 switched to X2APIC mode.
|
|
[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x4 switched to X2APIC mode.
|
|
[INFO ] LAPIC 0x6 switched to X2APIC mode.
|
|
[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 3 apic_id 6, MCU rev: 0x00000021
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7fe95c9a
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] HANDLER [0x802fe000-0x802ff62f]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fdc00-0x802fdfff]
|
|
[DEBUG] stub0 [0x802f6000-0x802f619f]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fd800-0x802fdbff]
|
|
[DEBUG] stub1 [0x802f5c00-0x802f5d9f]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fd400-0x802fd7ff]
|
|
[DEBUG] stub2 [0x802f5800-0x802f599f]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fd000-0x802fd3ff]
|
|
[DEBUG] stub3 [0x802f5400-0x802f559f]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80000fff]
|
|
[DEBUG] Loading module at 0x802fe000 with entry 0x802ff37c. filesize: 0x15d0 memsize: 0x1630
|
|
[DEBUG] Processing 77 relocs. Offset value of 0x802fe000
|
|
[DEBUG] Loading module at 0x802f6000 with entry 0x802f6000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x802f6000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 802f6000. Will call 0x802ff37c
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ee000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802ee000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802edc00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802edc00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed800, cpu = 2
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ed800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ed400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked
|
|
[INFO ] APIC: 00: PP0 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #2
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] APIC: 02: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
|
|
[INFO ] APIC: 04: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] IA32_FEATURE_CONTROL already locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] CPU #1 initialized
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] CPU #2 initialized
|
|
[INFO ] APIC: 06: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] CPU #3 initialized
|
|
[INFO ] bsp_do_flight_plan done after 625 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO6
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 897 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling IGD.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 65 Watts
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 16 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:01.0 init
|
|
[DEBUG] PCI: 00:00:01.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:14.0 init
|
|
[DEBUG] XHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:14.0 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : YES
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Normal
|
|
[DEBUG] ME: Current Operation State : M0 with UMA
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : Host Communication
|
|
[DEBUG] ME: Power Management Event : Pseudo-global reset
|
|
[DEBUG] ME: Progress Phase State : Host communication established
|
|
[NOTE ] ME: BIOS path: Normal
|
|
[DEBUG] No CMOS option 'me_state'.
|
|
[DEBUG] No CMOS option 'me_state_prev'.
|
|
[DEBUG] ME: me_state=0, me_state_prev=0
|
|
[DEBUG] ME: Extend SHA-256: 89c5086d985c68d6817725b46ce96d1c2f968bae63d77eb5bd9b9a92920ffd04
|
|
[INFO ] ME: MBP item header 00020103
|
|
[INFO ] ME: MBP item header 00050102
|
|
[INFO ] ME: MBP item header 00020501
|
|
[INFO ] ME: MBP item header 00020201
|
|
[INFO ] ME: MBP item header 02030101
|
|
[INFO ] ME: MBP item header 02060301
|
|
[INFO ] ME: MBP item header 02090401
|
|
[DEBUG] ME: found version 8.1.0.1248
|
|
[DEBUG] ME Capability: Full Network manageability : disabled
|
|
[DEBUG] ME Capability: Regular Network manageability : disabled
|
|
[DEBUG] ME Capability: Manageability : disabled
|
|
[DEBUG] ME Capability: Small business technology : disabled
|
|
[DEBUG] ME Capability: Level III manageability : disabled
|
|
[DEBUG] ME Capability: IntelR Anti-Theft (AT) : disabled
|
|
[DEBUG] ME Capability: IntelR Capability Licensing Service (CLS) : enabled
|
|
[DEBUG] ME Capability: IntelR Power Sharing Technology (MPC) : enabled
|
|
[DEBUG] ME Capability: ICC Over Clocking : enabled
|
|
[DEBUG] ME Capability: Protected Audio Video Path (PAVP) : enabled
|
|
[DEBUG] ME Capability: IPV6 : disabled
|
|
[DEBUG] ME Capability: KVM Remote Control (KVM) : disabled
|
|
[DEBUG] ME Capability: Outbreak Containment Heuristic (OCH) : disabled
|
|
[DEBUG] ME Capability: Virtual LAN (VLAN) : enabled
|
|
[DEBUG] ME Capability: TLS : disabled
|
|
[DEBUG] ME Capability: Wireless LAN (WLAN) : disabled
|
|
[DEBUG] PCI: 00:00:16.0 init finished in 241 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:19.0 init
|
|
[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1a.0 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: base = 0xefbcc000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: initializing codec #3...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x80862806
|
|
[DEBUG] azalia_audio: - verb size: 16
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] azalia_audio: initializing codec #0...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0892
|
|
[DEBUG] azalia_audio: - verb size: 60
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 49 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1c.3 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.3 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1c.4 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.4 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1c.7 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.7 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected Z77, device id: 0x1e44, rev id 0x4
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] PantherPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 56 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0xefbca000
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 10 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00:1f.3 init
|
|
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:04:00.0 init
|
|
[DEBUG] PCI: 00:04:00.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:05:00.0 init
|
|
[DEBUG] PCI: 00:05:00.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:09:00.0 init
|
|
[DEBUG] PCI: 00:09:00.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.2 init
|
|
[DEBUG] PNP: 002e.2 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.5 init
|
|
[DEBUG] Keyboard init...
|
|
[DEBUG] PS/2 keyboard initialized on primary channel
|
|
[DEBUG] PNP: 002e.5 init finished in 423 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.108 init
|
|
[DEBUG] PNP: 002e.108 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.109 init
|
|
[DEBUG] PNP: 002e.109 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.209 init
|
|
[DEBUG] PNP: 002e.209 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.309 init
|
|
[DEBUG] PNP: 002e.309 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.509 init
|
|
[DEBUG] PNP: 002e.509 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.a init
|
|
[DEBUG] PNP: 002e.a init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.b init
|
|
[DEBUG] PNP: 002e.b init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.308 init
|
|
[DEBUG] PNP: 002e.308 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.409 init
|
|
[DEBUG] PNP: 002e.409 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.609 init
|
|
[DEBUG] PNP: 002e.609 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.709 init
|
|
[DEBUG] PNP: 002e.709 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PNP: 002e.9 init
|
|
[DEBUG] PNP: 002e.9 init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 740 / 1440 ms
|
|
[DEBUG] clear_memory: Clearing DRAM 0000000000000000-0000000000005000
|
|
[ERROR] Null dereference at eip: 0x7fea0e22
|
|
[DEBUG] clear_memory: Clearing DRAM 000000000000a000-00000000000a0000
|
|
[DEBUG] clear_memory: Clearing DRAM 00000000000c0000-000000007fe68000
|
|
[DEBUG] clear_memory: Clearing DRAM 0000000100000000-000000047a600000
|
|
[DEBUG] memset_pae: Using virtual address 0x00400000 as scratchpad
|
|
[DEBUG] init_pae_pagetables: Using address 0x00005000 for page tables
|
|
[DEBUG] clear_memory: Clearing DRAM 0000000000005000-000000000000a000
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 735 / 53 ms
|
|
[INFO ] POST: 0x76
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[DEBUG] read 6008 from 07e4
|
|
[DEBUG] wrote 5006 to 0874
|
|
[DEBUG] wrote 01 to 0878
|
|
[DEBUG] wrote 02 to 0879
|
|
[DEBUG] wrote 03 to 087a
|
|
[DEBUG] wrote 05 to 087b
|
|
[DEBUG] wrote 20 to 087c
|
|
[DEBUG] wrote 9f to 087d
|
|
[DEBUG] wrote d8 to 087e
|
|
[DEBUG] wrote 0b to 087f
|
|
[DEBUG] wrote b32d to 0876
|
|
[INFO ] Devices finalized
|
|
[INFO ] Timestamp - device setup done: 64339362021
|
|
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 52 ms
|
|
[INFO ] POST: 0x77
|
|
[INFO ] Timestamp - cbmem post: 64380736613
|
|
[DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 7 ms
|
|
[INFO ] POST: 0x79
|
|
[INFO ] Timestamp - write tables: 64421109901
|
|
[INFO ] POST: 0x9c
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x2ec80 size 0x2332 in mcache @0x7ffdc158
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7fe3c000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] Supported C-states: C0 C1 C1E C3 C6
|
|
[DEBUG] PSS: 2901MHz power 65000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 50690 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 45377 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 40306 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 35383 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 30693 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 2901MHz power 65000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 50690 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 45377 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 40306 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 35383 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 30693 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 2901MHz power 65000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 50690 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 45377 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 40306 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 35383 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 30693 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 2901MHz power 65000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 50690 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 45377 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 40306 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 35383 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 30693 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x47a600000, len = 0xb85a00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] ACPI: * SPCR
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] current = 7fe3fc30
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[DEBUG] current = 7fe3fcc0
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 7/32, length now 92
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 15616 bytes.
|
|
[DEBUG] smbios_write_tables: 7fe34000
|
|
[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.03-250-g59e4095ecfcb-dirty'
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[DEBUG] SMBIOS tables: 956 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7ff8
|
|
[DEBUG] Writing coreboot table at 0x7fe60000
|
|
[INFO ] CBFS: Found 'cmos_layout.bin' @0x31680 size 0x5ac in mcache @0x7ffdc1dc
|
|
[DEBUG] CFR: Written 16 bytes of CFR structures at 0x7fe605dc, with CRC32 0x00000000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000007fe33fff: RAM
|
|
[DEBUG] 6. 000000007fe34000-000000007fe78fff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007fe79000-000000007ffcbfff: RAMSTAGE
|
|
[DEBUG] 8. 000000007ffcc000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 0000000080000000-00000000849fffff: RESERVED
|
|
[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 11. 00000000fed90000-00000000fed91fff: RESERVED
|
|
[DEBUG] 12. 0000000100000000-000000047a5fffff: RAM
|
|
[DEBUG] Wrote coreboot table at: 0x7fe60000, 0x98c bytes, checksum df11
|
|
[DEBUG] coreboot table: 2468 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
|
|
[DEBUG] TIME STAMP 3. 0x7ffdd000 0x00000910
|
|
[DEBUG] RO MCACHE 4. 0x7ffdc000 0x000003d0
|
|
[DEBUG] MEM INFO 5. 0x7ffdb000 0x00000f48
|
|
[DEBUG] AFTER CAR 6. 0x7ffcc000 0x0000f000
|
|
[DEBUG] RAMSTAGE 7. 0x7fe78000 0x00154000
|
|
[DEBUG] SMM BACKUP 8. 0x7fe68000 0x00010000
|
|
[DEBUG] COREBOOT 9. 0x7fe60000 0x00008000
|
|
[DEBUG] ACPI 10. 0x7fe3c000 0x00024000
|
|
[DEBUG] SMBIOS 11. 0x7fe34000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7fffeb20 0x000000e0
|
|
[DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004
|
|
[DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8
|
|
[DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100
|
|
[INFO ] Timestamp - finalize chips: 66283089553
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 646 ms
|
|
[INFO ] POST: 0x7a
|
|
[INFO ] Timestamp - starting to load payload: 66324214645
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x51000 size 0x11c61 in mcache @0x7ffdc298
|
|
[DEBUG] Checking segment from ROM address 0xffa6122c
|
|
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
|
|
[DEBUG] Checking segment from ROM address 0xffa61248
|
|
[DEBUG] Loading segment from ROM address 0xffa6122c
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x000de1a0 memsize 0x21e60 srcaddr 0xffa61264 filesize 0x11c29
|
|
[DEBUG] Loading Segment: addr: 0x000de1a0 memsz: 0x0000000000021e60 filesz: 0x0000000000011c29
|
|
[DEBUG] using LZMA
|
|
[INFO ] Timestamp - starting LZMA decompress (ignore for x86): 66505518801
|
|
[INFO ] Timestamp - finished LZMA decompress (ignore for x86): 66589639489
|
|
[DEBUG] Loading segment from ROM address 0xffa61248
|
|
[DEBUG] Entry Point 0x000fd246
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 21 / 89 ms
|
|
[INFO ] POST: 0x7b
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x000fd246(0x7fe60000)
|
|
[INFO ] POST: 0xf8
|
|
[INFO ] Timestamp - selfboot jump: 66699733245
|
|
SeaBIOS (version rel-1.16.3-0-ga6ed6b7)
|
|
BUILD: gcc: (coreboot toolchain v2024-08-28_0abdb8b8a9) 14.2.0 binutils: (GNU Binutils) 2.43.1
|
|
SeaBIOS (version rel-1.16.3-0-ga6ed6b7)
|
|
BUILD: gcc: (coreboot toolchain v2024-08-28_0abdb8b8a9) 14.2.0 binutils: (GNU Binutils) 2.43.1
|
|
Found coreboot cbmem console @ 7ffde000
|
|
Found mainboard ASUS P8Z77-V
|
|
Relocating init from 0x000df900 to 0x7ee26c20 (size 54080)
|
|
Found CBFS header at 0xffa1022c
|
|
multiboot: eax=0, ebx=7d8
|
|
Found 23 PCI devices (max PCI bus is 09)
|
|
Copying SMBIOS from 0x7fe34000 to 0x000f5b40
|
|
Copying SMBIOS 3.0 from 0x7fe34020 to 0x000f5b20
|
|
Copying ACPI RSDP from 0x7fe3c000 to 0x000f5af0
|
|
table(50434146)=0x7fe3e5d0 (via xsdt)
|
|
Using pmtimer, ioport 0x508
|
|
Scan for VGA option rom
|
|
No VGA found, scan for other display
|
|
Running option rom at c000:0003
|
|
Start SeaVGABIOS (version rel-1.16.3-0-ga6ed6b7)
|
|
VGABUILD: gcc: (coreboot toolchain v2024-08-28_0abdb8b8a9) 14.2.0 binutils: (GNU Binutils) 2.43.1
|
|
enter vga_post:
|
|
a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000
|
|
si=00000000 di=000066e0 bp=00000000 sp=00006da2 cs=f000 ip=cff4 f=0000
|
|
coreboot vga init
|
|
Did not find coreboot framebuffer - assuming EGA text
|
|
Attempting to allocate 512 bytes lowmem via pmm call to f000:d06c
|
|
pmm call arg1=0
|
|
VGA stack allocated at ec180
|
|
Hooking hardware timer irq (old=f000fea5 new=c0003ef8)
|
|
sercon: using ioport 0x3f8
|
|
sercon: configuring in splitmode (vgabios c000:3e1f)
|
|
Turning on vga text mode console
|
|
set VGA mode 3
|
|
SeaBIOS (version rel-1.16.3-0-ga6ed6b7PCI: XHCI at 00:14.0 (mmio 0xefbd0000)
|
|
XHCI init: regs @ 0xefbd0000, 8 ports, 32 slots, 32 byte contexts
|
|
XHCI protocol USB 2.00, 4 ports (offset 1), def 3001
|
|
XHCI protocol USB 3.00, 4 ports (offset 5), def 1000
|
|
XHCI extcap 0xc1 @ 0xefbd8040
|
|
XHCI extcap 0xc0 @ 0xefbd8070
|
|
XHCI extcap 0x1 @ 0xefbd8330
|
|
)
|
|
PCI: XHCI at 05:00.0 (mmio 0xeff00000)
|
|
XHCI init: regs @ 0xeff00000, 4 ports, 64 slots, 64 byte contexts
|
|
XHCI extcap 0x1 @ 0xeff01000
|
|
XHCI protocol USB 2.00, 2 ports (offset 1), def 0
|
|
XHCI protocol USB 3.00, 2 ports (offset 3), def 0
|
|
PCI: XHCI at 09:00.0 (mmio 0xefc00000)
|
|
XHCI init: regs @ 0xefc00000, 4 ports, 32 slots, 32 byte contexts
|
|
XHCI extcap 0x1 @ 0xefc00800
|
|
XHCI protocol USB 3.00, 2 ports (offset 1), def 0
|
|
XHCI protocol USB 2.00, 2 ports (offset 3), def 1
|
|
EHCI init on dev 00:1a.0 (regs=0xefbc9020)
|
|
EHCI init on dev 00:1d.0 (regs=0xefbc8020)
|
|
AHCI controller at 00:1f.2, iobase 0xefbca000, irq 11
|
|
AHCI controller at 04:00.0, iobase 0xefe10000, irq 11
|
|
AHCI controller at 06:00.0, iobase 0xefd00000, irq 11
|
|
Searching bootorder for: HALT
|
|
Found 0 lpt ports
|
|
Found 1 serial ports
|
|
Searching bootorder for: /rom@img/grub2
|
|
Searching bootorder for: /rom@img/nvramcui
|
|
Searching bootorder for: /rom@img/coreinfo
|
|
XHCI no devices found
|
|
XHCI no devices found
|
|
XHCI port #3: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
|
|
USB mouse initialized
|
|
Initialized USB HUB (0 ports used)
|
|
Initialized USB HUB (0 ports used)
|
|
PS2 keyboard initialized
|
|
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
|
|
AHCI/0: Set transfer mode to UDMA-5
|
|
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
|
|
AHCI/0: registering: "AHCI/0: ADATA SP600 ATA-9 Hard-Disk (30533 MiBytes)"
|
|
All threads complete.
|
|
Scan for option roms
|
|
|
|
Press ESC for boot menu.
|
|
|
|
Searching bootorder for: HALT
|
|
drive 0x000f5a40: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=62533296
|
|
Space available for UMB: c7800-eb000, f5360-f5a40
|
|
Returned 16683008 bytes of ZoneHigh
|
|
e820 map has 8 items:
|
|
0: 0000000000000000 - 000000000009fc00 = 1 RAM
|
|
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
|
|
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
|
|
3: 0000000000100000 - 000000007fe1d000 = 1 RAM
|
|
4: 000000007fe1d000 - 0000000084a00000 = 2 RESERVED
|
|
5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
|
|
6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
|
|
7: 0000000100000000 - 000000047a600000 = 1 RAM
|
|
enter handle_19:
|
|
NULL
|
|
Booting from Hard Disk..Booting from 0000:7c00
|
|
.
|
|
GRUB loading.
|
|
Welcome to GRUB!
|
|
|
|
VBE current mode=3
|
|
stub vbe_104fXX:435:
|
|
a=00004f11 b=00000001 c=0007fbcc d=00000004 ds=0000 es=6000 ss=ec18
|
|
si=0007fbac di=00008080 bp=00001ff0 sp=000001f6 cs=0000 ip=9104 f=0202
|
|
set VGA mode 12
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
set VGA mode 3
|