
[NOTE ]  coreboot-24.08-1645-gb83fac3e1c74-dirty Fri Feb 28 02:19:33 UTC 2025 x86_32 ramstage starting (log level: 7)...
[INFO ]  POST: 0x39
[INFO ]  Timestamp - start of ramstage: 46633795361
[INFO ]  POST: 0x6f
[DEBUG]  Normal boot
[INFO ]  POST: 0x70
[DEBUG]  BS: BS_PRE_DEVICE run times (exec / console): 0 / 3 ms
[INFO ]  POST: 0x71
[INFO ]  Timestamp - device enumeration: 46696721439
[DEBUG]  BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 8 ms
[INFO ]  POST: 0x72
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 00000000 enabled
[DEBUG]  DOMAIN: 00000000 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 00
[INFO ]  POST: 0x24
[DEBUG]  PCI: 00:00:00.0 [8086/0150] enabled
[DEBUG]  PCI: 00:00:01.0 [8086/0151] enabled
[INFO ]  PCI: Static device PCI: 00:00:01.1 not found, disabling it.
[DEBUG]  PCI: 00:00:01.2 [0000/0000] hidden
[DEBUG]  PCI: 00:00:02.0 [8086/0162] enabled
[DEBUG]  PCI: 00:00:04.0 [0000/0000] hidden
[DEBUG]  PCI: 00:00:06.0 [0000/0000] hidden
[DEBUG]  PCI: 00:00:14.0 [8086/1e31] enabled
[DEBUG]  PCI: 00:00:16.0 [8086/1e3a] enabled
[DEBUG]  PCI: 00:00:16.1: Disabling device
[DEBUG]  PCI: 00:00:16.2: Disabling device
[DEBUG]  PCI: 00:00:16.3: Disabling device
[DEBUG]  PCI: 00:00:19.0 [8086/1503] enabled
[DEBUG]  PCI: 00:00:1a.0 [8086/1e2d] enabled
[DEBUG]  PCI: 00:00:1b.0 [8086/1e20] enabled
[DEBUG]  PCI: 00:00:1c.0: Found a downstream device
[DEBUG]  PCI: 00:00:1c.0 [8086/1e10] enabled
[DEBUG]  PCI: 00:00:1c.1: No downstream device
[DEBUG]  PCI: 00:00:1c.1: Disabling device
[DEBUG]  PCI: 00:00:1c.1 [8086/1e12] disabled
[DEBUG]  PCI: 00:00:1c.2: No downstream device
[DEBUG]  PCI: 00:00:1c.2: Disabling device
[DEBUG]  PCI: 00:00:1c.2 [8086/1e14] disabled
[DEBUG]  PCI: 00:00:1c.3: Found a downstream device
[DEBUG]  PCI: 00:00:1c.3 [8086/1e16] enabled
[DEBUG]  PCI: 00:00:1c.4: Found a downstream device
[DEBUG]  PCI: 00:00:1c.4 [8086/1e18] enabled
[DEBUG]  PCI: 00:00:1c.5: No downstream device
[DEBUG]  PCI: 00:00:1c.5: Disabling device
[DEBUG]  PCI: 00:00:1c.5 [8086/1e1a] disabled
[DEBUG]  PCI: 00:00:1c.6: No downstream device
[DEBUG]  PCI: 00:00:1c.6: Disabling device
[DEBUG]  PCI: 00:00:1c.6 [8086/1e1c] disabled
[DEBUG]  PCI: 00:00:1c.7: Found a downstream device
[DEBUG]  PCI: 00:00:1c.7 [8086/1e1e] enabled
[DEBUG]  PCI: 00:00:1d.0 [8086/1e26] enabled
[DEBUG]  PCI: 00:00:1e.0: Disabling device
[DEBUG]  PCI: 00:00:1e.0 [8086/244e] disabled
[DEBUG]  PCI: 00:00:1f.0 [8086/1e44] enabled
[DEBUG]  PCI: 00:00:1f.2 [8086/1e00] enabled
[DEBUG]  PCI: 00:00:1f.3 [8086/1e22] enabled
[DEBUG]  PCI: 00:00:1f.5: Disabling device
[DEBUG]  PCI: 00:00:1f.5 [8086/1e08] disabled No operations
[DEBUG]  PCI: 00:00:1f.6: Disabling device
[DEBUG]  PCI: 00:00:1f.6 [8086/1e24] disabled No operations
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:00:01.1
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:00:01.0 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 01
[INFO ]  POST: 0x24
[INFO ]  POST: 0x25
[INFO ]  PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:01.0 finished in 19 msecs
[DEBUG]  PCI: 00:00:01.2 scanning...
[DEBUG]  scan_bus: bus PCI: 00:00:01.2 finished in 0 msecs
[DEBUG]  PCI: 00:00:04.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:00:04.0 finished in 0 msecs
[DEBUG]  PCI: 00:00:06.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:00:06.0 finished in 0 msecs
[DEBUG]  PCI: 00:00:1c.0 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 02
[INFO ]  POST: 0x24
[DEBUG]  PCI: 00:02:00.0 [197b/2392] enabled
[DEBUG]  PCI: 00:02:00.2 [197b/2391] enabled
[DEBUG]  PCI: 00:02:00.3 [197b/2393] enabled
[DEBUG]  PCI: 00:02:00.4 [197b/2394] enabled
[INFO ]  POST: 0x25
[INFO ]  Enabling Common Clock Configuration
[INFO ]  PCIE CLK PM is not supported by endpoint
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:02:00.0: No LTR support
[INFO ]  PCIe: Common Clock Configuration already enabled
[INFO ]  PCIE CLK PM is not supported by endpoint
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:02:00.2: No LTR support
[INFO ]  PCIe: Common Clock Configuration already enabled
[INFO ]  PCIE CLK PM is not supported by endpoint
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:02:00.3: No LTR support
[INFO ]  PCIe: Common Clock Configuration already enabled
[INFO ]  PCIE CLK PM is not supported by endpoint
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:02:00.4: No LTR support
[INFO ]  PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:1c.0 finished in 110 msecs
[DEBUG]  PCI: 00:00:1c.3 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 03
[INFO ]  POST: 0x24
[INFO ]  POST: 0x25
[INFO ]  PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port
[WARN ]  PCI: 00:00:1c.3: Has a slow downstream device. Enumeration failed.
[DEBUG]  scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs
[DEBUG]  PCI: 00:00:1c.4 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 04
[INFO ]  POST: 0x24
[DEBUG]  PCI: 00:04:00.0 subordinate PCI
[DEBUG]  PCI: 00:04:00.0 [1b21/1080] enabled
[DEBUG]  PCI: 00:04:00.0 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 05
[INFO ]  POST: 0x24
[INFO ]  POST: 0x25
[DEBUG]  scan_bus: bus PCI: 00:04:00.0 finished in 10 msecs
[INFO ]  POST: 0x25
[INFO ]  PCIE CLK PM is not supported by endpoint
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:04:00.0: No LTR support
[INFO ]  PCI: 00:00:1c.4: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:1c.4 finished in 61 msecs
[DEBUG]  PCI: 00:00:1c.7 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 06
[INFO ]  POST: 0x24
[DEBUG]  PCI: 00:06:00.0 [1b21/1042] enabled
[INFO ]  POST: 0x25
[INFO ]  Enabling Common Clock Configuration
[INFO ]  PCIE CLK PM is not supported by endpoint
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:06:00.0: No LTR support
[INFO ]  PCI: 00:00:1c.7: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:1c.7 finished in 41 msecs
[DEBUG]  PCI: 00:00:1f.0 scanning...
[DEBUG]  PNP: 002e.1 disabled
[DEBUG]  PNP: 002e.2 enabled
[DEBUG]  PNP: 002e.3 disabled
[DEBUG]  PNP: 002e.5 enabled
[DEBUG]  PNP: 002e.6 disabled
[DEBUG]  PNP: 002e.7 disabled
[DEBUG]  PNP: 002e.8 disabled
[DEBUG]  PNP: 002e.108 enabled
[DEBUG]  PNP: 002e.109 enabled
[DEBUG]  PNP: 002e.209 enabled
[DEBUG]  PNP: 002e.309 enabled
[DEBUG]  PNP: 002e.509 enabled
[DEBUG]  PNP: 002e.a enabled
[DEBUG]  PNP: 002e.b enabled
[DEBUG]  PNP: 002e.d disabled
[DEBUG]  PNP: 002e.e disabled
[DEBUG]  PNP: 002e.f disabled
[DEBUG]  PNP: 002e.14 disabled
[DEBUG]  PNP: 002e.16 disabled
[DEBUG]  PNP: 0c31.0 enabled
[DEBUG]  PNP: 002e.308 enabled
[DEBUG]  PNP: 002e.409 enabled
[DEBUG]  PNP: 002e.609 enabled
[DEBUG]  PNP: 002e.709 enabled
[DEBUG]  PNP: 002e.9 enabled
[DEBUG]  scan_bus: bus PCI: 00:00:1f.0 finished in 84 msecs
[DEBUG]  PCI: 00:00:1f.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
[INFO ]  POST: 0x25
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 681 msecs
[DEBUG]  scan_bus: bus Root Device finished in 698 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 714 ms
[DEBUG]  BM-LOCKDOWN: Enabling boot media protection scheme 'readonly' using CTRL...
[DEBUG]  read 6000 from 07e4
[DEBUG]  wrote 00000004 to 0890
[DEBUG]  read 03040003 from 0894
[DEBUG]  wrote 00001000 to 0890
[DEBUG]  read 09300024 from 0894
[DEBUG]  read 00000000 from 0880
[DEBUG]  wrote 00000000 to 0880
[DEBUG]  read 0080 from 0870
[DEBUG]  wrote 000c to 0870
[DEBUG]  read 6000 from 07e4
[DEBUG]  wrote 9f to 0878
[DEBUG]  read 0000 from 0876
[DEBUG]  wrote 0000 to 0876
[DEBUG]  read 0000 from 0874
[DEBUG]  wrote 00000000 to 07e8
[DEBUG]  wrote 44 to 0872
[DEBUG]  wrote 02 to 0871
[DEBUG]  read 0084 from 0870
[DEBUG]  wrote 0004 to 0870
[DEBUG]  read 001740ef from 07f0
[DEBUG]  read 00 from 07f4
[DEBUG]  wrote 0000 to 0874
[INFO ]  Manufacturer: ef
[INFO ]  SF: Detected ef 4017 with sector size 0x1000, total 0x800000
[INFO ]  spi_flash_protect: FPR 0 is enabled for range 0x00000000-0x007fffff
[INFO ]  BM-LOCKDOWN: Enabled bootmedia protection
[DEBUG]  BS: BS_DEV_RESOURCES entry times (exec / console): 0 / 104 ms
[INFO ]  POST: 0x73
[INFO ]  Timestamp - device configuration: 49157175399
[DEBUG]  found VGA at PCI: 00:00:02.0
[DEBUG]  Setting up VGA for PCI: 00:00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
[DEBUG]  TOUUD 0x47b600000 TOLUD 0x84a00000 TOM 0x400000000
[DEBUG]  MEBASE 0x7ffff00000
[DEBUG]  IGD decoded, subtracting 64M UMA and 2M GTT
[DEBUG]  TSEG base 0x80000000 size 8M
[INFO ]  Available memory below 4GB: 2048M
[INFO ]  Available memory above 4GB: 14262M
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
[DEBUG]   PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]   PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 00:02:00.0 30 *  [0x0 - 0xffff] mem
[DEBUG]    PCI: 00:02:00.0 10 *  [0x10000 - 0x100ff] mem
[DEBUG]    PCI: 00:02:00.2 10 *  [0x11000 - 0x110ff] mem
[DEBUG]    PCI: 00:02:00.3 10 *  [0x12000 - 0x120ff] mem
[DEBUG]    PCI: 00:02:00.4 10 *  [0x13000 - 0x130ff] mem
[DEBUG]   PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]   PCI: 00:00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]   PCI: 00:00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:00:1c.7 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]   PCI: 00:00:1c.7 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:00:1c.7 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 00:06:00.0 10 *  [0x0 - 0x7fff] mem
[DEBUG]   PCI: 00:00:1c.7 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ]  === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.b 62 base 00000000 limit 00000001 io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
[INFO ]   DOMAIN: 00000000: Resource ranges:
[INFO ]   * Base: 1000, Size: f000, Tag: 100
[DEBUG]    PCI: 00:00:02.0 20 *  [0xffc0 - 0xffff] limit: ffff io
[DEBUG]    PCI: 00:00:19.0 18 *  [0xffa0 - 0xffbf] limit: ffbf io
[DEBUG]    PCI: 00:00:1f.2 20 *  [0xff80 - 0xff9f] limit: ff9f io
[ERROR]  Resource didn't fit!!!
[DEBUG]    PNP: 002e.308 60 *  size: 0x8 limit: fff io
[DEBUG]    PCI: 00:00:1f.2 10 *  [0xff78 - 0xff7f] limit: ff7f io
[DEBUG]    PCI: 00:00:1f.2 18 *  [0xff70 - 0xff77] limit: ff77 io
[DEBUG]    PCI: 00:00:1f.2 14 *  [0xff6c - 0xff6f] limit: ff6f io
[DEBUG]    PCI: 00:00:1f.2 1c *  [0xff68 - 0xff6b] limit: ff6b io
[DEBUG]  DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff
[DEBUG]  DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 05 base 100000000 limit 47b5fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 06 base 80000000 limit 849fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 09 base fed90000 limit fed90fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 0a base fed91000 limit fed91fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
[INFO ]   DOMAIN: 00000000: Resource ranges:
[INFO ]   * Base: 84a00000, Size: 6b600000, Tag: 200
[INFO ]   * Base: 47b600000, Size: b84a00000, Tag: 200
[DEBUG]    PCI: 00:00:02.0 18 *  [0xe0000000 - 0xefffffff] limit: efffffff prefmem
[DEBUG]    PCI: 00:00:02.0 10 *  [0xdfc00000 - 0xdfffffff] limit: dfffffff mem
[DEBUG]    PCI: 00:00:1c.0 20 *  [0xdfb00000 - 0xdfbfffff] limit: dfbfffff mem
[DEBUG]    PCI: 00:00:1c.7 20 *  [0xdfa00000 - 0xdfafffff] limit: dfafffff mem
[DEBUG]    PCI: 00:00:19.0 10 *  [0xdf9e0000 - 0xdf9fffff] limit: df9fffff mem
[DEBUG]    PCI: 00:00:14.0 10 *  [0xdf9d0000 - 0xdf9dffff] limit: df9dffff mem
[DEBUG]    PCI: 00:00:1b.0 10 *  [0xdf9cc000 - 0xdf9cffff] limit: df9cffff mem
[DEBUG]    PCI: 00:00:19.0 14 *  [0xdf9cb000 - 0xdf9cbfff] limit: df9cbfff mem
[DEBUG]    PCI: 00:00:1f.2 24 *  [0xdf9ca000 - 0xdf9ca7ff] limit: df9ca7ff mem
[DEBUG]    PCI: 00:00:1a.0 10 *  [0xdf9c9000 - 0xdf9c93ff] limit: df9c93ff mem
[DEBUG]    PCI: 00:00:1d.0 10 *  [0xdf9c8000 - 0xdf9c83ff] limit: df9c83ff mem
[DEBUG]    PCI: 00:00:1f.3 10 *  [0xdf9c7000 - 0xdf9c70ff] limit: df9c70ff mem
[DEBUG]    PCI: 00:00:16.0 10 *  [0xdf9c6000 - 0xdf9c600f] limit: df9c600f mem
[DEBUG]  DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff done
[DEBUG]  DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
[DEBUG]    PCI: 00:02:00.0 10 *  [0xdfb10000 - 0xdfb100ff] limit: dfb100ff mem
[DEBUG]    PCI: 00:02:00.0 30 *  [0xdfb00000 - 0xdfb0ffff] limit: dfb0ffff mem
[DEBUG]    PCI: 00:02:00.2 10 *  [0xdfb11000 - 0xdfb110ff] limit: dfb110ff mem
[DEBUG]    PCI: 00:02:00.3 10 *  [0xdfb12000 - 0xdfb120ff] limit: dfb120ff mem
[DEBUG]    PCI: 00:02:00.4 10 *  [0xdfb13000 - 0xdfb130ff] limit: dfb130ff mem
[DEBUG]    PCI: 00:06:00.0 10 *  [0xdfa00000 - 0xdfa07fff] limit: dfa07fff mem
[INFO ]  === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
[DEBUG]  PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
[DEBUG]  PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
[DEBUG]  PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
[DEBUG]  PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64
[DEBUG]  PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:00:14.0 10 <- [0x00000000df9d0000 - 0x00000000df9dffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:00:16.0 10 <- [0x00000000df9c6000 - 0x00000000df9c600f] size 0x00000010 gran 0x04 mem64
[DEBUG]  PCI: 00:00:19.0 10 <- [0x00000000df9e0000 - 0x00000000df9fffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 00:00:19.0 14 <- [0x00000000df9cb000 - 0x00000000df9cbfff] size 0x00001000 gran 0x0c mem
[DEBUG]  PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 00:00:1a.0 10 <- [0x00000000df9c9000 - 0x00000000df9c93ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PCI: 00:00:1b.0 10 <- [0x00000000df9cc000 - 0x00000000df9cffff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
[DEBUG]  PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
[DEBUG]  PCI: 00:00:1c.0 20 <- [0x00000000dfb00000 - 0x00000000dfbfffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem
[DEBUG]  PCI: 00:02:00.0 10 <- [0x00000000dfb10000 - 0x00000000dfb100ff] size 0x00000100 gran 0x08 mem
[DEBUG]  PCI: 00:02:00.0 30 <- [0x00000000dfb00000 - 0x00000000dfb0ffff] size 0x00010000 gran 0x10 romem
[DEBUG]  PCI: 00:02:00.2 10 <- [0x00000000dfb11000 - 0x00000000dfb110ff] size 0x00000100 gran 0x08 mem
[DEBUG]  PCI: 00:02:00.3 10 <- [0x00000000dfb12000 - 0x00000000dfb120ff] size 0x00000100 gran 0x08 mem
[DEBUG]  PCI: 00:02:00.4 10 <- [0x00000000dfb13000 - 0x00000000dfb130ff] size 0x00000100 gran 0x08 mem
[DEBUG]  PCI: 00:00:1c.3 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io
[DEBUG]  PCI: 00:00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
[DEBUG]  PCI: 00:00:1c.3 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 mem
[DEBUG]  PCI: 00:00:1c.4 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 04 io
[DEBUG]  PCI: 00:00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem
[DEBUG]  PCI: 00:00:1c.4 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 mem
[DEBUG]  PCI: 00:04:00.0 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c seg 00 bus 05 io
[DEBUG]  PCI: 00:04:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 prefmem
[DEBUG]  PCI: 00:04:00.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 mem
[DEBUG]  PCI: 00:00:1c.7 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 06 io
[DEBUG]  PCI: 00:00:1c.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 06 prefmem
[DEBUG]  PCI: 00:00:1c.7 20 <- [0x00000000dfa00000 - 0x00000000dfafffff] size 0x00100000 gran 0x14 seg 00 bus 06 mem
[DEBUG]  PCI: 00:06:00.0 10 <- [0x00000000dfa00000 - 0x00000000dfa07fff] size 0x00008000 gran 0x0f mem64
[DEBUG]  PCI: 00:00:1d.0 10 <- [0x00000000df9c8000 - 0x00000000df9c83ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
[DEBUG]  PNP: 002e.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
[DEBUG]  PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
[DEBUG]  PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
[DEBUG]  PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
[DEBUG]  PNP: 002e.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
[DEBUG]  PNP: 002e.5 f0 <- [0x0000000000000082 - 0x0000000000000081] size 0x00000000 gran 0x00 drq
[DEBUG]  PNP: 002e.209 e0 <- [0x00000000000000df - 0x00000000000000de] size 0x00000000 gran 0x00 drq
[NOTE ]  PNP: 002e.509 f4 irq size: 0x0000000001 not assigned in devicetree
[NOTE ]  PNP: 002e.509 f5 irq size: 0x0000000001 not assigned in devicetree
[DEBUG]  PNP: 002e.a e3 <- [0x0000000000000004 - 0x0000000000000003] size 0x00000000 gran 0x00 drq
[DEBUG]  PNP: 002e.a e7 <- [0x0000000000000011 - 0x0000000000000010] size 0x00000000 gran 0x00 drq
[DEBUG]  PNP: 002e.a f2 <- [0x000000000000005d - 0x000000000000005d] size 0x00000001 gran 0x00 drq
[DEBUG]  PNP: 002e.b 60 <- [0x0000000000000290 - 0x0000000000000291] size 0x00000002 gran 0x01 io
[DEBUG]  PNP: 002e.b 62 <- [0x0000000000000000 - 0x0000000000000001] size 0x00000002 gran 0x01 io
[DEBUG]  PNP: 002e.b 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq
[NOTE ]  PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree
[NOTE ]  PNP: 002e.308 60 io size: 0x0000000008 not assigned in devicetree
[NOTE ]  PNP: 002e.609 f4 irq size: 0x0000000001 not assigned in devicetree
[NOTE ]  PNP: 002e.609 f5 irq size: 0x0000000001 not assigned in devicetree
[DEBUG]  PCI: 00:00:1f.2 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:00:1f.2 14 <- [0x000000000000ff6c - 0x000000000000ff6f] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:00:1f.2 18 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:00:1f.2 1c <- [0x000000000000ff68 - 0x000000000000ff6b] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 00:00:1f.2 24 <- [0x00000000df9ca000 - 0x00000000df9ca7ff] size 0x00000800 gran 0x0b mem
[DEBUG]  PCI: 00:00:1f.3 10 <- [0x00000000df9c7000 - 0x00000000df9c70ff] size 0x00000100 gran 0x08 mem64
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1313 ms
[INFO ]  POST: 0x74
[INFO ]  Timestamp - device enable: 52993356872
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00:00.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:00.0 cmd <- 06
[DEBUG]  PCI: 00:00:01.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:01.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:01.0 cmd <- 00
[DEBUG]  PCI: 00:00:02.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:02.0 cmd <- 03
[DEBUG]  PCI: 00:00:14.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:14.0 cmd <- 102
[DEBUG]  PCI: 00:00:16.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:16.0 cmd <- 02
[DEBUG]  PCI: 00:00:19.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:19.0 cmd <- 103
[DEBUG]  PCI: 00:00:1a.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1a.0 cmd <- 102
[DEBUG]  PCI: 00:00:1b.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1b.0 cmd <- 102
[DEBUG]  PCI: 00:00:1c.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1c.0 cmd <- 106
[DEBUG]  PCI: 00:00:1c.3 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.3 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1c.3 cmd <- 100
[DEBUG]  PCI: 00:00:1c.4 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.4 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1c.4 cmd <- 100
[DEBUG]  PCI: 00:00:1c.7 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.7 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1c.7 cmd <- 106
[DEBUG]  PCI: 00:00:1d.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1d.0 cmd <- 102
[DEBUG]  PCI: 00:00:1f.0 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1f.0 cmd <- 107
[DEBUG]  PCI: 00:00:1f.2 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1f.2 cmd <- 03
[DEBUG]  PCI: 00:00:1f.3 subsystem <- 1043/84ca
[DEBUG]  PCI: 00:00:1f.3 cmd <- 103
[DEBUG]  PCI: 00:02:00.0 cmd <- 06
[DEBUG]  PCI: 00:02:00.2 cmd <- 06
[DEBUG]  PCI: 00:02:00.3 cmd <- 06
[DEBUG]  PCI: 00:02:00.4 cmd <- 06
[DEBUG]  PCI: 00:04:00.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:04:00.0 cmd <- 00
[DEBUG]  PCI: 00:06:00.0 cmd <- 02
[INFO ]  done.
[DEBUG]  BS: BS_DEV_ENABLE run times (exec / console): 1 / 204 ms
[DEBUG]  read 6000 from 07e4
[DEBUG]  wrote 00000004 to 0890
[DEBUG]  read 03040003 from 0894
[DEBUG]  wrote 00001000 to 0890
[DEBUG]  read 09300024 from 0894
[DEBUG]  read 00000000 from 0880
[DEBUG]  wrote 00000000 to 0880
[DEBUG]  BS: BS_DEV_INIT entry times (exec / console): 0 / 25 ms
[INFO ]  POST: 0x75
[INFO ]  Timestamp - device initialization: 53696091745
[INFO ]  Initializing devices...
[INFO ]  POST: 0x75
[DEBUG]  CPU_CLUSTER: 0 init
[INFO ]  LAPIC 0x0 switched to X2APIC mode.
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
[DEBUG]  0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0
[DEBUG]  0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1
[DEBUG]  0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0
[DEBUG]  0x0000000100000000 - 0x000000047b5fffff size 0x37b600000 type 6
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 4/5.
[DEBUG]  MTRR: WB selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
[DEBUG]  MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0
[DEBUG]  MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
[DEBUG]  MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[INFO ]  POST: 0x93
[DEBUG]  CPU has 4 cores, 4 threads enabled.
[DEBUG]  Setting up SMI for CPU
[INFO ]  Will perform SMM setup.
[DEBUG]  microcode: sig=0x306a9 pf=0x2 revision=0x21
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x6800 in mcache @0x7ffdd02c
[INFO ]  CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
[INFO ]  LAPIC 0x0 in X2APIC mode.
[DEBUG]  CPU: APIC: 00 enabled
[DEBUG]  CPU: APIC: 01 enabled
[DEBUG]  CPU: APIC: 02 enabled
[DEBUG]  CPU: APIC: 03 enabled
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 16 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 3 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x2 switched to X2APIC mode.
[INFO ]  AP: slot 1 apic_id 2, MCU rev: 0x00000021
[INFO ]  LAPIC 0x6 switched to X2APIC mode.
[INFO ]  LAPIC 0x4 switched to X2APIC mode.
[INFO ]  AP: slot 3 apic_id 6, MCU rev: 0x00000021
[INFO ]  AP: slot 2 apic_id 4, MCU rev: 0x00000021
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG]  Processing 9 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x80001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x7fe974c3
[DEBUG]  Installing permanent SMM handler to 0x80000000
[DEBUG]  HANDLER      [0x802fe000-0x802ffd37]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x802fdc00-0x802fdfff]
[DEBUG]    stub0      [0x802f6000-0x802f619f]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x802fd800-0x802fdbff]
[DEBUG]    stub1      [0x802f5c00-0x802f5d9f]

[DEBUG]  CPU 2
[DEBUG]    ss2        [0x802fd400-0x802fd7ff]
[DEBUG]    stub2      [0x802f5800-0x802f599f]

[DEBUG]  CPU 3
[DEBUG]    ss3        [0x802fd000-0x802fd3ff]
[DEBUG]    stub3      [0x802f5400-0x802f559f]

[DEBUG]  stacks       [0x80000000-0x80000fff]
[DEBUG]  Loading module at 0x802fe000 with entry 0x802fe77f. filesize: 0x1cd0 memsize: 0x1d38
[DEBUG]  Processing 78 relocs. Offset value of 0x802fe000
[DEBUG]  Loading module at 0x802f6000 with entry 0x802f6000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG]  Processing 9 relocs. Offset value of 0x802f6000
[DEBUG]  smm_module_setup_stub: stack_top = 0x80001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x300000
[DEBUG]  SMM Module: placing smm entry code at 802f5c00,  cpu # 0x1
[DEBUG]  SMM Module: placing smm entry code at 802f5800,  cpu # 0x2
[DEBUG]  SMM Module: placing smm entry code at 802f5400,  cpu # 0x3
[DEBUG]  SMM Module: stub loaded at 802f6000. Will call 0x802fe77f
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ee000, cpu = 0
[DEBUG]  In relocation handler: cpu 0
[DEBUG]  New SMBASE=0x802ee000 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed800, cpu = 2
[DEBUG]  In relocation handler: cpu 2
[DEBUG]  New SMBASE=0x802ed800 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed400, cpu = 3
[DEBUG]  In relocation handler: cpu 3
[DEBUG]  New SMBASE=0x802ed400 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802edc00, cpu = 1
[DEBUG]  In relocation handler: cpu 1
[DEBUG]  New SMBASE=0x802edc00 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[INFO ]  CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT supported
[INFO ]  CPU: VT supported
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL already locked
[INFO ]  APIC: 00: PP0 current limit not set in devicetree
[INFO ]  APIC: 00: PP0 PSI0 not set in devicetree
[INFO ]  APIC: 00: PP0 PSI1 not set in devicetree
[INFO ]  APIC: 00: PP0 PSI2 not set in devicetree
[INFO ]  APIC: 00: PP1 current limit not set in devicetree
[INFO ]  APIC: 00: PP1 PSI0 not set in devicetree
[INFO ]  APIC: 00: PP1 PSI1 not set in devicetree
[INFO ]  APIC: 00: PP1 PSI2 not set in devicetree
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 2900
[INFO ]  Turbo is available but hidden
[INFO ]  Turbo is available and visible
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #2
[INFO ]  Initializing CPU #3
[INFO ]  Initializing CPU #1
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[INFO ]  CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
[INFO ]  CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: Intel(R) Core(TM) i5-3475S CPU @ 2.90GHz.
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT supported
[INFO ]  CPU: VT supported
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT supported
[INFO ]  CPU: VT supported
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[INFO ]  CPU: cpuid(1) 0x306a9
[DEBUG]  IA32_FEATURE_CONTROL already locked
[DEBUG]  IA32_FEATURE_CONTROL already locked
[DEBUG]  cpu: energy policy set to 6
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT supported
[INFO ]  CPU: VT supported
[DEBUG]  model_x06ax: frequency set to 2900
[INFO ]  CPU #1 initialized
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG]  model_x06ax: frequency set to 2900
[INFO ]  CPU #3 initialized
[DEBUG]  IA32_FEATURE_CONTROL already locked
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 2900
[INFO ]  CPU #2 initialized
[INFO ]  bsp_do_flight_plan done after 598 msecs.
[DEBUG]  SMI_STS: 
[DEBUG]  GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 
[DEBUG]  ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 
[DEBUG]  TCO_STS: 
[DEBUG]  Locking SMM.
[DEBUG]  CPU_CLUSTER: 0 init finished in 905 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:00.0 init
[DEBUG]  Disabling PEG11.
[DEBUG]  Disabling Device 7.
[DEBUG]  Set BIOS_RESET_CPL
[DEBUG]  CPU TDP: 65 Watts
[DEBUG]  PCI: 00:00:00.0 init finished in 13 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:01.0 init
[DEBUG]  PCI: 00:00:01.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:02.0 init
[INFO ]  CBFS: Found 'vbt.bin' @0x33080 size 0x4e1 in mcache @0x7ffdd184
[INFO ]  Timestamp - starting LZMA decompress (ignore for x86): 56566791807
[INFO ]  Timestamp - finished LZMA decompress (ignore for x86): 56589222911
[INFO ]  Found a VBT of 3902 bytes
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[DEBUG]  GT Power Management Init
[DEBUG]  IVB GT2 35W Power Meter Weights
[DEBUG]  GT Power Management Init (post VBIOS)
[3.478974] HW.GFX.GMA.Initialize
[3.481898] HW.GFX.GMA.Panel.Setup_PP_Sequencer
[3.486045] HW.GFX.GMA.Panel.Setup_PP_Sequencer
[3.490196] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS
[3.497286] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
[3.504463] HW.GFX.GMA.Registers.Read:  0x00186904 <- 0x000c7210:PCH_PP_DIVISOR
[3.511380] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS
[3.517432] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS
[3.524522] HW.GFX.GMA.Registers.Write: 0x48340001 -> 0x000c7208:PCH_PP_ON_DELAYS
[3.531612] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS
[3.537751] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
[3.544927] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS
[3.552103] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR
[3.557983] HW.GFX.GMA.Registers.Read:  0x00186904 <- 0x000c7210:PCH_PP_DIVISOR
[3.564898] HW.GFX.GMA.Registers.Write: 0x00186904 -> 0x000c7210:PCH_PP_DIVISOR
[3.571817] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL
[3.577696] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c7204:PCH_PP_CONTROL
[3.584613] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL
[3.591532] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_LVDS
[3.596286] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000e1180:PCH_LVDS
[3.602684] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
[3.607872] HW.GFX.GMA.Registers.Read:  0x00000018 <- 0x00064000:DDI_BUF_CTL_A
[3.614702] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB
[3.619545] HW.GFX.GMA.Registers.Read:  0x0000001c <- 0x000e1140:PCH_HDMIB
[3.626028] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B
[3.630785] HW.GFX.GMA.Registers.Read:  0x00000004 <- 0x000e4100:PCH_DP_B
[3.637183] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[3.642889] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c4030:SHOTPLUG_CTL
[3.649634] HW.GFX.GMA.Registers.Write: 0x00000013 -> 0x000c4030:SHOTPLUG_CTL
[3.656378] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC
[3.661219] HW.GFX.GMA.Registers.Read:  0x0000001c <- 0x000e1150:PCH_HDMIC
[3.667703] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C
[3.672459] HW.GFX.GMA.Registers.Read:  0x00000004 <- 0x000e4200:PCH_DP_C
[3.678857] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[3.684564] HW.GFX.GMA.Registers.Read:  0x00000010 <- 0x000c4030:SHOTPLUG_CTL
[3.691308] HW.GFX.GMA.Registers.Write: 0x00001310 -> 0x000c4030:SHOTPLUG_CTL
[3.698052] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID
[3.702893] HW.GFX.GMA.Registers.Read:  0x0000001c <- 0x000e1160:PCH_HDMID
[3.709377] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D
[3.714134] HW.GFX.GMA.Registers.Read:  0x00000004 <- 0x000e4300:PCH_DP_D
[3.720532] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[3.726239] HW.GFX.GMA.Registers.Read:  0x00001010 <- 0x000c4030:SHOTPLUG_CTL
[3.732983] HW.GFX.GMA.Registers.Write: 0x00131010 -> 0x000c4030:SHOTPLUG_CTL
[3.739829] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
[3.745805] HW.GFX.GMA.Registers.Read:  0x00002900 <- 0x00041000:CPU_VGACNTRL
[3.752549] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
[3.759293] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL
[3.766385] HW.GFX.GMA.Registers.Read:  0x00001402 <- 0x000c6200:PCH_DREF_CONTROL
[3.773476] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
[3.779441] HW.GFX.GMA.Registers.Read:  0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ
[3.786443] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ
[3.793449] HW.GFX.GMA.Display_Probing.Read_EDID
[3.797684] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
[3.803131] HW.GFX.GMA.Registers.Read:  0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.810221] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
[3.817571] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
[3.823624] HW.GFX.GMA.Registers.Read:  0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.830712] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
[3.837803] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
[3.846017] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.853106] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
[3.858554] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.865642] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
[3.872993] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
[3.879045] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.886134] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
[3.893225] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
[3.901439] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.908527] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
[3.913975] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.921064] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
[3.928414] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
[3.934467] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.941557] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
[3.948647] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
[3.956861] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[3.963951] HW.GFX.GMA.Display_Probing.Read_EDID
[3.968187] HW.GFX.GMA.I2C.I2C_Read
[3.971300] HW.GFX.GMA.I2C.Init_GMBUS
[3.974585] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[3.982281] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[3.988853] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[3.995423] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
[4.001995] HW.GFX.GMA.I2C.Check_And_Reset
[4.005712] HW.GFX.GMA.Registers.Read:  0x00008800 <- 0x000c5108:PCH_GMBUS2
[4.012282] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[4.018855] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.026550] HW.GFX.GMA.Registers.Read:  0x00008a08 <- 0x000c5108:PCH_GMBUS2
[4.033121] HW.GFX.GMA.Registers.Read:  0xffffff00 <- 0x000c510c:PCH_GMBUS3
[4.039691] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.047388] HW.GFX.GMA.Registers.Read:  0x00008a0c <- 0x000c5108:PCH_GMBUS2
[4.053958] HW.GFX.GMA.Registers.Read:  0x00ffffff <- 0x000c510c:PCH_GMBUS3
[4.060529] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.068224] HW.GFX.GMA.Registers.Read:  0x00008a10 <- 0x000c5108:PCH_GMBUS2
[4.074795] HW.GFX.GMA.Registers.Read:  0x00001863 <- 0x000c510c:PCH_GMBUS3
[4.081364] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.089061] HW.GFX.GMA.Registers.Read:  0x00008a14 <- 0x000c5108:PCH_GMBUS2
[4.095633] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c510c:PCH_GMBUS3
[4.102202] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.109899] HW.GFX.GMA.Registers.Read:  0x00008a18 <- 0x000c5108:PCH_GMBUS2
[4.116469] HW.GFX.GMA.Registers.Read:  0x03011e06 <- 0x000c510c:PCH_GMBUS3
[4.123040] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.130735] HW.GFX.GMA.Registers.Read:  0x00008a1c <- 0x000c5108:PCH_GMBUS2
[4.137307] HW.GFX.GMA.Registers.Read:  0x78000080 <- 0x000c510c:PCH_GMBUS3
[4.143878] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.151573] HW.GFX.GMA.Registers.Read:  0x00008a20 <- 0x000c5108:PCH_GMBUS2
[4.158143] HW.GFX.GMA.Registers.Read:  0xa2a5d70a <- 0x000c510c:PCH_GMBUS3
[4.164714] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.172411] HW.GFX.GMA.Registers.Read:  0x00008a24 <- 0x000c5108:PCH_GMBUS2
[4.178980] HW.GFX.GMA.Registers.Read:  0x24964a59 <- 0x000c510c:PCH_GMBUS3
[4.185551] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.193246] HW.GFX.GMA.Registers.Read:  0x00008a28 <- 0x000c5108:PCH_GMBUS2
[4.199818] HW.GFX.GMA.Registers.Read:  0xa3545014 <- 0x000c510c:PCH_GMBUS3
[4.206388] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.214085] HW.GFX.GMA.Registers.Read:  0x00008a2c <- 0x000c5108:PCH_GMBUS2
[4.220655] HW.GFX.GMA.Registers.Read:  0xc0810008 <- 0x000c510c:PCH_GMBUS3
[4.227226] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.234923] HW.GFX.GMA.Registers.Read:  0x00008a30 <- 0x000c5108:PCH_GMBUS2
[4.241493] HW.GFX.GMA.Registers.Read:  0x01010101 <- 0x000c510c:PCH_GMBUS3
[4.248064] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.255760] HW.GFX.GMA.Registers.Read:  0x00008a34 <- 0x000c5108:PCH_GMBUS2
[4.262330] HW.GFX.GMA.Registers.Read:  0x01010101 <- 0x000c510c:PCH_GMBUS3
[4.268901] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.276598] HW.GFX.GMA.Registers.Read:  0x00008a38 <- 0x000c5108:PCH_GMBUS2
[4.283168] HW.GFX.GMA.Registers.Read:  0x01010101 <- 0x000c510c:PCH_GMBUS3
[4.289739] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.297436] HW.GFX.GMA.Registers.Read:  0x00008a3c <- 0x000c5108:PCH_GMBUS2
[4.304006] HW.GFX.GMA.Registers.Read:  0x21660101 <- 0x000c510c:PCH_GMBUS3
[4.310577] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.318274] HW.GFX.GMA.Registers.Read:  0x00008a40 <- 0x000c5108:PCH_GMBUS2
[4.324844] HW.GFX.GMA.Registers.Read:  0x0051aa56 <- 0x000c510c:PCH_GMBUS3
[4.331414] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.339111] HW.GFX.GMA.Registers.Read:  0x00008a44 <- 0x000c5108:PCH_GMBUS2
[4.345681] HW.GFX.GMA.Registers.Read:  0x8f46301e <- 0x000c510c:PCH_GMBUS3
[4.352252] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.359949] HW.GFX.GMA.Registers.Read:  0x00008a48 <- 0x000c5108:PCH_GMBUS2
[4.366520] HW.GFX.GMA.Registers.Read:  0x433f0033 <- 0x000c510c:PCH_GMBUS3
[4.373091] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.380786] HW.GFX.GMA.Registers.Read:  0x00008a4c <- 0x000c5108:PCH_GMBUS2
[4.387357] HW.GFX.GMA.Registers.Read:  0x1e000021 <- 0x000c510c:PCH_GMBUS3
[4.393927] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.401624] HW.GFX.GMA.Registers.Read:  0x00008a50 <- 0x000c5108:PCH_GMBUS2
[4.408194] HW.GFX.GMA.Registers.Read:  0x18803a02 <- 0x000c510c:PCH_GMBUS3
[4.414765] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.422460] HW.GFX.GMA.Registers.Read:  0x00008a54 <- 0x000c5108:PCH_GMBUS2
[4.429032] HW.GFX.GMA.Registers.Read:  0x402d3871 <- 0x000c510c:PCH_GMBUS3
[4.435602] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.443299] HW.GFX.GMA.Registers.Read:  0x00008a58 <- 0x000c5108:PCH_GMBUS2
[4.449869] HW.GFX.GMA.Registers.Read:  0x00452c58 <- 0x000c510c:PCH_GMBUS3
[4.456440] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.464137] HW.GFX.GMA.Registers.Read:  0x00008a5c <- 0x000c5108:PCH_GMBUS2
[4.470707] HW.GFX.GMA.Registers.Read:  0x0021433f <- 0x000c510c:PCH_GMBUS3
[4.477278] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.484974] HW.GFX.GMA.Registers.Read:  0x00008a60 <- 0x000c5108:PCH_GMBUS2
[4.491546] HW.GFX.GMA.Registers.Read:  0x00001a00 <- 0x000c510c:PCH_GMBUS3
[4.498115] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.505812] HW.GFX.GMA.Registers.Read:  0x00008a64 <- 0x000c5108:PCH_GMBUS2
[4.512382] HW.GFX.GMA.Registers.Read:  0x1e00fd00 <- 0x000c510c:PCH_GMBUS3
[4.518953] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.526650] HW.GFX.GMA.Registers.Read:  0x00008a68 <- 0x000c5108:PCH_GMBUS2
[4.533220] HW.GFX.GMA.Registers.Read:  0x1e5a1e4c <- 0x000c510c:PCH_GMBUS3
[4.539791] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.547487] HW.GFX.GMA.Registers.Read:  0x00008a6c <- 0x000c5108:PCH_GMBUS2
[4.554058] HW.GFX.GMA.Registers.Read:  0x20200a00 <- 0x000c510c:PCH_GMBUS3
[4.560628] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.568324] HW.GFX.GMA.Registers.Read:  0x00008a70 <- 0x000c5108:PCH_GMBUS2
[4.574894] HW.GFX.GMA.Registers.Read:  0x20202020 <- 0x000c510c:PCH_GMBUS3
[4.581465] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.589162] HW.GFX.GMA.Registers.Read:  0x00008a74 <- 0x000c5108:PCH_GMBUS2
[4.595732] HW.GFX.GMA.Registers.Read:  0xfc000000 <- 0x000c510c:PCH_GMBUS3
[4.602303] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.609998] HW.GFX.GMA.Registers.Read:  0x00008a78 <- 0x000c5108:PCH_GMBUS2
[4.616569] HW.GFX.GMA.Registers.Read:  0x41414100 <- 0x000c510c:PCH_GMBUS3
[4.623139] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.630834] HW.GFX.GMA.Registers.Read:  0x00008a7c <- 0x000c5108:PCH_GMBUS2
[4.637406] HW.GFX.GMA.Registers.Read:  0x2020200a <- 0x000c510c:PCH_GMBUS3
[4.643976] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.651672] HW.GFX.GMA.Registers.Read:  0x0000ca00 <- 0x000c5108:PCH_GMBUS2
[4.658243] HW.GFX.GMA.Registers.Read:  0x20202020 <- 0x000c510c:PCH_GMBUS3
[4.664814] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[4.672511] HW.GFX.GMA.Registers.Read:  0x0000ca00 <- 0x000c5108:PCH_GMBUS2
[4.679081] HW.GFX.GMA.Registers.Read:  0x24012020 <- 0x000c510c:PCH_GMBUS3
[4.685651] HW.GFX.GMA.Registers.Wait:  0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2
[4.693347] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1
[4.699919] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
[4.707613] HW.GFX.GMA.I2C.Release_GMBUS
[4.711159] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[4.717730] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[4.724302] EDID+0x0000:  00 ff ff ff ff ff ff 00  63 18 00 00 00 00 00 00 
[4.730872] EDID+0x0010:  06 1e 01 03 80 00 00 78  0a d7 a5 a2 59 4a 96 24 
[4.737443] EDID+0x0020:  14 50 54 a3 08 00 81 c0  01 01 01 01 01 01 01 01 
[4.744014] EDID+0x0030:  01 01 01 01 01 01 66 21  56 aa 51 00 1e 30 46 8f 
[4.750585] EDID+0x0040:  33 00 3f 43 21 00 00 1e  02 3a 80 18 71 38 2d 40 
[4.757157] EDID+0x0050:  58 2c 45 00 3f 43 21 00  00 1a 00 00 00 fd 00 1e 
[4.763728] EDID+0x0060:  4c 1e 5a 1e 00 0a 20 20  20 20 20 20 00 00 00 fc 
[4.770299] EDID+0x0070:  00 41 41 41 0a 20 20 20  20 20 20 20 20 20 01 24 
[4.776870] HW.GFX.GMA.Display_Probing.Read_EDID
[4.781106] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
[4.786554] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.793644] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
[4.800994] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
[4.807046] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.814136] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
[4.821226] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
[4.829440] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.836529] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
[4.841977] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.849065] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
[4.856415] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
[4.862468] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.869557] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
[4.876647] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
[4.884861] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.891951] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
[4.897397] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.904487] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
[4.911838] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
[4.917890] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.924981] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
[4.932071] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
[4.940285] HW.GFX.GMA.Registers.Read:  0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
[4.947373] HW.GFX.GMA.Display_Probing.Read_EDID
[4.951610] HW.GFX.GMA.I2C.I2C_Read
[4.954723] HW.GFX.GMA.I2C.Init_GMBUS
[4.958007] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[4.965703] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[4.972275] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[4.978845] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
[4.985417] HW.GFX.GMA.I2C.Check_And_Reset
[4.989134] HW.GFX.GMA.Registers.Read:  0x00008800 <- 0x000c5108:PCH_GMBUS2
[4.995705] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[5.002276] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[5.009972] HW.GFX.GMA.Registers.Read:  0x00008c00 <- 0x000c5108:PCH_GMBUS2
[5.016542] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
[5.024236] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
[5.030808] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
[5.037380] HW.GFX.GMA.I2C.Release_GMBUS
[5.040924] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[5.047496] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[5.054068] HW.GFX.GMA.Display_Probing.Read_EDID
[5.058304] HW.GFX.GMA.I2C.I2C_Read
[5.061417] HW.GFX.GMA.I2C.Init_GMBUS
[5.064703] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[5.072398] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[5.078970] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[5.085541] HW.GFX.GMA.Registers.Write: 0x00000006 -> 0x000c5100:PCH_GMBUS0
[5.092112] HW.GFX.GMA.I2C.Check_And_Reset
[5.095830] HW.GFX.GMA.Registers.Read:  0x00008000 <- 0x000c5108:PCH_GMBUS2
[5.102401] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[5.108972] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[5.116667] HW.GFX.GMA.Registers.Read:  0x00008c00 <- 0x000c5108:PCH_GMBUS2
[5.123236] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
[5.130932] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
[5.137504] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
[5.144075] HW.GFX.GMA.I2C.Release_GMBUS
[5.147619] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[5.154190] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[5.160762] HW.GFX.GMA.Display_Probing.Read_EDID
[5.164998] HW.GFX.GMA.I2C.I2C_Read
[5.168111] HW.GFX.GMA.I2C.Init_GMBUS
[5.171395] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[5.179090] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[5.185662] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[5.192233] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0
[5.198804] HW.GFX.GMA.I2C.Check_And_Reset
[5.202521] HW.GFX.GMA.Registers.Read:  0x00008000 <- 0x000c5108:PCH_GMBUS2
[5.209092] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[5.215665] HW.GFX.GMA.Registers.Wait:  0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[5.223360] HW.GFX.GMA.Registers.Read:  0x00008c00 <- 0x000c5108:PCH_GMBUS2
[5.229929] HW.GFX.GMA.Registers.Wait:  0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
[5.237625] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
[5.244197] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
[5.250768] HW.GFX.GMA.I2C.Release_GMBUS
[5.254312] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[5.260883] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2

[5.267627] CONFIG =>
[5.269529]   (Primary   =>
[5.271949]      (Port => HDMI1     ,
[5.275235]       Framebuffer =>
[5.278087]         (Width     => 1366,
[5.281546]          Height    => 768,
[5.284918]          Start_X   => 0,
[5.288116]          Start_Y   => 0,
[5.291315]          Stride    => 1376,
[5.294774]          V_Stride  => 768,
[5.298145]          Tiling    => Linear ,
[5.301863]          Rotation  => No_Rotation,
[5.305927]          Offset => 0x00000000,
[5.309643]          BPC    => 8),
[5.312669]       Mode =>
[5.314916]         (Dotclock           => 85500000,
[5.319499]          H_Visible          => 1366,
[5.323736]          H_Sync_Begin       => 1436,
[5.327973]          H_Sync_End         => 1579,
[5.332209]          H_Total            => 1792,
[5.336446]          V_Visible          => 768,
[5.340596]          V_Sync_Begin       => 771,
[5.344747]          V_Sync_End         => 774,
[5.348896]          V_Total            => 798,
[5.353047]          H_Sync_Active_High => True,
[5.357283]          V_Sync_Active_High => True,
[5.361520]          BPC                => 5)),
[5.365670]    Secondary =>
[5.368090]      (Port => Disabled  ,
[5.371375]       Framebuffer =>
[5.374227]         (Width     => 1,
[5.377426]          Height    => 1,
[5.380625]          Start_X   => 0,
[5.383824]          Start_Y   => 0,
[5.387022]          Stride    => 1,
[5.390221]          V_Stride  => 1,
[5.393420]          Tiling    => Linear ,
[5.397137]          Rotation  => No_Rotation,
[5.401201]          Offset => 0x00000000,
[5.404919]          BPC    => 8),
[5.407944]       Mode =>
[5.410193]         (Dotclock           => 1000000,
[5.414688]          H_Visible          => 1,
[5.418666]          H_Sync_Begin       => 1,
[5.422644]          H_Sync_End         => 1,
[5.426621]          H_Total            => 1,
[5.430597]          V_Visible          => 1,
[5.434575]          V_Sync_Begin       => 1,
[5.438551]          V_Sync_End         => 1,
[5.442529]          V_Total            => 1,
[5.446507]          H_Sync_Active_High => False,
[5.450829]          V_Sync_Active_High => False,
[5.455152]          BPC                => 5)),
[5.459302]    Tertiary  =>
[5.461723]      (Port => Disabled  ,
[5.465008]       Framebuffer =>
[5.467860]         (Width     => 1,
[5.471059]          Height    => 1,
[5.474259]          Start_X   => 0,
[5.477457]          Start_Y   => 0,
[5.480656]          Stride    => 1,
[5.483855]          V_Stride  => 1,
[5.487054]          Tiling    => Linear ,
[5.490771]          Rotation  => No_Rotation,
[5.494835]          Offset => 0x00000000,
[5.498553]          BPC    => 8),
[5.501580]       Mode =>
[5.503827]         (Dotclock           => 1000000,
[5.508323]          H_Visible          => 1,
[5.512299]          H_Sync_Begin       => 1,
[5.516277]          H_Sync_End         => 1,
[5.520255]          H_Total            => 1,
[5.524232]          V_Visible          => 1,
[5.528208]          V_Sync_Begin       => 1,
[5.532186]          V_Sync_End         => 1,
[5.536164]          V_Total            => 1,
[5.540140]          H_Sync_Active_High => False,
[5.544463]          V_Sync_Active_High => False,
[5.548786]          BPC                => 5)));

[5.553939] Trying to enable port HDMI1     
[5.557829] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting
[5.563103] HW.GFX.GMA.PLLs.Alloc
[5.566044] HW.GFX.GMA.PLLs.On
[5.568765] Valid clock found.
[5.571403] Best/Target/Delta: 85500000/85500000/0.
[5.575900] HW.GFX.GMA.PLLs.Program_DPLL
[5.579444] HW.GFX.GMA.Registers.Write: 0x00021307 -> 0x000c6040:PCH_FPA0
[5.585843] HW.GFX.GMA.Registers.Write: 0x00021307 -> 0x000c6044:PCH_FPA1
[5.592241] HW.GFX.GMA.Registers.Write: 0x44080008 -> 0x000c6014:PCH_DPLL_A
[5.598812] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DPLL_A
[5.604692] HW.GFX.GMA.Registers.Read:  0x44080008 <- 0x000c6014:PCH_DPLL_A
[5.611262] HW.GFX.GMA.Registers.Write: 0xc4080008 -> 0x000c6014:PCH_DPLL_A
[5.617836] HW.GFX.GMA.Registers.Read:  0xc4080008 <- 0x000c6014:PCH_DPLL_A
[5.624558] HW.GFX.GMA.Connectors.Pre_On
[5.628019] HW.GFX.GMA.Connectors.FDI.Pre_On
[5.631909] HW.GFX.GMA.Registers.Write: 0x00200090 -> 0x000f0010:FDI_RX_MISC_A
[5.638740] HW.GFX.GMA.Registers.Write: 0x7e000000 -> 0x000f0030:FDI_RXA_TUSIZE1
[5.645744] HW.GFX.GMA.Registers.Unset_Mask: 0x00000700 !S FDI_RXA_IMR
[5.651883] HW.GFX.GMA.Registers.Read:  0x00000fff <- 0x000f0018:FDI_RXA_IMR
[5.658540] HW.GFX.GMA.Registers.Write: 0x000008ff -> 0x000f0018:FDI_RXA_IMR
[5.665198] HW.GFX.GMA.Registers.Read:  0x000008ff <- 0x000f0018:FDI_RXA_IMR
[5.671854] HW.GFX.GMA.Registers.Write: 0x00000700 -> 0x000f0014:FDI_RXA_IIR
[5.678514] HW.GFX.GMA.Registers.Write: 0x00002840 -> 0x000f000c:FDI_RXA_CTL
[5.685171] HW.GFX.GMA.Registers.Read:  0x00002840 <- 0x000f000c:FDI_RXA_CTL
[5.692049] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S FDI_RXA_CTL
[5.697931] HW.GFX.GMA.Registers.Read:  0x00002840 <- 0x000f000c:FDI_RXA_CTL
[5.704588] HW.GFX.GMA.Registers.Write: 0x00002850 -> 0x000f000c:FDI_RXA_CTL
[5.711246] HW.GFX.GMA.Registers.Write: 0x00044800 -> 0x00060100:FDI_TX_CTL_A
[5.717990] HW.GFX.GMA.Registers.Read:  0x00044800 <- 0x00060100:FDI_TX_CTL_A
[5.724834] HW.GFX.GMA.Pipe_Setup.On
[5.727950] HW.GFX.GMA.Transcoder.Setup
[5.731408] HW.GFX.GMA.Transcoder.Setup_Link
[5.735299] HW.GFX.GMA.DP_Info.Calculate_M_N
[5.739189] HW.GFX.GMA.Registers.Write: 0x7e799999 -> 0x00060030:PIPEA_DATA_M1
[5.746020] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x00060034:PIPEA_DATA_N1
[5.752850] HW.GFX.GMA.Registers.Write: 0x00051111 -> 0x00060040:PIPEA_LINK_M1
[5.759681] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x00060044:PIPEA_LINK_N1
[5.766512] HW.GFX.GMA.Registers.Write: 0x06ff0555 -> 0x00060000:HTOTAL_A
[5.772911] HW.GFX.GMA.Registers.Write: 0x06ff0555 -> 0x00060004:HBLANK_A
[5.779309] HW.GFX.GMA.Registers.Write: 0x062a059b -> 0x00060008:HSYNC_A
[5.785621] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x0006000c:VTOTAL_A
[5.792021] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x00060010:VBLANK_A
[5.798419] HW.GFX.GMA.Registers.Write: 0x03050302 -> 0x00060014:VSYNC_A
[5.804730] HW.GFX.GMA.Pipe_Setup.Setup_FB
[5.808449] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
[5.814934] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
[5.821419] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
[5.827990] HW.GFX.GMA.Pipe_Setup.Setup_Display
[5.832139] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane
[5.836635] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DSPACNTR
[5.841996] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x00070180:DSPACNTR
[5.848394] HW.GFX.GMA.Registers.Write: 0x98004000 -> 0x00070180:DSPACNTR
[5.854792] HW.GFX.GMA.Registers.Write: 0x00001580 -> 0x00070188:DSPASTRIDE
[5.861363] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070184:DSPALINOFF
[5.867934] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF
[5.874591] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF
[5.880989] HW.GFX.GMA.Registers.Write: 0x055502ff -> 0x0006001c:PIPEASRC
[5.887387] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PFA_CTL_1
[5.893353] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x00068080:PFA_CTL_1
[5.899839] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068080:PFA_CTL_1
[5.906324] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068074:PFA_WIN_SZ
[5.912895] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
[5.919380] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
[5.925865] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
[5.932436] HW.GFX.GMA.Transcoder.On
[5.935634] HW.GFX.GMA.Transcoder.Configure
[5.939439] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00070008:PIPEACONF
[5.945924] HW.GFX.GMA.Registers.Read:  0x80000000 <- 0x00070008:PIPEACONF
[5.952409] HW.GFX.GMA.Connectors.Post_On
[5.956039] HW.GFX.GMA.Connectors.FDI.Post_On
[5.960017] HW.GFX.GMA.Connectors.FDI.Auto_Training
[5.964513] HW.GFX.GMA.Registers.Unset_And_Set_Mask: FDI_TX_CTL_A
[5.970218] HW.GFX.GMA.Registers.Read:  0x00044800 <- 0x00060100:FDI_TX_CTL_A
[5.976963] HW.GFX.GMA.Registers.Write: 0x80044c00 -> 0x00060100:FDI_TX_CTL_A
[5.983707] HW.GFX.GMA.Registers.Read:  0x80044c00 <- 0x00060100:FDI_TX_CTL_A
[5.990451] HW.GFX.GMA.Registers.Set_Mask: 0x80000400 .S FDI_RXA_CTL
[5.996417] HW.GFX.GMA.Registers.Read:  0x00002850 <- 0x000f000c:FDI_RXA_CTL
[6.003074] HW.GFX.GMA.Registers.Write: 0x80002c50 -> 0x000f000c:FDI_RXA_CTL
[6.009734] HW.GFX.GMA.Registers.Read:  0x80002c50 <- 0x000f000c:FDI_RXA_CTL
[6.016395] HW.GFX.GMA.Registers.Is_Set_Mask: FDI_TX_CTL_A
[6.021491] HW.GFX.GMA.Registers.Read:  0x80044c02 <- 0x00060100:FDI_TX_CTL_A
[6.028236] HW.GFX.GMA.Registers.Set_Mask: 0x0c000000 .S FDI_RXA_CTL
[6.034202] HW.GFX.GMA.Registers.Read:  0x80002c50 <- 0x000f000c:FDI_RXA_CTL
[6.040859] HW.GFX.GMA.Registers.Write: 0x8c002c50 -> 0x000f000c:FDI_RXA_CTL
[6.047517] HW.GFX.GMA.PCH.Transcoder.On
[6.051061] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DPLL_SEL
[6.056768] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000c7000:PCH_DPLL_SEL
[6.063512] HW.GFX.GMA.Registers.Write: 0x00000008 -> 0x000c7000:PCH_DPLL_SEL
[6.070256] HW.GFX.GMA.Registers.Write: 0x06ff0555 -> 0x000e0000:TRANS_HTOTAL_A
[6.077173] HW.GFX.GMA.Registers.Write: 0x06ff0555 -> 0x000e0004:TRANS_HBLANK_A
[6.084091] HW.GFX.GMA.Registers.Write: 0x062a059b -> 0x000e0008:TRANS_HSYNC_A
[6.090921] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x000e000c:TRANS_VTOTAL_A
[6.097838] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x000e0010:TRANS_VBLANK_A
[6.104755] HW.GFX.GMA.Registers.Write: 0x03050302 -> 0x000e0014:TRANS_VSYNC_A
[6.111586] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S TRANSA_CHICKEN2
[6.117897] HW.GFX.GMA.Registers.Read:  0x00000000 <- 0x000f0064:TRANSA_CHICKEN2
[6.124900] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0064:TRANSA_CHICKEN2
[6.131903] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0008:TRANSACONF
[6.138474] HW.GFX.GMA.PCH.HDMI.On
[6.141499] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_HDMIB
[6.146947] HW.GFX.GMA.Registers.Read:  0x0000001c <- 0x000e1140:PCH_HDMIB
[6.153431] HW.GFX.GMA.Registers.Write: 0x8000081c -> 0x000e1140:PCH_HDMIB
[6.159917] HW.GFX.GMA.Registers.Read:  0x8000081c <- 0x000e1140:PCH_HDMIB
[6.166400] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_HDMIB
[6.172194] HW.GFX.GMA.Registers.Read:  0x8000081c <- 0x000e1140:PCH_HDMIB
[6.178678] HW.GFX.GMA.Registers.Write: 0x8000081c -> 0x000e1140:PCH_HDMIB
[6.185165] HW.GFX.GMA.Registers.Read:  0x8000081c <- 0x000e1140:PCH_HDMIB
[6.191648] Enabled port HDMI1     
[INFO ]  framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1366 x 768, size: 4227072 at 0xe0000000
[DEBUG]  PCI: 00:00:02.0 init finished in 2777 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:14.0 init
[DEBUG]  XHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:00:14.0 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:16.0 init
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : NO
[DEBUG]  ME: Manufacturing Mode      : YES
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: Current Working State   : Initializing
[DEBUG]  ME: Current Operation State : Bring up
[DEBUG]  ME: Current Operation Mode  : Debug or Disabled by AltDisableBit
[DEBUG]  ME: Error Code              : No Error
[DEBUG]  ME: Progress Phase          : BUP Phase
[DEBUG]  ME: Power Management Event  : Pseudo-global reset
[DEBUG]  ME: Progress Phase State    : Check to see if straps say ME DISABLED
[CRIT ]  intel_me_path: mbp is not ready!
[NOTE ]  ME: BIOS path: Error
[DEBUG]  No CMOS option 'me_state'.
[DEBUG]  No CMOS option 'me_state_prev'.
[DEBUG]  ME: me_state=0, me_state_prev=0
[DEBUG]  PCI: 00:00:16.0: Disabling device
[DEBUG]  PCI: 00:00:16.0 init finished in 92 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:19.0 init
[DEBUG]  PCI: 00:00:19.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1a.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:00:1a.0 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1b.0 init
[DEBUG]  Azalia: base = 0xdf9cc000
[DEBUG]  Azalia: codec_mask = 09
[DEBUG]  azalia_audio: initializing codec #3...
[DEBUG]  azalia_audio:  - vendor/device id: 0x80862806
[DEBUG]  azalia_audio:  - verb size: 16
[DEBUG]  azalia_audio:  - verb loaded
[DEBUG]  azalia_audio: initializing codec #0...
[DEBUG]  azalia_audio:  - vendor/device id: 0x10ec0892
[DEBUG]  azalia_audio:  - verb size: 60
[DEBUG]  azalia_audio:  - verb loaded
[DEBUG]  PCI: 00:00:1b.0 init finished in 49 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1c.0 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.0 init finished in 4 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1c.3 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.3 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1c.4 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.4 init finished in 4 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1c.7 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.7 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1d.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:00:1d.0 init finished in 4 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1f.0 init
[DEBUG]  pch: lpc_init
[INFO ]  PCH: detected Z77, device id: 0x1e44, rev id 0x4
[DEBUG]  IOAPIC: Initializing IOAPIC at fec00000
[DEBUG]  IOAPIC: ID = 0x00
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at fec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[INFO ]  Set power off after power failure.
[INFO ]  NMI sources disabled.
[DEBUG]  PantherPoint PM init
[DEBUG]  RTC: failed = 0x0
[DEBUG]  RTC Init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  pch_spi_init
[DEBUG]  PCI: 00:00:1f.0 init finished in 56 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1f.2 init
[DEBUG]  SATA: Initializing...
[DEBUG]  SATA: Controller in AHCI mode.
[DEBUG]  ABAR: 0xdf9ca000
[DEBUG]  PCI: 00:00:1f.2 init finished in 10 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00:1f.3 init
[DEBUG]  PCI: 00:00:1f.3 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:02:00.0 init
[DEBUG]  PCI: 00:02:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:02:00.2 init
[DEBUG]  PCI: 00:02:00.2 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:02:00.3 init
[DEBUG]  PCI: 00:02:00.3 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:02:00.4 init
[DEBUG]  PCI: 00:02:00.4 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:06:00.0 init
[DEBUG]  PCI: 00:06:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.2 init
[DEBUG]  PNP: 002e.2 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.5 init
[DEBUG]  Keyboard init...
[DEBUG]  PS/2 keyboard initialized on primary channel
[DEBUG]  PNP: 002e.5 init finished in 424 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.108 init
[DEBUG]  PNP: 002e.108 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.109 init
[DEBUG]  PNP: 002e.109 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.209 init
[DEBUG]  PNP: 002e.209 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.309 init
[DEBUG]  PNP: 002e.309 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.509 init
[DEBUG]  PNP: 002e.509 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.a init
[DEBUG]  PNP: 002e.a init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.b init
[DEBUG]  PNP: 002e.b init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.308 init
[DEBUG]  PNP: 002e.308 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.409 init
[DEBUG]  PNP: 002e.409 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.609 init
[DEBUG]  PNP: 002e.609 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.709 init
[DEBUG]  PNP: 002e.709 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PNP: 002e.9 init
[DEBUG]  PNP: 002e.9 init finished in 0 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 3438 / 1403 ms
[DEBUG]  clear_memory: Clearing DRAM 0000000000000000-0000000000005000
[ERROR]  Null dereference at eip: 0x7fe9c0dd
[DEBUG]  clear_memory: Clearing DRAM 000000000000a000-00000000000a0000
[DEBUG]  clear_memory: Clearing DRAM 00000000000c0000-000000007fe5e000
[DEBUG]  clear_memory: Clearing DRAM 0000000100000000-000000047b600000
[DEBUG]  memset_pae: Using virtual address 0x00400000 as scratchpad
[DEBUG]  init_pae_pagetables: Using address 0x00005000 for page tables
[DEBUG]  clear_memory: Clearing DRAM 0000000000005000-000000000000a000
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 738 / 53 ms
[INFO ]  POST: 0x76
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:00:1f.0 final
[DEBUG]  read 6008 from 07e4
[DEBUG]  wrote 5006 to 0874
[DEBUG]  wrote 01 to 0878
[DEBUG]  wrote 02 to 0879
[DEBUG]  wrote 03 to 087a
[DEBUG]  wrote 05 to 087b
[DEBUG]  wrote 20 to 087c
[DEBUG]  wrote 9f to 087d
[DEBUG]  wrote d8 to 087e
[DEBUG]  wrote 0b to 087f
[DEBUG]  wrote b32d to 0876
[INFO ]  Devices finalized
[INFO ]  Timestamp - device setup done: 70195148463
[DEBUG]  BS: BS_POST_DEVICE run times (exec / console): 0 / 52 ms
[INFO ]  POST: 0x77
[INFO ]  Timestamp - cbmem post: 70236521059
[DEBUG]  BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 7 ms
[INFO ]  POST: 0x79
[INFO ]  Timestamp - write tables: 70276893463
[INFO ]  POST: 0x9c
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x30d00 size 0x231f in mcache @0x7ffdd158
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 7fe32000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  ACPI:    * FACP
[DEBUG]  ACPI: added table 1/32, length now 44
[DEBUG]  Found 1 CPU(s) with 4 core(s) each.
[DEBUG]  Supported C-states:  C0 C1 C1E C3 C6
[DEBUG]  PSS: 2901MHz power 65000 control 0x2400 status 0x2400
[DEBUG]  PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
[DEBUG]  PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
[DEBUG]  PSS: 2400MHz power 50690 control 0x1800 status 0x1800
[DEBUG]  PSS: 2200MHz power 45377 control 0x1600 status 0x1600
[DEBUG]  PSS: 2000MHz power 40306 control 0x1400 status 0x1400
[DEBUG]  PSS: 1800MHz power 35383 control 0x1200 status 0x1200
[DEBUG]  PSS: 1600MHz power 30693 control 0x1000 status 0x1000
[INFO ]  Requested C-state C7 not supported, using C6 instead
[DEBUG]  Advertising ACPI C State type C1 as CPU C1
[DEBUG]  Advertising ACPI C State type C2 as CPU C3
[DEBUG]  Advertising ACPI C State type C3 as CPU C6
[DEBUG]  PSS: 2901MHz power 65000 control 0x2400 status 0x2400
[DEBUG]  PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
[DEBUG]  PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
[DEBUG]  PSS: 2400MHz power 50690 control 0x1800 status 0x1800
[DEBUG]  PSS: 2200MHz power 45377 control 0x1600 status 0x1600
[DEBUG]  PSS: 2000MHz power 40306 control 0x1400 status 0x1400
[DEBUG]  PSS: 1800MHz power 35383 control 0x1200 status 0x1200
[DEBUG]  PSS: 1600MHz power 30693 control 0x1000 status 0x1000
[INFO ]  Requested C-state C7 not supported, using C6 instead
[DEBUG]  Advertising ACPI C State type C1 as CPU C1
[DEBUG]  Advertising ACPI C State type C2 as CPU C3
[DEBUG]  Advertising ACPI C State type C3 as CPU C6
[DEBUG]  PSS: 2901MHz power 65000 control 0x2400 status 0x2400
[DEBUG]  PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
[DEBUG]  PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
[DEBUG]  PSS: 2400MHz power 50690 control 0x1800 status 0x1800
[DEBUG]  PSS: 2200MHz power 45377 control 0x1600 status 0x1600
[DEBUG]  PSS: 2000MHz power 40306 control 0x1400 status 0x1400
[DEBUG]  PSS: 1800MHz power 35383 control 0x1200 status 0x1200
[DEBUG]  PSS: 1600MHz power 30693 control 0x1000 status 0x1000
[INFO ]  Requested C-state C7 not supported, using C6 instead
[DEBUG]  Advertising ACPI C State type C1 as CPU C1
[DEBUG]  Advertising ACPI C State type C2 as CPU C3
[DEBUG]  Advertising ACPI C State type C3 as CPU C6
[DEBUG]  PSS: 2901MHz power 65000 control 0x2400 status 0x2400
[DEBUG]  PSS: 2900MHz power 65000 control 0x1d00 status 0x1d00
[DEBUG]  PSS: 2600MHz power 56259 control 0x1a00 status 0x1a00
[DEBUG]  PSS: 2400MHz power 50690 control 0x1800 status 0x1800
[DEBUG]  PSS: 2200MHz power 45377 control 0x1600 status 0x1600
[DEBUG]  PSS: 2000MHz power 40306 control 0x1400 status 0x1400
[DEBUG]  PSS: 1800MHz power 35383 control 0x1200 status 0x1200
[DEBUG]  PSS: 1600MHz power 30693 control 0x1000 status 0x1000
[INFO ]  Requested C-state C7 not supported, using C6 instead
[DEBUG]  Advertising ACPI C State type C1 as CPU C1
[DEBUG]  Advertising ACPI C State type C2 as CPU C3
[DEBUG]  Advertising ACPI C State type C3 as CPU C6
[DEBUG]  PCI space above 4GB MMIO is at 0x47b600000, len = 0xb84a00000
[DEBUG]  Generating ACPI PIRQ entries
[DEBUG]  ACPI:    * SSDT
[DEBUG]  ACPI: added table 2/32, length now 52
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 60
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  ACPI:    * APIC
[DEBUG]  ACPI: added table 4/32, length now 68
[DEBUG]  ACPI:    * SPCR
[DEBUG]  ACPI: added table 5/32, length now 76
[DEBUG]  current = 7fe35c20
[DEBUG]  ACPI:     * DMAR
[DEBUG]  ACPI: added table 6/32, length now 84
[DEBUG]  current = 7fe35ce0
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 7/32, length now 92
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 15648 bytes.
[DEBUG]  smbios_write_tables: 7fe2a000
[DEBUG]  SMBIOS firmware version is set to coreboot_version: '24.08-1645-gb83fac3e1c74-dirty'
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[DEBUG]  SMBIOS tables: 995 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 1ff9
[DEBUG]  Writing coreboot table at 0x7fe56000
[INFO ]  CBFS: Found 'cmos_layout.bin' @0x33700 size 0x52c in mcache @0x7ffdd1dc
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000f5fff: RESERVED
[DEBUG]   3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
[DEBUG]   4. 00000000000f7000-00000000000fffff: RESERVED
[DEBUG]   5. 0000000000100000-000000007fe29fff: RAM
[DEBUG]   6. 000000007fe2a000-000000007fe71fff: CONFIGURATION TABLES
[DEBUG]   7. 000000007fe72000-000000007ffcafff: RAMSTAGE
[DEBUG]   8. 000000007ffcb000-000000007fffffff: CONFIGURATION TABLES
[DEBUG]   9. 0000000080000000-00000000849fffff: RESERVED
[DEBUG]  10. 00000000f0000000-00000000f3ffffff: RESERVED
[DEBUG]  11. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG]  12. 0000000100000000-000000047b5fffff: RAM
[DEBUG]  Wrote coreboot table at: 0x7fe56000, 0x93c bytes, checksum e0b5
[DEBUG]  coreboot table: 2388 bytes.
[DEBUG]  IMD ROOT    0. 0x7ffff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x7fffe000 0x00001000
[DEBUG]  CONSOLE     2. 0x7ffde000 0x00020000
[DEBUG]  RO MCACHE   3. 0x7ffdd000 0x000003d0
[DEBUG]  TIME STAMP  4. 0x7ffdc000 0x00000910
[DEBUG]  MEM INFO    5. 0x7ffdb000 0x00000f48
[DEBUG]  AFTER CAR   6. 0x7ffcb000 0x00010000
[DEBUG]  RAMSTAGE    7. 0x7fe71000 0x0015a000
[DEBUG]  SMM BACKUP  8. 0x7fe61000 0x00010000
[DEBUG]  IGD OPREGION 9. 0x7fe5e000 0x00003000
[DEBUG]  COREBOOT   10. 0x7fe56000 0x00008000
[DEBUG]  ACPI       11. 0x7fe32000 0x00024000
[DEBUG]  SMBIOS     12. 0x7fe2a000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x7fffec00 0x00000400
[DEBUG]    FMAP        1. 0x7fffeb20 0x000000e0
[DEBUG]    ROMSTAGE    2. 0x7fffeb00 0x00000004
[DEBUG]    ROMSTG STCK 3. 0x7fffea40 0x000000a8
[DEBUG]    ACPI GNVS   4. 0x7fffe940 0x00000100
[INFO ]  Timestamp - finalize chips: 72129272139
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 3 / 643 ms
[INFO ]  POST: 0x7a
[INFO ]  Timestamp - starting to load payload: 72170397691
[INFO ]  CBFS: Found 'fallback/payload' @0x53900 size 0x11c61 in mcache @0x7ffdd298
[DEBUG]  Checking segment from ROM address 0xff883b2c
[DEBUG]  Payload being loaded at below 1MiB without region being marked as RAM usable.
[DEBUG]  Checking segment from ROM address 0xff883b48
[DEBUG]  Loading segment from ROM address 0xff883b2c
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x000de1a0 memsize 0x21e60 srcaddr 0xff883b64 filesize 0x11c29
[DEBUG]  Loading Segment: addr: 0x000de1a0 memsz: 0x0000000000021e60 filesz: 0x0000000000011c29
[DEBUG]  using LZMA
[INFO ]  Timestamp - starting LZMA decompress (ignore for x86): 72351700515
[INFO ]  Timestamp - finished LZMA decompress (ignore for x86): 72435808667
[DEBUG]  Loading segment from ROM address 0xff883b48
[DEBUG]    Entry Point 0x000fd246
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 21 / 89 ms
[INFO ]  POST: 0x7b
[DEBUG]  ICH-NM10-PCH: watchdog disabled
[DEBUG]  Jumping to boot code at 0x000fd246(0x7fe56000)
[INFO ]  POST: 0xf8
[INFO ]  Timestamp - selfboot jump: 72545915051
SeaBIOS (version rel-1.16.3-0-ga6ed6b7)
BUILD: gcc: (coreboot toolchain v2024-08-28_0abdb8b8a9) 14.2.0 binutils: (GNU Binutils) 2.43.1
Found coreboot cbmem console @ 7ffde000
Found mainboard ASUS P8Z77-V
Relocating init from 0x000df900 to 0x7ee1cc20 (size 54080)
Found CBFS header at 0xff83022c
multiboot: eax=7feba7bc, ebx=7feba784
Found 21 PCI devices (max PCI bus is 06)
Copying SMBIOS from 0x7fe2a000 to 0x000f5b40
Copying SMBIOS 3.0 from 0x7fe2a020 to 0x000f5b20
Copying ACPI RSDP from 0x7fe32000 to 0x000f5af0
table(50434146)=0x7fe345c0 (via xsdt)
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
pmm call arg1=0
sercon: using ioport 0x3f8
sercon: configuring in splitmode (vgabios c000:3e1f)
Turning on vga text mode console
PCI: XHCI at 00:14.0 (mmio 0xdf9d0000)
XHCI init: regs @ 0xdf9d0000, 8 ports, 32 slots, 32 byte contexts
XHCI    protocol USB  2.00, 4 ports (offset 1), def 3001
XHCI    protocol USB  3.00, 4 ports (offset 5), def 1000
XHCI    extcap 0xc1 @ 0xdf9d8040
XHCI    extcap 0xc0 @ 0xdf9d8070
XHCI    extcap 0x1 @ 0xdf9d8330
PCI: XHCI at 06:00.0 (mmio 0xdfa00000)
XHCI init: regs @ 0xdfa00000, 4 ports, 32 slots, 32 byte contexts
XHCI    extcap 0x1 @ 0xdfa00800
XHCI    protocol USB  3.00, 2 ports (offset 1), def 0
XHCI    protocol USB  2.00, 2 ports (offset 3), def 1
EHCI init on dev 00:1a.0 (regs=0xdf9c9020)
EHCI init on dev 00:1d.0 (regs=0xdf9c8020)
AHCI controller at 00:1f.2, iobase 0xdf9ca000, irq 11
Searching bootorder for: /pci@i0cf8/pci-bridge@1c/*@0,2
Searching bootorder for: HALT
Found 0 lpt ports
Found 1 serial ports
Searching bootorder for: /rom@img/grub2
Searching bootorder for: /rom@img/nvramcui
Searching bootorder for: /rom@img/coreinfo
XHCI no devices found
XHCI port #3: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
USB mouse initialized
Initialized USB HUB (0 ports used)
Initialized USB HUB (0 ports used)
PS2 keyboard initialized
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
AHCI/0: Set transfer mode to UDMA-5
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
AHCI/0: registering: "AHCI/0: ADATA SP600 ATA-9 Hard-Disk (30533 MiBytes)"
All threads complete.
Scan for option roms
Searching bootorder for: HALT
drive 0x000f5a80: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=62533296
Space available for UMB: c7800-eb000, f5360-f5a80
Returned 16703488 bytes of ZoneHigh
e820 map has 8 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000007fe18000 = 1 RAM
  4: 000000007fe18000 - 0000000084a00000 = 2 RESERVED
  5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
  6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
  7: 0000000100000000 - 000000047b600000 = 1 RAM
enter handle_19:
  NULL
Booting from 0000:7c00
