Bug #128
closedskylake common gpio differences on purism
0%
Description
## Changes that apply to all
- Native with RX/TX disabled -> Native without RX/TX disabled.
this is irrelevant since PGIO RX/TX disable bits are ignored in native mode
- All NC pads became GPI (done on purpose for some reason)
See https://review.coreboot.org/#/c/19759/59/src/soc/intel/common/block/include/intelblocks/gpio_defs.h@232
## Side by side diff with comments
CPU: ID 0x406e3, Processor Type 0x0, Family 0x6, Model 0x4e, CPU: ID 0x406e3, Processor Type 0x0, Family 0x6, Model 0x4e,
Northbridge: 8086:1904 (unknown) Northbridge: 8086:1904 (unknown)
Southbridge: 8086:9d48 (Sunrise Point Low Power PCH-U Premium Southbridge: 8086:9d48 (Sunrise Point Low Power PCH-U Premium
IGD: 8086:1916 (unknown) IGD: 8086:1916 (unknown)
Trying to reveal Primary to Sideband Bridge (P2SB), Trying to reveal Primary to Sideband Bridge (P2SB),
let's hope the OS doesn't mind... done. let's hope the OS doesn't mind... done.
SBREG_BAR = 0xfd000000 (MEM) SBREG_BAR = 0xfd000000 (MEM)
P2SB Control = 0x80030007 P2SB Control = 0x80030007
Endpoint 0xac is posted. Endpoint 0xac is posted.
Endpoint 0xad is posted. Endpoint 0xad is posted.
Endpoint 0xae is posted. Endpoint 0xae is posted.
Endpoint 0xaf is posted. Endpoint 0xaf is posted.
Endpoint 0xc4 is posted. Endpoint 0xc4 is posted.
Endpoint 0xba is disabled and locked. Endpoint 0xba is disabled and locked.
Endpoint 0xbb is disabled and locked. Endpoint 0xbb is disabled and locked.
Endpoint 0xbc is disabled and locked. Endpoint 0xbc is disabled and locked.
Endpoint 0xbd is disabled and locked. Endpoint 0xbd is disabled and locked.
Endpoint 0xfe is disabled and locked. Endpoint 0xfe is disabled and locked.
Endpoint 0xff is disabled and locked. Endpoint 0xff is disabled and locked.
Hiding Primary to Sideband Bridge (P2SB). Hiding Primary to Sideband Bridge (P2SB).
============= GPIOS ============= ============= GPIOS =============
------- GPIO Community 0 ------- ------- GPIO Community 0 -------
PCR Port ID: 0xaf0000 PCR Port ID: 0xaf0000
MSC Configuration: 0x43203 MSC Configuration: 0x43203
GPIO Dynamic Local Clock Gating : Enabled GPIO Dynamic Local Clock Gating : Enabled
GPIO Dynamic Partition Clock Gating : Enabled GPIO Dynamic Partition Clock Gating : Enabled
GPIO Static Local Clock Gating : Disabled GPIO Static Local Clock Gating : Disabled
GPIO Driver IRQ Route : IRQ14 GPIO Driver IRQ Route : IRQ14
GPE DW0 : C GPE DW0 : C
GPE DW1 : D GPE DW1 : D
GPE DW2 : E GPE DW2 : E
------- GPIO Group GPP_A ------- ------- GPIO Group GPP_A -------
0x0400: 0x0000001844000702 GPP_A0 RCIN# | 0x0400: 0x0000001840000402 GPP_A0 RCIN# DRIVE0 -> LEVEL
0x0408: 0x0000001944000702 GPP_A1 LAD0 | 0x0408: 0x0000001940000402 GPP_A1 LAD0 DRIVE0 -> LEVEL
0x0410: 0x0000001a44000702 GPP_A2 LAD1 | 0x0410: 0x0000001a40000402 GPP_A2 LAD1 DRIVE0 -> LEVEL
0x0418: 0x0000001b44000702 GPP_A3 LAD2 | 0x0418: 0x0000001b40000402 GPP_A3 LAD2 DRIVE0 -> LEVEL
0x0420: 0x0000001c44000702 GPP_A4 LAD3 | 0x0420: 0x0000001c40000402 GPP_A4 LAD3 DRIVE0 -> LEVEL
0x0428: 0x0000001d44000700 GPP_A5 LFRAME# | 0x0428: 0x0000001d40000400 GPP_A5 LFRAME# DRIVE0 -> LEVEL
0x0430: 0x0000001e44000702 GPP_A6 SERIRQ | 0x0430: 0x0000001e40000400 GPP_A6 SERIRQ DRIVE0 -> LEVEL
0x0438: 0x0000001f44000301 GPP_A7 GPIO | 0x0438: 0x0000001f40000102 GPP_A7 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0440: 0x0000002044000700 GPP_A8 CLKRUN# | 0x0440: 0x0000002040000400 GPP_A8 CLKRUN# DRIVE0 -> LEVEL
0x0448: 0x0000002144000700 GPP_A9 CLKOUT_LPC0 | 0x0448: 0x0000002140000400 GPP_A9 CLKOUT_LPC0 DRIVE0 -> LEVEL
0x0450: 0x0000002244000700 GPP_A10 CLKOUT_LPC1 | 0x0450: 0x0000002240000400 GPP_A10 CLKOUT_LPC1 DRIVE0 -> LEVEL
0x0458: 0x0000002340000300 GPP_A11 GPIO | 0x0458: 0x0000002340000102 GPP_A11 GPIO NC -> GPI
0x0460: 0x0000002444000301 GPP_A12 GPIO | 0x0460: 0x0000002440000102 GPP_A12 GPIO DRIVE0 -> LEVEL
0x0468: 0x0000002544000700 GPP_A13 SUSWARN#/SUSPWRDNACK | 0x0468: 0x0000002540000400 GPP_A13 SUSWARN#/SUSPWRDNACK DRIVE0 -> LEVEL
0x0470: 0x0000002644000700 GPP_A14 SUS_STAT# | 0x0470: 0x0000002640000400 GPP_A14 SUS_STAT# DRIVE0 -> LEVEL
0x0478: 0x0000102744000700 GPP_A15 SUS_ACK# | 0x0478: 0x0000102740000400 GPP_A15 SUS_ACK# DRIVE0 -> LEVEL
0x0480: 0x0000002844000300 GPP_A16 GPIO | 0x0480: 0x0000002840000102 GPP_A16 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0488: 0x0000002944000700 GPP_A17 ISH_GP7 | 0x0488: 0x0000002940000400 GPP_A17 ISH_GP7 DRIVE0 -> LEVEL
0x0490: 0x0000002a44000300 GPP_A18 GPIO | 0x0490: 0x0000002a40000102 GPP_A18 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0498: 0x0000002b44000300 GPP_A19 GPIO | 0x0498: 0x0000002b40000102 GPP_A19 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04a0: 0x0000002c44000300 GPP_A20 GPIO | 0x04a0: 0x0000002c40000102 GPP_A20 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04a8: 0x0000002d44000300 GPP_A21 GPIO | 0x04a8: 0x0000002d40000102 GPP_A21 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04b0: 0x0000002e44000301 GPP_A22 GPIO | 0x04b0: 0x0000002e40000102 GPP_A22 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04b8: 0x0000002f40000300 GPP_A23 GPIO | 0x04b8: 0x0000002f40000102 GPP_A23 GPIO NC -> GPI
------- GPIO Group GPP_B ------- ------- GPIO Group GPP_B -------
0x04c0: 0x0000003044000300 GPP_B0 GPIO | 0x04c0: 0x0000003040000102 GPP_B0 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04c8: 0x0000003144000300 GPP_B1 GPIO | 0x04c8: 0x0000003140000102 GPP_B1 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04d0: 0x0000003244000300 GPP_B2 GPIO | 0x04d0: 0x0000003240000102 GPP_B2 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04d8: 0x0000003340000300 GPP_B3 GPIO | 0x04d8: 0x0000003340000102 GPP_B3 GPIO NC -> GPI
0x04e0: 0x0000003444000301 GPP_B4 GPIO | 0x04e0: 0x0000003440000102 GPP_B4 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04e8: 0x0000003540000702 GPP_B5 SRCCLKREQ0# | 0x04e8: 0x0000003540000402 GPP_B5 SRCCLKREQ0#
0x04f0: 0x0000003644000702 GPP_B6 SRCCLKREQ1# | 0x04f0: 0x0000003640000402 GPP_B6 SRCCLKREQ1# DRIVE0 -> LEVEL
0x04f8: 0x0000003744000702 GPP_B7 SRCCLKREQ2# | 0x04f8: 0x0000003740000402 GPP_B7 SRCCLKREQ2# DRIVE0 -> LEVEL
0x0500: 0x0000003844000702 GPP_B8 SRCCLKREQ3# | 0x0500: 0x0000003840000402 GPP_B8 SRCCLKREQ3# DRIVE0 -> LEVEL
0x0508: 0x0000003944000702 GPP_B9 SRCCLKREQ4# | 0x0508: 0x0000003940000402 GPP_B9 SRCCLKREQ4# DRIVE0 -> LEVEL
0x0510: 0x0000003a44000702 GPP_B10 SRCCLKREQ5# | 0x0510: 0x0000003a40000402 GPP_B10 SRCCLKREQ5# DRIVE0 -> LEVEL
0x0518: 0x0000003b44000300 GPP_B11 GPIO | 0x0518: 0x0000003b40000102 GPP_B11 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0520: 0x0000003c44000700 GPP_B12 SLP_S0# | 0x0520: 0x0000003c40000400 GPP_B12 SLP_S0# DRIVE0 -> LEVEL
0x0528: 0x0000003d44000700 GPP_B13 PLTRST# | 0x0528: 0x0000003d40000400 GPP_B13 PLTRST# DRIVE0 -> LEVEL
0x0530: 0x0000103e44000201 GPP_B14 GPIO | 0x0530: 0x0000103e40000201 GPP_B14 GPIO DRIVE0 -> LEVEL
0x0538: 0x0000003f44000300 GPP_B15 GPIO | 0x0538: 0x0000003f40000102 GPP_B15 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0540: 0x0000004040800300 GPP_B16 GPIO | 0x0540: 0x0000004040000102 GPP_B16 GPIO NC -> GPI, RXINV->
0x0548: 0x0000004142800300 GPP_B17 GPIO | 0x0548: 0x0000004140000102 GPP_B17 GPIO EDGE -> LEVEL, NC -> GPI
0x0550: 0x0000304280880102 GPP_B18 GPIO 0x0550: 0x0000304280880102 GPP_B18 GPIO
0x0558: 0x0000004344000300 GPP_B19 GPIO | 0x0558: 0x0000004340000102 GPP_B19 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0560: 0x0000004444000300 GPP_B20 GPIO | 0x0560: 0x0000004440000102 GPP_B20 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0568: 0x0000004544000300 GPP_B21 GPIO | 0x0568: 0x0000004540000102 GPP_B21 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0570: 0x0000104644000700 GPP_B22 GSPIO_MOSI | 0x0570: 0x0000104640000400 GPP_B22 GSPIO_MOSI DRIVE0 -> LEVEL
0x0578: 0x0000104744000201 GPP_B23 GPIO | 0x0578: 0x0000104740000201 GPP_B23 GPIO DRIVE0 -> LEVEL
------- GPIO Community 1 ------- ------- GPIO Community 1 -------
PCR Port ID: 0xae0000 PCR Port ID: 0xae0000
MSC Configuration: 0x43203 MSC Configuration: 0x43203
GPIO Dynamic Local Clock Gating : Enabled GPIO Dynamic Local Clock Gating : Enabled
GPIO Dynamic Partition Clock Gating : Enabled GPIO Dynamic Partition Clock Gating : Enabled
GPIO Static Local Clock Gating : Disabled GPIO Static Local Clock Gating : Disabled
GPIO Driver IRQ Route : IRQ14 GPIO Driver IRQ Route : IRQ14
GPE DW0 : C GPE DW0 : C
GPE DW1 : D GPE DW1 : D
GPE DW2 : E GPE DW2 : E
------- GPIO Group GPP_C ------- ------- GPIO Group GPP_C -------
0x0400: 0x0000004844000702 GPP_C0 SMBCLK | 0x0400: 0x0000004840000402 GPP_C0 SMBCLK DRIVE0 -> LEVEL
0x0408: 0x0000104944000702 GPP_C1 SMBDATA | 0x0408: 0x0000104940000402 GPP_C1 SMBDATA DRIVE0 -> LEVEL
0x0410: 0x0000104a44000201 GPP_C2 GPIO | 0x0410: 0x0000104a40000201 GPP_C2 GPIO DRIVE0 -> LEVEL
0x0418: 0x0000004b44000702 GPP_C3 SML0CLK | 0x0418: 0x0000004b40000402 GPP_C3 SML0CLK DRIVE0 -> LEVEL
0x0420: 0x0000004c44000702 GPP_C4 SML0DATA | 0x0420: 0x0000004c40000402 GPP_C4 SML0DATA DRIVE0 -> LEVEL
0x0428: 0x0000104d40900100 GPP_C5 GPIO 0x0428: 0x0000104d40900100 GPP_C5 GPIO
0x0430: 0xffffffffffffffff GPP_C6 RESERVED 0x0430: 0xffffffffffffffff GPP_C6 RESERVED
0x0438: 0xffffffffffffffff GPP_C7 RESERVED 0x0438: 0xffffffffffffffff GPP_C7 RESERVED
0x0440: 0x0000005044000702 GPP_C8 UART0_RXD | 0x0440: 0x0000005040000402 GPP_C8 UART0_RXD DRIVE0 -> LEVEL
0x0448: 0x0000005144000700 GPP_C9 UART0_TXD | 0x0448: 0x0000005140000400 GPP_C9 UART0_TXD DRIVE0 -> LEVEL
0x0450: 0x0000005244000700 GPP_C10 UART0_RTS# | 0x0450: 0x0000005240000400 GPP_C10 UART0_RTS# DRIVE0 -> LEVEL
0x0458: 0x0000005344000702 GPP_C11 UART0_CTS# | 0x0458: 0x0000005340000402 GPP_C11 UART0_CTS# DRIVE0 -> LEVEL
0x0460: 0x0000005444000300 GPP_C12 GPIO | 0x0460: 0x0000005440000102 GPP_C12 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0468: 0x0000005544000300 GPP_C13 GPIO | 0x0468: 0x0000005540000102 GPP_C13 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0470: 0x0000005644000300 GPP_C14 GPIO | 0x0470: 0x0000005640000102 GPP_C14 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0478: 0x0000005744000300 GPP_C15 GPIO | 0x0478: 0x0000005740000100 GPP_C15 GPIO DRIVE0 -> LEVEL
0x0480: 0x0000005844000100 GPP_C16 GPIO | 0x0480: 0x0000005840000100 GPP_C16 GPIO DRIVE0 -> LEVEL
0x0488: 0x0000005944000100 GPP_C17 GPIO | 0x0488: 0x0000005940000100 GPP_C17 GPIO DRIVE0 -> LEVEL
0x0490: 0x0000005a44000100 GPP_C18 GPIO | 0x0490: 0x0000005a40000100 GPP_C18 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0498: 0x0000005b44000300 GPP_C19 GPIO | 0x0498: 0x0000005b40000100 GPP_C19 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04a0: 0x0000005c44000300 GPP_C20 GPIO | 0x04a0: 0x0000005c40000100 GPP_C20 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04a8: 0x0000005d44000300 GPP_C21 GPIO | 0x04a8: 0x0000005d40000102 GPP_C21 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04b0: 0x0000005e44000300 GPP_C22 GPIO | 0x04b0: 0x0000005e40000100 GPP_C22 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04b8: 0x0000005f44000300 GPP_C23 GPIO | 0x04b8: 0x0000005f40000100 GPP_C23 GPIO DRIVE0 -> LEVEL, NC -> GPI
------- GPIO Group GPP_D ------- ------- GPIO Group GPP_D -------
0x04c0: 0x0000006044000300 GPP_D0 GPIO | 0x04c0: 0x0000006040000100 GPP_D0 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04c8: 0x0000006144000300 GPP_D1 GPIO | 0x04c8: 0x0000006140000100 GPP_D1 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04d0: 0x0000006244000300 GPP_D2 GPIO | 0x04d0: 0x0000006240000100 GPP_D2 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04d8: 0x0000006344000300 GPP_D3 GPIO | 0x04d8: 0x0000006340000102 GPP_D3 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04e0: 0x0000006444000300 GPP_D4 GPIO | 0x04e0: 0x0000006440000100 GPP_D4 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04e8: 0x0000006544000300 GPP_D5 GPIO | 0x04e8: 0x0000006540000102 GPP_D5 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04f0: 0x0000006644000300 GPP_D6 GPIO | 0x04f0: 0x0000006640000102 GPP_D6 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04f8: 0x0000006744000300 GPP_D7 GPIO | 0x04f8: 0x0000006740000102 GPP_D7 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0500: 0x0000006844000300 GPP_D8 GPIO | 0x0500: 0x0000006840000102 GPP_D8 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0508: 0x0000006940000300 GPP_D9 GPIO | 0x0508: 0x0000006940000102 GPP_D9 GPIO NC -> GPI
0x0510: 0x0000006a40000300 GPP_D10 GPIO | 0x0510: 0x0000006a40000102 GPP_D10 GPIO NC -> GPI
0x0518: 0x0000006b40000300 GPP_D11 GPIO | 0x0518: 0x0000006b40000102 GPP_D11 GPIO NC -> GPI
0x0520: 0x0000006c40000300 GPP_D12 GPIO | 0x0520: 0x0000006c40000100 GPP_D12 GPIO NC -> GPI
0x0528: 0x0000006d44000300 GPP_D13 GPIO | 0x0528: 0x0000006d40000102 GPP_D13 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0530: 0x0000006e44000300 GPP_D14 GPIO | 0x0530: 0x0000006e40000102 GPP_D14 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0538: 0x0000006f44000300 GPP_D15 GPIO | 0x0538: 0x0000006f40000102 GPP_D15 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0540: 0x0000007044000300 GPP_D16 GPIO | 0x0540: 0x0000007040000102 GPP_D16 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0548: 0x0000007144000700 GPP_D17 DMIC_CLK1 | 0x0548: 0x0000007140000400 GPP_D17 DMIC_CLK1 DRIVE0 -> LEVEL
0x0550: 0x0000007244000700 GPP_D18 DMIC_DATA1 | 0x0550: 0x0000007240000400 GPP_D18 DMIC_DATA1 DRIVE0 -> LEVEL
0x0558: 0x0000007344000700 GPP_D19 DMIC_CLK0 | 0x0558: 0x0000007340000400 GPP_D19 DMIC_CLK0 DRIVE0 -> LEVEL
0x0560: 0x0000007444000700 GPP_D20 DMIC_DATA0 | 0x0560: 0x0000007440000400 GPP_D20 DMIC_DATA0 DRIVE0 -> LEVEL
0x0568: 0x0000007544000300 GPP_D21 GPIO | 0x0568: 0x0000007540000100 GPP_D21 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0570: 0x0000007644000300 GPP_D22 GPIO | 0x0570: 0x0000007640000100 GPP_D22 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0578: 0x0000007744000300 GPP_D23 GPIO | 0x0578: 0x0000007740000100 GPP_D23 GPIO DRIVE0 -> LEVEL, NC -> GPI
------- GPIO Group GPP_E ------- ------- GPIO Group GPP_E -------
0x0580: 0x0000001842000300 GPP_E0 GPIO | 0x0580: 0x0000001840000102 GPP_E0 GPIO EDGE -> LEVEL, NC -> GPI
0x0588: 0x0000001944000300 GPP_E1 GPIO | 0x0588: 0x0000001940000102 GPP_E1 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0590: 0x0000301a44000702 GPP_E2 SATAXPCIE2 | 0x0590: 0x0000301a40000402 GPP_E2 SATAXPCIE2 DRIVE0 -> LEVEL
0x0598: 0x0000001b44000301 GPP_E3 GPIO | 0x0598: 0x0000001b40000100 GPP_E3 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05a0: 0x0000001c44000300 GPP_E4 GPIO | 0x05a0: 0x0000001c40000100 GPP_E4 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05a8: 0x0000001d44000300 GPP_E5 GPIO | 0x05a8: 0x0000001d40000100 GPP_E5 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05b0: 0x0000001e44000300 GPP_E6 GPIO | 0x05b0: 0x0000001e40000100 GPP_E6 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05b8: 0x0000001f44000300 GPP_E7 GPIO | 0x05b8: 0x0000001f40000102 GPP_E7 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05c0: 0x0000002044000300 GPP_E8 GPIO | 0x05c0: 0x0000002040000102 GPP_E8 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05c8: 0x0000002144000702 GPP_E9 USB_OC0# | 0x05c8: 0x0000002140000402 GPP_E9 USB_OC0# DRIVE0 -> LEVEL
0x05d0: 0x0000002244000702 GPP_E10 USB_OC1# | 0x05d0: 0x0000002240000402 GPP_E10 USB_OC1# DRIVE0 -> LEVEL
0x05d8: 0x0000002344000702 GPP_E11 USB_OC2# | 0x05d8: 0x0000002340000402 GPP_E11 USB_OC2# DRIVE0 -> LEVEL
0x05e0: 0x0000002444000300 GPP_E12 GPIO | 0x05e0: 0x0000002440000100 GPP_E12 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x05e8: 0x0000002544000700 GPP_E13 DDPB_HPD0 | 0x05e8: 0x0000002540000400 GPP_E13 DDPB_HPD0 DRIVE0 -> LEVEL
0x05f0: 0x0000002644000700 GPP_E14 DDPC_HPD1 | 0x05f0: 0x0000002640000400 GPP_E14 DDPC_HPD1 DRIVE0 -> LEVEL
0x05f8: 0x0000002742800300 GPP_E15 GPIO | 0x05f8: 0x0000002740000102 GPP_E15 GPIO EDGE -> LEVEL, NC -> GPI, RXINV ->
0x0600: 0x0000002882080102 GPP_E16 GPIO 0x0600: 0x0000002882080102 GPP_E16 GPIO
0x0608: 0x0000002944000700 GPP_E17 EDP_HPD | 0x0608: 0x0000002940000402 GPP_E17 EDP_HPD DRIVE0 -> LEVEL
0x0610: 0x0000002a44000700 GPP_E18 DDPB_CTRLCLK | 0x0610: 0x0000002a40000400 GPP_E18 DDPB_CTRLCLK DRIVE0 -> LEVEL
0x0618: 0x0000102b44000700 GPP_E19 DDPB_CTRLDATA | 0x0618: 0x0000102b40000400 GPP_E19 DDPB_CTRLDATA DRIVE0 -> LEVEL
0x0620: 0x0000002c44000700 GPP_E20 DDPC_CTRLCLK | 0x0620: 0x0000002c40000400 GPP_E20 DDPC_CTRLCLK DRIVE0 -> LEVEL
0x0628: 0x0000102d44000700 GPP_E21 DDPC_CTRLDATA | 0x0628: 0x0000102d40000400 GPP_E21 DDPC_CTRLDATA DRIVE0 -> LEVEL
0x0630: 0x0000002e40100000 GPP_E22 GPIO | 0x0630: 0x0000002e40100100 GPP_E22 GPIO GPIO -> GPI
0x0638: 0x0000102f44000201 GPP_E23 GPIO | 0x0638: 0x0000102f40000201 GPP_E23 GPIO DRIVE0 -> LEVEL
------- GPIO Community 2 ------- ------- GPIO Community 2 -------
PCR Port ID: 0xad0000 PCR Port ID: 0xad0000
MSC Configuration: 0x43203 MSC Configuration: 0x43203
GPIO Dynamic Local Clock Gating : Enabled GPIO Dynamic Local Clock Gating : Enabled
GPIO Dynamic Partition Clock Gating : Enabled GPIO Dynamic Partition Clock Gating : Enabled
GPIO Static Local Clock Gating : Disabled GPIO Static Local Clock Gating : Disabled
GPIO Driver IRQ Route : IRQ14 GPIO Driver IRQ Route : IRQ14
GPE DW0 : C GPE DW0 : C
GPE DW1 : D GPE DW1 : D
GPE DW2 : E GPE DW2 : E
-------- GPIO Group GPD -------- -------- GPIO Group GPD --------
0x0400: 0x0000005044000300 GPD0 GPIO | 0x0400: 0x0000005040000102 GPD0 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0408: 0x0000005104000702 GPD1 ACPRESENT | 0x0408: 0x0000005100000402 GPD1 ACPRESENT DRIVE0 -> LEVEL
0x0410: 0x0000005240000300 GPD2 GPIO | 0x0410: 0x0000005240000102 GPD2 GPIO NC -> GPI
0x0418: 0x0000305304000702 GPD3 PWRBTN# | 0x0418: 0x0000305300000402 GPD3 PWRBTN# DRIVE0 -> LEVEL
0x0420: 0x0000005404000700 GPD4 SLP_S3# | 0x0420: 0x0000005400000400 GPD4 SLP_S3# DRIVE0 -> LEVEL
0x0428: 0x0000005504000700 GPD5 SLP_S4# | 0x0428: 0x0000005500000400 GPD5 SLP_S4# DRIVE0 -> LEVEL
0x0430: 0x0000005604000700 GPD6 SLP_A# | 0x0430: 0x0000005600000400 GPD6 SLP_A# DRIVE0 -> LEVEL
0x0438: 0x0000005744000301 GPD7 GPIO | 0x0438: 0x0000005740000102 GPD7 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0440: 0x0000005804000700 GPD8 SUSCLK | 0x0440: 0x0000005800000400 GPD8 SUSCLK DRIVE0 -> LEVEL
0x0448: 0x0000005904000700 GPD9 SLP_WLAN# | 0x0448: 0x0000005900000400 GPD9 SLP_WLAN# DRIVE0 -> LEVEL
0x0450: 0x0000005a04000700 GPD10 SLP_S5# | 0x0450: 0x0000005a00000400 GPD10 SLP_S5# DRIVE0 -> LEVEL
0x0458: 0x0000005b44000700 GPD11 LANPHYPC | 0x0458: 0x0000005b40000400 GPD11 LANPHYPC DRIVE0 -> LEVEL
------- GPIO Community 3 ------- ------- GPIO Community 3 -------
PCR Port ID: 0xac0000 PCR Port ID: 0xac0000
MSC Configuration: 0x43203 MSC Configuration: 0x43203
GPIO Dynamic Local Clock Gating : Enabled GPIO Dynamic Local Clock Gating : Enabled
GPIO Dynamic Partition Clock Gating : Enabled GPIO Dynamic Partition Clock Gating : Enabled
GPIO Static Local Clock Gating : Disabled GPIO Static Local Clock Gating : Disabled
GPIO Driver IRQ Route : IRQ14 GPIO Driver IRQ Route : IRQ14
GPE DW0 : C GPE DW0 : C
GPE DW1 : D GPE DW1 : D
GPE DW2 : E GPE DW2 : E
------- GPIO Group GPP_F ------- ------- GPIO Group GPP_F -------
0x0400: 0x0000003044000300 GPP_F0 GPIO | 0x0400: 0x0000003040000100 GPP_F0 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0408: 0x0000003144000300 GPP_F1 GPIO | 0x0408: 0x0000003140000100 GPP_F1 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0410: 0x0000003244000300 GPP_F2 GPIO | 0x0410: 0x0000003240000100 GPP_F2 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0418: 0x0000003344000300 GPP_F3 GPIO | 0x0418: 0x0000003340000100 GPP_F3 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0420: 0x0200003444000300 GPP_F4 GPIO | 0x0420: 0x0000003440000100 GPP_F4 GPIO DRIVE0 -> LEVEL, NC -> GPI, 1v8 tolerance -> 3v3
0x0428: 0x0200003544000300 GPP_F5 GPIO | 0x0428: 0x0000003540000100 GPP_F5 GPIO DRIVE0 -> LEVEL, NC -> GPI, 1v8 tolerance -> 3v3
0x0430: 0x0200003644000300 GPP_F6 GPIO | 0x0430: 0x0000003640000100 GPP_F6 GPIO DRIVE0 -> LEVEL, NC -> GPI, 1v8 tolerance -> 3v3
0x0438: 0x0200003744000300 GPP_F7 GPIO | 0x0438: 0x0000003740000100 GPP_F7 GPIO DRIVE0 -> LEVEL, NC -> GPI, 1v8 tolerance -> 3v3
0x0440: 0x0200003844000702 GPP_F8 SATA_DEVSLP6 | 0x0440: 0x0000003840000400 GPP_F8 SATA_DEVSLP6 DRIVE0 -> LEVEL, 1v8 tolerance -> 3v3
0x0448: 0x0200003944000702 GPP_F9 SATA_DEVSLP7 | 0x0448: 0x0000003940000400 GPP_F9 SATA_DEVSLP7 DRIVE0 -> LEVEL, 1v8 tolerance -> 3v3
0x0450: 0x0200003a44000300 GPP_F10 GPIO | 0x0450: 0x0000003a40000100 GPP_F10 GPIO DRIVE0 -> LEVEL, NC -> GPI, 1v8 tolerance -> 3v3
0x0458: 0x0200003b44000300 GPP_F11 GPIO | 0x0458: 0x0000003b40000100 GPP_F11 GPIO DRIVE0 -> LEVEL, NC -> GPI, 1v8 tolerance -> 3v3
0x0460: 0x0000003c44000300 GPP_F12 GPIO | 0x0460: 0x0000003c40000100 GPP_F12 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0468: 0x0000003d44000300 GPP_F13 GPIO | 0x0468: 0x0000003d40000100 GPP_F13 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0470: 0x0000003e44000300 GPP_F14 GPIO | 0x0470: 0x0000003e40000100 GPP_F14 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0478: 0x0000003f44000300 GPP_F15 GPIO | 0x0478: 0x0000003f40000100 GPP_F15 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0480: 0x0000004044000300 GPP_F16 GPIO | 0x0480: 0x0000004040000100 GPP_F16 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0488: 0x0000004144000300 GPP_F17 GPIO | 0x0488: 0x0000004140000100 GPP_F17 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0490: 0x0000004244000300 GPP_F18 GPIO | 0x0490: 0x0000004240000100 GPP_F18 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x0498: 0x0000004344000300 GPP_F19 GPIO | 0x0498: 0x0000004340000100 GPP_F19 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04a0: 0x0000004444000300 GPP_F20 GPIO | 0x04a0: 0x0000004440000100 GPP_F20 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04a8: 0x0000004544000300 GPP_F21 GPIO | 0x04a8: 0x0000004540000100 GPP_F21 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04b0: 0x0000004644000300 GPP_F22 GPIO | 0x04b0: 0x0000004640000100 GPP_F22 GPIO DRIVE0 -> LEVEL, NC -> GPI
0x04b8: 0x0000004740000300 GPP_F23 GPIO | 0x04b8: 0x0000004740000100 GPP_F23 GPIO NC -> GPI
------- GPIO Group GPP_G ------- ------- GPIO Group GPP_G -------
0x04c0: 0x0000004844000700 GPP_G0 FAN_TACH_0 | 0x04c0: 0x0000004840000400 GPP_G0 FAN_TACH_0 DRIVE0 -> LEVEL
0x04c8: 0x0000004944000700 GPP_G1 FAN_TACH_1 | 0x04c8: 0x0000004940000400 GPP_G1 FAN_TACH_1 DRIVE0 -> LEVEL
0x04d0: 0x0000004a44000700 GPP_G2 FAN_TACH_2 | 0x04d0: 0x0000004a40000400 GPP_G2 FAN_TACH_2 DRIVE0 -> LEVEL
0x04d8: 0x0000004b44000700 GPP_G3 FAN_TACH_3 | 0x04d8: 0x0000004b40000400 GPP_G3 FAN_TACH_3 DRIVE0 -> LEVEL
0x04e0: 0x0000004c44000700 GPP_G4 FAN_TACH_4 | 0x04e0: 0x0000004c40000400 GPP_G4 FAN_TACH_4 DRIVE0 -> LEVEL
0x04e8: 0x0000004d44000702 GPP_G5 FAN_TACH_5 | 0x04e8: 0x0000004d40000402 GPP_G5 FAN_TACH_5 DRIVE0 -> LEVEL
0x04f0: 0x0000004e44000700 GPP_G6 FAN_TACH_6 | 0x04f0: 0x0000004e40000400 GPP_G6 FAN_TACH_6 DRIVE0 -> LEVEL
0x04f8: 0x0000304f44000702 GPP_G7 FAN_TACH_7 | 0x04f8: 0x0000304f40000402 GPP_G7 FAN_TACH_7 DRIVE0 -> LEVEL
## Conclusion
The major changes are :
- the 1v8 tolerance that are lost on GPP_F4->GPP_F11,
- The GPIO becoming GPI for GPP_E22
- All DRIVE0 (and some pads being EDGE or LEVEL) becoming LEVEL everywhere
Updated by Aaron Durbin over 7 years ago
Formatting broke it seems. :( It's from this CL: https://review.coreboot.org/#/c/20233/
And if ghostbin doesn't delete the file here it is: https://ghostbin.com/paste/cnzj6
Updated by Aaron Durbin over 7 years ago
deleted formatted comment now that I figured out how to edit the description.
Updated by Hannah Williams over 7 years ago
The 1v8 tolerance that are lost on GPP_F4->GPP_F11 are the NC ones - PAD_CFG_NC_1V8
Regarding Drive0 changed to LEVEL , following is what EDS says - this change should not be an issue for Native Functions
RXEVCFG - "This field does not affect the received pad state (to GPIORXState or native functions) but how the interrupt or wake triggering events should be delivered to the GPIO Community Controller."
Since we are also seeing issues on Poppy and Soraka, we will narrow down to see which of these needs to go back to the way they were before.
However, Youness Alaoui said these changes worked for him though.
Updated by Youness Alaoui over 7 years ago
@Hannah, The GPP_F8 and GPP_F9 are indeed unmodified by your patch, but if you look at the lines, you'll see that they also lost the 1v8 tolerance bit (0x02xxxxxx).
0x0440: 0x0200003844000702 GPP_F8 SATA_DEVSLP6 | 0x0440: 0x0000003840000400 GPP_F8 SATA_DEVSLP6 DRIVE0 -> LEVEL, 1v8 tolerance -> 3v3
0x0448: 0x0200003944000702 GPP_F9 SATA_DEVSLP7 | 0x0448: 0x0000003940000400 GPP_F9 SATA_DEVSLP7 DRIVE0 -> LEVEL, 1v8 tolerance -> 3v3
So it might be a bug in your gpio code that somehow doesn't set the 1v8 tolerance bit in PAD_CFG_NF_1V8.
For RXEVCFG, my understanding is that it doesn't say that it doesn't affect native functions, but rather that it doesn't affect the "pad state" (bit 1) whether for GPI or for native functions, but it affects the interrupts and wake triggering events (potentially for both GPI and for native as well). Maybe I'm wrong though.
Regardless, even if it doesn't affect native functions, GPP_C16, GPP_C17 and GPP_C18 are GPI and were DRIVE0 and became LEVEL, and I still don't understand what that change means.
Updated by Hannah Williams over 7 years ago
That is interesting because following is what I see - bit 25 in DW1 which is the the PAD_TOL is set for GPP_F8 and GPP_F9
Are you using the latest patchset https://review.coreboot.org/#/c/19201/ ?
pin 124 (I2C2_SDA) mode 1 0x40000402 0x02000034 [ACPI]
pin 125 (I2C2_SCL) mode 1 0x40000402 0x02000035 [ACPI]
pin 126 (I2C3_SDA) mode 1 0x40000402 0x02000036 [ACPI]
pin 127 (I2C3_SCL) mode 1 0x40000402 0x02000037 [ACPI]
pin 128 (I2C4_SDA) mode 1 0x40000402 0x02000038 [ACPI]
pin 129 (I2C4_SCL) mode 1 0x40000402 0x02000039 [ACPI]
pin 130 (I2C5_SDA) mode 1 0x40000402 0x0200003a [ACPI]
pin 131 (I2C5_SCL) mode 1 0x40000402 0x0200003b [ACPI]
Updated by Hannah Williams over 7 years ago
Hi Youness,
Can you please update if https://review.coreboot.org/#/c/19201/ and https://review.coreboot.org/#/c/20233/ works for you
Thanks
Hannah
Updated by Youness Alaoui over 7 years ago
Hannah Williams wrote:
That is interesting because following is what I see - bit 25 in DW1 which is the the PAD_TOL is set for GPP_F8 and GPP_F9
Are you using the latest patchset https://review.coreboot.org/#/c/19201/ ?
pin 124 (I2C2_SDA) mode 1 0x40000402 0x02000034 [ACPI]
pin 125 (I2C2_SCL) mode 1 0x40000402 0x02000035 [ACPI]
pin 126 (I2C3_SDA) mode 1 0x40000402 0x02000036 [ACPI]
pin 127 (I2C3_SCL) mode 1 0x40000402 0x02000037 [ACPI]
pin 128 (I2C4_SDA) mode 1 0x40000402 0x02000038 [ACPI]
pin 129 (I2C4_SCL) mode 1 0x40000402 0x02000039 [ACPI]
pin 130 (I2C5_SDA) mode 1 0x40000402 0x0200003a [ACPI]
pin 131 (I2C5_SCL) mode 1 0x40000402 0x0200003b [ACPI]
Sorry for the delay, I've been busy (and then it seems I wrote the reply and forgot to press 'submit' and I just found the chrome tab with the half-written response, while cleaning up my tabs).
Where did you get this information you just pasted ? On the machine itself, with inteltool, it doesn't show the 1v8 tolerance bit set. I just reset to master and cherry picked the two patches (19201 and 20233) and tried inteltool again and I get the same thing as before :
0x0440: 0x0000003840000400 GPP_F8 SATA_DEVSLP6
0x0448: 0x0000003940000400 GPP_F9 SATA_DEVSLP7
I reverted the patches and tried again and it shows the proper values :
0x0440: 0x0200003844000702 GPP_F8 SATA_DEVSLP6
0x0448: 0x0200003944000702 GPP_F9 SATA_DEVSLP7
So your patch is definitely causing the change in the 1v8 tolerance for F8 and F9.
Updated by Hannah Williams over 7 years ago
Hi Youness,
You have given the values for DW0 for GPP_F8 and F9. Padtol field is in DW1. Please check the values from DW0 (offset 0x444 and 0x44c)
Updated by Youness Alaoui over 7 years ago
Hi Hannah,
The value is 64 bits, the first 32 bits are DW1, the second 32 bits is DW0, that's how inteltool displays them. as you can see from both the good and bad lines, the padtol field is the 0x02 at the start of 0x0200003844000702 which disappeared and became 0x0000003840000400 (so basically, DW1 went from 0x02000038 to 0x00000038)
Updated by Hannah Williams over 7 years ago
With 20233 + 19201 , can you please check if your build has CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
Please check from which file the macro PAD_CFG_NF_1V8 is getting picked from
Updated by Youness Alaoui over 7 years ago
Yes, it's enabled and the only file that has that macro is src/soc/intel/common/block/include/intelblocks/gpio_defs.h
I also modified the macro in that file to something invalid (just to confirm), and it did cause a compilation error, so it's the right place where the macro is taken from.
The PAD_CFG_NF_1V8 macro seems to do the right thing so I enabled GPIO debugging and this is what I see :
gpio_padcfg [0xac, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xac, 08] DW1 [0x00000038 : 0x02000000 : 0x00000038]
gpio_padcfg [0xac, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xac, 09] DW1 [0x00000039 : 0x02000000 : 0x00000039]
And I think the problem is because the value is masked using this :
#define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \
PAD_CFG1_PULL_MASK | \
PAD_CFG1_IOSSTATE_MASK)
Which doesn't include PAD_CFG1_TOL_MASK, which is why the 1v8 flag is ignored and not applied in the gpio_configure_pad. I added that mask and it worked, fixed the problem with the 1v8 tolerance.
So now the only issues remaining are :
- The GPIO becoming GPI for GPP_E22
All DRIVE0 (and some pads being EDGE or LEVEL) becoming LEVEL everywhere
of course all the NC becoming GPI, which is annoying me even though it probably has no effect.
Updated by Hannah Williams over 7 years ago
Thanks for debugging the PAD TOL issue. I'll push the patch for this.
For GPP_E22, why do you need the tx buffer enabled, as it seems to be a input that is also routed to ioapic ?
Also, for the other GPIOs, where RXEVCFG becomes = 0 which is LEVEL, we left it that way because this bit is only about how the interrupt or wake from this gpio is to be delivered. So all the PAD_CFG_GPI_ ones that are configured for interrupts have a way to set the value to edge, level or drive 0.
Can you review your interrupt or wake triggering gpios and see if they have RXEVCFG (26:25) configured correctly.
Updated by Youness Alaoui about 7 years ago
Thanks Hannah. We have had no issues to report so far.
Thanks for the explanation on the other items. I'm not sure I understand about the RXEVCFG, but if you say it's not needed, then it's fine.
@Aaron: I think this issue needs to be closed/marked as resolved, but I don't think I can do it.