Youness Alaoui

Projects

  • coreboot (Developer, Reporter, 05/08/2019)

Activity

Reported issues: 1

02/09/2018

08:50 PM coreboot Bug #158 (Resolved): Skylake: SGX feature conflicts with VMX
If you enable SGX, it will cause the Features (MSR 0x3A: IA32_FEATURE_CONTROL) to be locked before the FSP SiliconIni...

11/20/2017

10:53 PM coreboot Bug #128: skylake common gpio differences on purism
Thanks Hannah. We have had no issues to report so far.
Thanks for the explanation on the other items. I'm not sure ...

08/29/2017

07:13 PM coreboot Bug #128: skylake common gpio differences on purism
Yes, it's enabled and the only file that has that macro is src/soc/intel/common/block/include/intelblocks/gpio_defs.h...

08/25/2017

11:53 PM coreboot Bug #128: skylake common gpio differences on purism
Hi Hannah,
The value is 64 bits, the first 32 bits are DW1, the second 32 bits is DW0, that's how inteltool displa...

08/08/2017

05:19 PM coreboot Bug #128: skylake common gpio differences on purism
Hannah Williams wrote:
> That is interesting because following is what I see - bit 25 in DW1 which is the the PAD_TO...

07/13/2017

09:47 PM coreboot Bug #128: skylake common gpio differences on purism
@Hannah, The GPP_F8 and GPP_F9 are indeed unmodified by your patch, but if you look at the lines, you'll see that the...

Also available in: Atom