If you enable SGX, it will cause the Features (MSR 0x3A: IA32_FEATURE_CONTROL) to be locked before the FSP SiliconInit runs, and that will prevent the FSP from enabling the VMX features. If we set register 'SgxEnable' to 1 and set the '...Youness Alaoui
Thanks Hannah. We have had no issues to report so far. Thanks for the explanation on the other items. I'm not sure I understand about the RXEVCFG, but if you say it's not needed, then it's fine. @Aaron: I think this issue needs to ...Youness Alaoui
Yes, it's enabled and the only file that has that macro is src/soc/intel/common/block/include/intelblocks/gpio_defs.h I also modified the macro in that file to something invalid (just to confirm), and it did cause a compilation error, s...Youness Alaoui
Hi Hannah, The value is 64 bits, the first 32 bits are DW1, the second 32 bits is DW0, that's how inteltool displays them. as you can see from both the good and bad lines, the padtol field is the 0x02 at the start of 0x020000384400070...Youness Alaoui
Hannah Williams wrote: > That is interesting because following is what I see - bit 25 in DW1 which is the the PAD_TOL is set for GPP_F8 and GPP_F9 > ... Sorry for the delay, I've been busy (and then it seems I wrote the reply and forgo...Youness Alaoui
@Hannah, The GPP_F8 and GPP_F9 are indeed unmodified by your patch, but if you look at the lines, you'll see that they also lost the 1v8 tolerance bit (0x02xxxxxx). ~~~ 0x0440: 0x0200003844000702 GPP_F8 SATA_DEVSLP6 | ...Youness Alaoui