Hannah Williams

Projects

  • coreboot (Developer, Reporter, 05/08/2019)

Activity

Reported issues: 0

08/29/2017

09:06 PM coreboot Bug #128: skylake common gpio differences on purism
Thanks for debugging the PAD TOL issue. I'll push the patch for this.
For GPP_E22, why do you need the tx buffer en...

08/28/2017

05:08 PM coreboot Bug #128: skylake common gpio differences on purism
With 20233 + 19201 , can you please check if your build has CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
Pleas...

08/25/2017

11:48 PM coreboot Bug #128: skylake common gpio differences on purism
Hi Youness,
You have given the values for DW0 for GPP_F8 and F9. Padtol field is in DW1. Please check the values fr...

07/28/2017

05:39 PM coreboot Bug #128: skylake common gpio differences on purism
Hi Youness,
Can you please update if https://review.coreboot.org/#/c/19201/ and https://review.coreboot.org/#/c/202...

07/13/2017

11:42 PM coreboot Bug #128: skylake common gpio differences on purism
That is interesting because following is what I see - bit 25 in DW1 which is the the PAD_TOL is set for GPP_F8 and GP...
09:21 PM coreboot Bug #128: skylake common gpio differences on purism
The 1v8 tolerance that are lost on GPP_F4->GPP_F11 are the NC ones - PAD_CFG_NC_1V8
Regarding Drive0 changed to LEV...

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