Issue Tracker

08/29/2017

HW 09:06 PM coreboot Bug #128: skylake common gpio differences on purism

Thanks for debugging the PAD TOL issue. I'll push the patch for this.
For GPP_E22, why do you need the tx buffer enabled, as it seems to be a input that is also routed to ioapic ?
Also, for the other GPIOs, where RXEVCFG becomes = 0 w... Hannah Williams

08/28/2017

HW 05:08 PM coreboot Bug #128: skylake common gpio differences on purism

With 20233 + 19201 , can you please check if your build has CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
Please check from which file the macro PAD_CFG_NF_1V8 is getting picked from Hannah Williams

08/25/2017

HW 11:48 PM coreboot Bug #128: skylake common gpio differences on purism

Hi Youness,
You have given the values for DW0 for GPP_F8 and F9. Padtol field is in DW1. Please check the values from DW0 (offset 0x444 and 0x44c) Hannah Williams

07/28/2017

HW 05:39 PM coreboot Bug #128: skylake common gpio differences on purism

Hi Youness,
Can you please update if https://review.coreboot.org/#/c/19201/ and https://review.coreboot.org/#/c/20233/ works for you
Thanks
Hannah Hannah Williams

07/13/2017

HW 11:42 PM coreboot Bug #128: skylake common gpio differences on purism

That is interesting because following is what I see - bit 25 in DW1 which is the the PAD_TOL is set for GPP_F8 and GPP_F9
Are you using the latest patchset https://review.coreboot.org/#/c/19201/ ?
pin 124 (I2C2_SDA) mode 1 0x4000040... Hannah Williams

HW 09:21 PM coreboot Bug #128: skylake common gpio differences on purism

The 1v8 tolerance that are lost on GPP_F4->GPP_F11 are the NC ones - PAD_CFG_NC_1V8
Regarding Drive0 changed to LEVEL , following is what EDS says - this change should not be an issue for Native Functions
**RXEVCFG** - "This field doe... Hannah Williams