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Bug #512

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1MiB heap breaks TSEG stage cache resume on many platforms

Bug #512: 1MiB heap breaks TSEG stage cache resume on many platforms

Added by Bill XIE over 2 years ago. Updated over 2 years ago.

Status:
Resolved
Priority:
High
Category:
coreboot common code
Target version:
Start date:
10/27/2023
Due date:
% Done:

0%

Estimated time:
Affected versions:
Needs backport to:
Affected hardware:
GM45, Ivy Bridge
Affected OS:
GNU/Linux

Description

commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value") proves to break S3 resume from TSEG stage cache on many platforms, including GM45 and Ivy Bridge.

coreboot-4.21-587-g9b230ae29557 Fri Oct 13 18:35:11 UTC 2023 x86_32 postcar starting (log level: 7)...
Timestamp - start of postcar: 248582576
Timestamp - end of postcar: 248589814
S3 Resume
Error: Can't find stage_cache 57a9e100 in imd
ramstage cache invalid.
board_reset() called!
system_reset() called!

It seems that the commit above has not experienced many test for S3 resume before getting merged.

The default heap size may have to be reconsidered.

AP Updated by Andrei Purdea over 2 years ago Actions #1

A number of libreboot users are also experiencing this, see here: https://codeberg.org/libreboot/lbmk/issues/140
Either disabling Stage Cache, or increasing SMM_RESERVED_SIZE makes the problem go away.

MR Updated by Martin Roth over 2 years ago Actions #2

  • Status changed from Needs Testing to Resolved

Issue should be fixed. The patch that caused the problems was reverted.
https://review.coreboot.org/c/coreboot/+/78850

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