Bug #244


Bootblock size inflated by over 1000%

Added by Patrik Tesarik about 4 years ago. Updated almost 4 years ago.

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Hello everyone,

I just tried to build a new coreboot.rom for my Thinkpad X220.

The build fails because the payload (tianocore) does not fit into the (standard) CBFS (1MB) anymore.

It turns out: The bootblock size increased from < 5KB to over 60 KB in the latest master build.
Tianocore has roughly the same size, a little less actually.
In the last build the empty space was around 3KB. If bootblock size hadn't increased by that much, it would've been a fit.

Unfortunatly I have no knowledge about how the bootblock (size) is affected by or build in coreboot. I did not find any specific documentation on this regard in

I'd really appreciate information/hints about how I can tackle this issue myself or how I can provide you with information needed to investigate this behavior.

Actions #1

Updated by Paul Menzel about 4 years ago

Kyösti replied in

C_ENV_BOOTBLOCK_SIZE 0x4000 is probably enough, unless some debugging consoles are enabled

Please change that value, and try if it builds and boots.

Actions #2

Updated by Angel Pons almost 4 years ago

My guess is that the bootblock size increased because of C_ENVIRONMENT_BOOTBLOCK. This is a small price to pay to get rid of romcc and its weird quirks.

Another suggestion would be to override the default CBFS size in the mainboard Kconfig. If I recall correctly, the BIOS region is 3MB on these devices.

Using the BIOS region size as default CBFS size makes sense in most cases. However, should anyone want to change all mainboards, bear in mind that there are (at least) two exceptions:

  • On some "shared" flash chip topologies, the EC firmware is on the same chip as the BIOS. If the EC firmware is at the beginning of the BIOS region, the CBFS has to start after that.
  • On devices with two flash chips (xx30 series), the default size should not be larger than that of the second component. This is to encourage people to externally flash only the second chip, which is less risky.

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