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Bug #113

open

soc/intel/skylake sets P*RC registers three times

Added by Nico Huber over 7 years ago. Updated over 7 years ago.

Status:
New
Priority:
Normal
Assignee:
-
Category:
chipset configuration
Target version:
-
Start date:
05/10/2017
Due date:
% Done:

0%

Estimated time:
Affected versions:
Needs backport to:
Affected hardware:
Affected OS:

Description

PIRQ* Routing Control registers are set in these places:

  • lpc.c: from devicetree
  • bootblock/pch.c: from devicetree
  • irq.c: from constants passed to FSP

Don't know if the config has to match what FSP is told or if they overwrite each other. Doing this in the bootblock seems to be the least useful (at least if FSP can run without PIC interrupt delivery).

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 #1

Updated by Aaron Durbin over 7 years ago

Here's some more background:

https://review.coreboot.org/#/c/19244/7/src/soc/intel/skylake/bootblock/pch.c@151

"fwiw, I have no idea why we're bothering doing this configuration this early. We should remove this in a follow up patch. It seems to have come in from https://review.coreboot.org/#/c/10341/9/src/soc/intel/skylake/romstage/pch.c which in turn came from https://chromium-review.googlesource.com/c/270758/ but there's no reasoning as for why."

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