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Bug #101
openAsus M2V fails to boot to payload
Status:
New
Priority:
Normal
Assignee:
-
Category:
-
Target version:
-
Start date:
03/15/2017
Due date:
% Done:
0%
Estimated time:
Affected versions:
Needs backport to:
Affected hardware:
Affected OS:
Description
A coreboot image built from commit 7f37418 (AGESA f14: Fix infinite loop) with the attached config does not get to the payload stage.
$ build/cbfstool build/coreboot.rom print
Name Offset Type Size
cbfs master header 0x0 cbfs header 32
cpu_microcode_blob.bin 0x80 microcode 6144
fallback/ramstage 0x1900 stage 58951
fallback/romstage 0xff80 stage 49980
config 0x1c340 raw 351
revision 0x1c500 raw 570
cmos_layout.bin 0x1c780 cmos_layout 1392
fallback/dsdt.aml 0x1cd40 raw 3000
img/nvramcui 0x1d940 payload 148104
img/memtest 0x41c00 payload 180268
fallback/payload 0x6dc80 payload 59680
(empty) 0x7c600 null 12824
bootblock 0x7f840 bootblock 1656
$ sudo ~/src/seabios/scripts/readserial.py /dev/ttyUSB0 1200
======= Wed Mar 15 17:09:19 2017 (adjust=8333.3us)
00.000: <fe>
00.484:
00.483: coreboot-4.5-1291-g7f37418 Wed Mar 15 13:11:50 UTC 2017 romstage starting...
00.653: m2v_bus_init
00.654: it8712f gpio init...
00.654: it8712f gpio: 25=00
00.655: it8712f gpio: 28=00
00.655: it8712f gpio: 29=40
00.656: it8712f gpio: 2a=00
00.656: it8712f gpio: 2c=1d
00.657: it8712f gpio: 62=0a
00.657: it8712f gpio: 63=20
00.658: it8712f gpio: b8=00
00.659: it8712f gpio: c0=00
00.659: it8712f gpio: c3=00
00.660: it8712f gpio: c4=c0
00.660: it8712f gpio: c8=00
00.661: it8712f gpio: cb=00
00.661: it8712f gpio: cc=c0
00.662: it8712f gpio: Setting DDR2 voltage to 1.80V
00.662: now booting...
00.664: Enabling routing table for node 0 done.
00.666: Enabling UP settings
00.666: coherent_ht_finalize
00.667: done
00.668: core0 started:
00.670: now booting... All core 0 started
00.670: started ap apicid:
00.671: SBLink=00
00.673: NC node|link=00
00.676: 00entering optimize_link_incoherent_ht
00.677: sysinfo->link_pair_num=0x1
00.678: entering ht_optimize_link
00.679: pos=0x8a, unfiltered freq_cap=0x8075
00.679: pos=0x8a, filtered freq_cap=0x75
00.680: pos=0x6e, unfiltered freq_cap=0x75
00.680: pos=0x6e, filtered freq_cap=0x75
00.680: freq_cap1=0x75, freq_cap2=0x75
00.681: dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
00.681: dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
00.681: width_cap1=0x11, width_cap2=0x11
00.681: dev1 input ln_width1=0x4, ln_width2=0x4
00.682: dev1 input width=0x1
00.682: dev1 output ln_width1=0x4, ln_width2=0x4
00.683: dev1 input|output width=0x11
00.683: old dev1 input|output width=0x11
00.683: dev2 input|output width=0x11
00.684: old dev2 input|output width=0x11
00.684: after ht_optimize_link for link pair 0, reset_needed=0x1
00.685: after optimize_link_read_pointers_chain, reset_needed=0x1
00.685: 01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
00.691: 01ht reset -
00.692: soft reset
00.869:
00.869:
00.869: coreboot-4.5-1291-g7f37418 Wed Mar 15 13:11:50 UTC 2017 romstage starting...
01.011: m2v_bus_init
01.012: it8712f gpio init...
01.012: it8712f gpio: 25=00
01.013: it8712f gpio: 28=00
01.013: it8712f gpio: 29=40
01.014: it8712f gpio: 2a=00
01.014: it8712f gpio: 2c=1d
01.015: it8712f gpio: 62=0a
01.016: it8712f gpio: 63=20
01.016: it8712f gpio: b8=00
01.017: it8712f gpio: c0=00
01.017: it8712f gpio: c3=00
01.018: it8712f gpio: c4=c0
01.018: it8712f gpio: c8=00
01.019: it8712f gpio: cb=00
01.020: it8712f gpio: cc=c0
01.020: it8712f gpio: Setting DDR2 voltage to 1.80V
01.020: now booting...
01.023: Enabling routing table for node 0 done.
01.024: Enabling UP settings
01.024: coherent_ht_finalize
01.025: done
01.026: core0 started:
01.028: now booting... All core 0 started
01.028: started ap apicid:
01.030: SBLink=00
01.031: NC node|link=00
01.034: 00entering optimize_link_incoherent_ht
01.035: sysinfo->link_pair_num=0x1
01.036: entering ht_optimize_link
01.037: pos=0x8a, unfiltered freq_cap=0x8075
01.037: pos=0x8a, filtered freq_cap=0x75
01.038: pos=0x6e, unfiltered freq_cap=0x75
01.038: pos=0x6e, filtered freq_cap=0x75
01.038: freq_cap1=0x75, freq_cap2=0x75
01.039: dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
01.039: dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
01.039: width_cap1=0x11, width_cap2=0x11
01.040: dev1 input ln_width1=0x4, ln_width2=0x4
01.040: dev1 input width=0x1
01.041: dev1 output ln_width1=0x4, ln_width2=0x4
01.041: dev1 input|output width=0x11
01.041: old dev1 input|output width=0x11
01.042: dev2 input|output width=0x11
01.042: old dev2 input|output width=0x11
01.043: after ht_optimize_link for link pair 0, reset_needed=0x0
01.043: after optimize_link_read_pointers_chain, reset_needed=0x0
01.043: 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
01.049: 00after enable_fid_change
01.193: Current fid_cur: 0x2, fid_max: 0xc
01.194: Requested fid_new: 0xc
01.195: FidVid table step fidvid: 0xc
01.327: R<ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff>
Files
Updated by Paul Menzel over 8 years ago
The issue with the serial console is related to issue #100.
Setting the baud rate to 115200 on the “receiver side”, no message are readable. I guess I need to try more baud rates.
Updated by Arthur Heymans about 8 years ago
Does it hang there or is that the uart console doing something weird (like wrong baud rate). Maybe EHCI debug provides more log?
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