coreboot

The ZBOX-CI320NANO series from ZOTAC see code CB:89528 behaves different
concerning enabling PCIe root ports via devicetree.cb compared to earlier
Baytrail ports from Lenovo H500s CB:89170 and Jetway NF9N-2930 CB:89279.

Although devicetree.cb lists all PCIe root ports for enabling 1c.0, 1c.1
1c.2, and 1c.3, coreboot first enables each device during early init:

...
[SPEW ]  PCI: 00:00:1c.0: enabled 1
[SPEW ]  PCI: 00:00:1c.1: enabled 1
[SPEW ]  PCI: 00:00:1c.2: enabled 1
[SPEW ]  PCI: 00:00:1c.3: enabled 1
...
[SPEW ]    PCI: 00:00:1c.0: enabled 1
[SPEW ]     PCI: 00:00:00.0: enabled 1	#force eth as builtin also tried without it?
[SPEW ]    PCI: 00:00:1c.1: enabled 1
[SPEW ]    PCI: 00:00:1c.2: enabled 1
[SPEW ]    PCI: 00:00:1c.3: enabled 1
...

Later on disables each device except 1c.2 which contains miniPCIe wifi:

...
[SPEW ]  PCI: 00:00:1c.0 [8086/0000] bus ops
[DEBUG]  No PCIe device present.
[WARN ]  reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
[DEBUG]  PCI: 00:00:1c.0: Disabling device: 1c.0
[DEBUG]  Power management CAP offset 0xa0.
[DEBUG]  PCI: 00:00:1c.0 [8086/0f48] disabled

[SPEW ]  PCI: 00:00:1c.1 [8086/0000] bus ops
[DEBUG]  No PCIe device present.
[WARN ]  reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
[DEBUG]  PCI: 00:00:1c.1: Disabling device: 1c.1
[DEBUG]  Power management CAP offset 0xa0.
[DEBUG]  PCI: 00:00:1c.1 [8086/0f4a] disabled

[SPEW ]  PCI: 00:00:1c.2 [8086/0000] bus ops
[DEBUG]  PCI: 00:00:1c.2 [8086/0f4c] enabled

[SPEW ]  PCI: 00:00:1c.3 [8086/0000] bus ops
[DEBUG]  No PCIe device present.
[WARN ]  reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
[DEBUG]  PCI: 00:00:1c.3: Disabling device: 1c.3
[DEBUG]  Power management CAP offset 0xa0.
[DEBUG]  PCI: 00:00:1c.3 [8086/0f4e] disabled
...
[SPEW ]  PCI: 00:00:1c.0: enabled 0
[SPEW ]  PCI: 00:00:1c.1: enabled 0
[SPEW ]  PCI: 00:00:1c.2: enabled 1
[SPEW ]  PCI: 00:00:1c.3: enabled 0
...

While the 1c.2 root port stays enabled it is not listed in the OS using
lspci, however the miniPCIe WIFI device behind it does list and works.
A Realtek RTL8111F Gb NIC on the PCIe 1c.0 root port remains undetected!

This only misbehaves on the ZBOX, Lenovo and Jetway boards enable and
do list their PCIe root ports including the devices on those root ports.

The coreboot log mentions the following lines while unintentionally
disabling a PCIe root port:

[WARN ]  reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
[DEBUG]  Power management CAP offset 0xa0.

Besides using devicetree.cb as a method to enable / disable devices, are
there special GPIO values that may override this or Power management CAP
offset values that I haven't yet set up correctly?

Could this be an issue with the Realtek Gb adapter that needs a special
gpio/reset pin and Kconfig option like the Asrock H110M-DVS (which also
doesn't seem to have a working NIC)?

Tried two coreboot code revisions including a older one that works fine
on the earlier Baytrail Lenovo and Jetway ports and different EDK2 revs:

coreboot-25.06-77-g812d0e2f626d
coreboot-25.09-70-g98a54453284e-dirty
EDK2 (MrChromebox-2502/2505/2508)

Also tried disabling libgfxinit, removing VBT and following options:

CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=n
CONFIG_PCIEXP_COMMON_CLOCK=n
CONFIG_PCIEXP_ASPM=n
CONFIG_PCIEXP_L1_SUB_STATE=n
CONFIG_PCIEXP_CLK_PM=n

It doesn't make a difference except that disabling TOP_DOWN breaks the
miniPCIe which contradicts this recent patchCB:89464 and BUG 611.

Comparing the build .config of the Jetway with this ZOTAC only reveals
this obvious difference which I still need to rule out, besides some
uart/serial/sio options:

< CONFIG_USE_DDR3=y
> CONFIG_DRAM_SUPPORT_DDR3=y
#both boards use DDR3L SODIMM(s) (Jetway uses 2)

More and complete logs are available in the attachment zotac_zbox-ci320nano.zip.