|
|
|
*** Pre-CBMEM romstage console overflowed, log truncated! ***
|
|
cs...
|
|
[DEBUG] Back from systemagent_early_init()
|
|
[DEBUG] Hybrid graphics: No discrete GPU present.
|
|
[DEBUG] Locking EEPROM RFID
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Requested 0MB UMA
|
|
[DEBUG] Starting native Platform init
|
|
[DEBUG] DMI: Running at X4 @ 5000MT/s
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes)
|
|
[DEBUG] Trying stored timings.
|
|
[DEBUG] Starting Ivy Bridge RAM training (fast boot).
|
|
[DEBUG] 100MHz reference clock support: yes
|
|
[DEBUG] PLL_REF100_CFG value: 0x7
|
|
[DEBUG] Trying CAS 9, tCK 320.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 800 MHz
|
|
[DEBUG] Selected CAS latency : 9T
|
|
[DEBUG] MPLL busy... done in 10 us
|
|
[DEBUG] MPLL frequency is set at : 800 MHz
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 4
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 8ea00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 71600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 4
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] t123: 1767, 6000, 6120
|
|
[NOTE ] ME: Wrong mode : 2
|
|
[NOTE ] ME: FWS2: 0x100a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: ME is reporting as disabled, so not waiting for a response.
|
|
[NOTE ] ME: FWS2: 0x100a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: No DID Ack received
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1596 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00620020):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 8192 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] memcfg channel[1] config (00620020):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 8192 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ffda000
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 2: 0x80300000 0x100000
|
|
[DEBUG] Subregion 3: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x4fb40 size 0x46d0 in mcache @0xfeff1024
|
|
[DEBUG] Loading module at 0x7ffd3000 with entry 0x7ffd3031. filesize: 0x42c8 memsize: 0x6790
|
|
[DEBUG] Processing 242 relocs. Offset value of 0x7dfd3000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 791 ms
|
|
|
|
|
|
[NOTE ] coreboot-26.03-1125-g69be07fac797-dirty Wed Jun 17 02:44:13 UTC 2026 x86_32 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x1e280 size 0x2af84 in mcache @0x7ffdd0bc
|
|
[DEBUG] Loading module at 0x7fe86000 with entry 0x7fe86000. filesize: 0x3c4a8 memsize: 0x14b5f0
|
|
[DEBUG] Processing 4283 relocs. Offset value of 0x7be86000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 65 ms
|
|
|
|
|
|
[NOTE ] coreboot-26.03-1125-g69be07fac797-dirty Wed Jun 17 02:44:13 UTC 2026 x86_32 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[DEBUG] PCI: 00:00:00.0 [8086/0154] enabled
|
|
[INFO ] PCI: Static device PCI: 00:00:01.0 not found, disabling it.
|
|
[DEBUG] PCI: 00:00:02.0 [8086/0166] enabled
|
|
[DEBUG] PCI: 00:00:04.0 [8086/0153] disabled
|
|
[DEBUG] PCI: 00:00:14.0 [8086/1e31] enabled
|
|
[DEBUG] PCI: 00:00:16.0 [8086/1e3a] enabled
|
|
[DEBUG] PCI: 00:00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:00:16.3: Disabling device
|
|
[DEBUG] PCI: 00:00:19.0 [8086/1502] enabled
|
|
[DEBUG] PCI: 00:00:1a.0 [8086/1e2d] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/1e20] enabled
|
|
[DEBUG] PCI: 00:00:1c.0: Found a downstream device
|
|
[INFO ] PCH: PCIe Root Port coalescing is enabled
|
|
[DEBUG] PCI: 00:00:1c.0 [8086/1e10] enabled
|
|
[DEBUG] PCI: 00:00:1c.1: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.1 [8086/1e12] enabled
|
|
[DEBUG] PCI: 00:00:1c.2: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.2 [8086/1e14] enabled
|
|
[DEBUG] PCI: 00:00:1c.3: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3 [8086/1e16] disabled
|
|
[DEBUG] PCI: 00:00:1c.4: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.4: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.4: check set enabled
|
|
[DEBUG] PCI: 00:00:1c.5: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.6: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.7: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.7: Disabling device
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/1e26] enabled
|
|
[DEBUG] PCI: 00:00:1e.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.0 [8086/2448] disabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/1e55] enabled
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/1e01] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/1e22] enabled
|
|
[DEBUG] PCI: 00:00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.5 [8086/1e09] disabled No operations
|
|
[DEBUG] PCI: 00:00:1f.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.6 [8086/1e24] disabled No operations
|
|
[DEBUG] PCI: 00:00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[DEBUG] PCI: 00:01:00.0 [1180/e823] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L0s and L1
|
|
[DEBUG] PCI: 00:01:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 49 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[DEBUG] PCI: 00:02:00.0 [168c/0030] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L0s and L1
|
|
[DEBUG] PCI: 00:02:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 49 msecs
|
|
[DEBUG] PCI: 00:00:1c.2 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
|
|
[INFO ] PCI: 00:00:1c.2: ASPM enabled L0s and L1 (no endpoint)
|
|
[INFO ] PCI: 00:00:1c.2: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.2 finished in 31 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[INFO ] PMH7: ID 05 Revision 00
|
|
[DEBUG] PNP: 00ff.1 enabled
|
|
[INFO ] Found TPM 1.2 ST33ZP24 (0x0000) by ST Microelectronics (0x104a)
|
|
[DEBUG] PNP: 0c31.0 enabled
|
|
[INFO ] H8: EC Firmware ID G1HT35WW-3.22, Version 3.01B
|
|
[DEBUG] No CMOS option 'power_management_beeps'.
|
|
[DEBUG] No CMOS option 'low_battery_beep'.
|
|
[INFO ] H8: BDC not installed
|
|
[INFO ] H8: WWAN not installed
|
|
[DEBUG] PNP: 00ff.2 enabled
|
|
[DEBUG] Hybrid graphics: Not installed
|
|
[DEBUG] GENERIC: 0.0 disabled
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 81 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] I2C: 01:54 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:55 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:56 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:57 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5c enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5d enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5e enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5f enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->scan_bus: bus PCI: 00:00:1f.3 finished in 65 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 667 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 694 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 713 ms
|
|
[DEBUG] found VGA at PCI: 00:00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x471600000 TOLUD 0x8ea00000 TOM 0x400000000
|
|
[DEBUG] MEBASE 0x7ffff00000
|
|
[DEBUG] IGD decoded, subtracting 224M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 14102M
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0xff] mem
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0x1ffff] mem
|
|
[DEBUG] PCI: 00:02:00.0 30 * [0x20000 - 0x2ffff] mem
|
|
[DEBUG] PCI: 00:00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] NONE 18 * [0x0 - 0x7ff] io
|
|
[DEBUG] PCI: 00:00:1c.2 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] NONE 10 * [0x0 - 0x7fffff] mem
|
|
[DEBUG] PCI: 00:00:1c.2 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem
|
|
[DEBUG] PCI: 00:00:1c.2 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base fed40000 limit fed44fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000200 base 000015e0 limit 000015eb io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000300 base 00001600 limit 0000167b io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.1 15e0 base 000015e0 limit 000015ef io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 60 base 00000060 limit 00000060 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 62 base 00000062 limit 00000062 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 64 base 00000064 limit 00000064 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 66 base 00000066 limit 00000066 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 1600 base 00001600 limit 00001600 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 1604 base 00001604 limit 00001604 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 1602 base 00001602 limit 00001602 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 1606 base 00001606 limit 00001606 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.2 1610 base 00001610 limit 0000161f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: 5e0, Tag: 100
|
|
[INFO ] * Base: 15f0, Size: 10, Tag: 100
|
|
[INFO ] * Base: 167c, Size: e984, Tag: 100
|
|
[DEBUG] PCI: 00:00:1c.2 1c * [0xf000 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:00:02.0 20 * [0xefc0 - 0xefff] limit: efff io
|
|
[DEBUG] PCI: 00:00:19.0 18 * [0xefa0 - 0xefbf] limit: efbf io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0xef80 - 0xef9f] limit: ef9f io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0xef78 - 0xef7f] limit: ef7f io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0xef70 - 0xef77] limit: ef77 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0xef6c - 0xef6f] limit: ef6f io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0xef68 - 0xef6b] limit: ef6b io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed10000 limit fed17fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed18000 limit fed18fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed19000 limit fed19fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 4715fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 80000000 limit 8e9fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 02 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 04 base fed00000 limit fed00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 05 base fed20000 limit fed3ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 06 base fed45000 limit fed8ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 f0 base fed1c000 limit fed1ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 8ea00000, Size: 61600000, Tag: 200
|
|
[INFO ] * Base: 471600000, Size: b8ea00000, Tag: 200
|
|
[DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem
|
|
[DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem
|
|
[DEBUG] PCI: 00:00:1c.2 24 * [0xff0000000 - 0xfffffffff] limit: fffffffff prefmem
|
|
[DEBUG] PCI: 00:00:1c.2 20 * [0xdf400000 - 0xdfbfffff] limit: dfbfffff mem
|
|
[DEBUG] PCI: 00:00:1c.0 20 * [0xdf300000 - 0xdf3fffff] limit: df3fffff mem
|
|
[DEBUG] PCI: 00:00:1c.1 20 * [0xdf200000 - 0xdf2fffff] limit: df2fffff mem
|
|
[DEBUG] PCI: 00:00:19.0 10 * [0xdf1e0000 - 0xdf1fffff] limit: df1fffff mem
|
|
[DEBUG] PCI: 00:00:14.0 10 * [0xdf1d0000 - 0xdf1dffff] limit: df1dffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0xdf1cc000 - 0xdf1cffff] limit: df1cffff mem
|
|
[DEBUG] PCI: 00:00:19.0 14 * [0xdf1cb000 - 0xdf1cbfff] limit: df1cbfff mem
|
|
[DEBUG] PCI: 00:00:1f.2 24 * [0xdf1ca000 - 0xdf1ca7ff] limit: df1ca7ff mem
|
|
[DEBUG] PCI: 00:00:1a.0 10 * [0xdf1c9000 - 0xdf1c93ff] limit: df1c93ff mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 * [0xdf1c8000 - 0xdf1c83ff] limit: df1c83ff mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 * [0xdf1c7000 - 0xdf1c70ff] limit: df1c70ff mem
|
|
[DEBUG] PCI: 00:00:16.0 10 * [0xdf1c6000 - 0xdf1c600f] limit: df1c600f mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 00:01:00.0 10 * [0xdf300000 - 0xdf3000ff] limit: df3000ff mem
|
|
[DEBUG] PCI: 00:02:00.0 10 * [0xdf200000 - 0xdf21ffff] limit: df21ffff mem
|
|
[DEBUG] PCI: 00:02:00.0 30 * [0xdf220000 - 0xdf22ffff] limit: df22ffff mem
|
|
[DEBUG] NONE 18 * [0xf000 - 0xf7ff] limit: f7ff io
|
|
[DEBUG] NONE 14 * [0xff0000000 - 0xfffffffff] limit: fffffffff prefmem
|
|
[DEBUG] NONE 10 * [0xdf400000 - 0xdfbfffff] limit: dfbfffff mem
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000efc0 - 0x000000000000efff] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000df1d0000 - 0x00000000df1dffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000df1c6000 - 0x00000000df1c600f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:00:19.0 10 <- [0x00000000df1e0000 - 0x00000000df1fffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:00:19.0 14 <- [0x00000000df1cb000 - 0x00000000df1cbfff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000efa0 - 0x000000000000efbf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000df1c9000 - 0x00000000df1c93ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000df1cc000 - 0x00000000df1cffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000df300000 - 0x00000000df3fffff] size 0x00100000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:01:00.0 10 <- [0x00000000df300000 - 0x00000000df3000ff] size 0x00000100 gran 0x08 mem
|
|
[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000df200000 - 0x00000000df2fffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PCI: 00:02:00.0 10 <- [0x00000000df200000 - 0x00000000df21ffff] size 0x00020000 gran 0x11 mem64
|
|
[DEBUG] PCI: 00:02:00.0 30 <- [0x00000000df220000 - 0x00000000df22ffff] size 0x00010000 gran 0x10 romem
|
|
[DEBUG] PCI: 00:00:1c.2 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 bus 03 io
|
|
[DEBUG] PCI: 00:00:1c.2 24 <- [0x0000000ff0000000 - 0x0000000fffffffff] size 0x10000000 gran 0x14 seg 00 bus 03 prefmem
|
|
[DEBUG] PCI: 00:00:1c.2 20 <- [0x00000000df400000 - 0x00000000dfbfffff] size 0x00800000 gran 0x14 seg 00 bus 03 mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000df1c8000 - 0x00000000df1c83ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ef78 - 0x000000000000ef7f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ef6c - 0x000000000000ef6f] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ef70 - 0x000000000000ef77] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ef68 - 0x000000000000ef6b] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ef80 - 0x000000000000ef9f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000df1ca000 - 0x00000000df1ca7ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000df1c7000 - 0x00000000df1c70ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1775 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:02.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:00:14.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:14.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:16.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:19.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1a.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1c.0 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.1 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1c.1 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1c.2 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.2 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1c.2 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 00:01:00.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:01:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:02:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 241 ms
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT NOT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] microcode: sig=0x306a9 pf=0x10 revision=0x21
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x6800 in mcache @0x7ffdd02c
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0
|
|
[DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x00000004715fffff size 0x371600000 type 6
|
|
[DEBUG] 0x0000000ff0000000 - 0x0000000fffffffff size 0x10000000 type 0
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 5/10.
|
|
[DEBUG] MTRR: WB selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
|
|
[DEBUG] MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0
|
|
[DEBUG] MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0
|
|
[DEBUG] MTRR: 4 base 0x0000000ff0000000 mask 0x0000000ff0000000 type 0
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 4 cores, 8 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] CPU: APIC: 04 enabled
|
|
[DEBUG] CPU: APIC: 05 enabled
|
|
[DEBUG] CPU: APIC: 06 enabled
|
|
[DEBUG] CPU: APIC: 07 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 7 APs
|
|
[DEBUG] Waiting for ICR not to be busy...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[DEBUG] done.
|
|
[INFO ] LAPIC 0x4 in XAPIC mode.
|
|
[INFO ] LAPIC 0x5 in XAPIC mode.
|
|
[INFO ] AP: slot 1 apic_id 4, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 3 apic_id 5, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x7 in XAPIC mode.
|
|
[INFO ] AP: slot 2 apic_id 1, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 5 apic_id 7, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x6 in XAPIC mode.
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[INFO ] LAPIC 0x3 in XAPIC mode.
|
|
[INFO ] AP: slot 6 apic_id 2, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 7 apic_id 3, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 4 apic_id 6, MCU rev: 0x00000021
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80002000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7fea753b
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] HANDLER [0x802fd000-0x802ff13f]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fcc00-0x802fcfff]
|
|
[DEBUG] stub0 [0x802f5000-0x802f519f]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fc800-0x802fcbff]
|
|
[DEBUG] stub1 [0x802f4c00-0x802f4d9f]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fc400-0x802fc7ff]
|
|
[DEBUG] stub2 [0x802f4800-0x802f499f]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fc000-0x802fc3ff]
|
|
[DEBUG] stub3 [0x802f4400-0x802f459f]
|
|
|
|
[DEBUG] CPU 4
|
|
[DEBUG] ss4 [0x802fbc00-0x802fbfff]
|
|
[DEBUG] stub4 [0x802f4000-0x802f419f]
|
|
|
|
[DEBUG] CPU 5
|
|
[DEBUG] ss5 [0x802fb800-0x802fbbff]
|
|
[DEBUG] stub5 [0x802f3c00-0x802f3d9f]
|
|
|
|
[DEBUG] CPU 6
|
|
[DEBUG] ss6 [0x802fb400-0x802fb7ff]
|
|
[DEBUG] stub6 [0x802f3800-0x802f399f]
|
|
|
|
[DEBUG] CPU 7
|
|
[DEBUG] ss7 [0x802fb000-0x802fb3ff]
|
|
[DEBUG] stub7 [0x802f3400-0x802f359f]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80001fff]
|
|
[DEBUG] Loading module at 0x802fd000 with entry 0x802fd746. filesize: 0x20d8 memsize: 0x2140
|
|
[DEBUG] Processing 90 relocs. Offset value of 0x802fd000
|
|
[DEBUG] Loading module at 0x802f5000 with entry 0x802f5000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x802f5000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80002000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f4c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f4800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f4400, cpu # 0x3
|
|
[DEBUG] SMM Module: placing smm entry code at 802f4000, cpu # 0x4
|
|
[DEBUG] SMM Module: placing smm entry code at 802f3c00, cpu # 0x5
|
|
[DEBUG] SMM Module: placing smm entry code at 802f3800, cpu # 0x6
|
|
[DEBUG] SMM Module: placing smm entry code at 802f3400, cpu # 0x7
|
|
[DEBUG] SMM Module: stub loaded at 802f5000. Will call 0x802fd746
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802ed000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ebc00, cpu = 5
|
|
[DEBUG] In relocation handler: cpu 5
|
|
[DEBUG] New SMBASE=0x802ebc00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec000, cpu = 4
|
|
[DEBUG] In relocation handler: cpu 4
|
|
[DEBUG] New SMBASE=0x802ec000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec800, cpu = 2
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ec800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ec400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ecc00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802ecc00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb400, cpu = 7
|
|
[DEBUG] In relocation handler: cpu 7
|
|
[DEBUG] New SMBASE=0x802eb400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb800, cpu = 6
|
|
[DEBUG] In relocation handler: cpu 6
|
|
[DEBUG] New SMBASE=0x802eb800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 00: PP0 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #2
|
|
[INFO ] Initializing CPU #7
|
|
[INFO ] Initializing CPU #6
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 02: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] APIC: 02: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #6 initialized
|
|
[INFO ] CPU #7 initialized
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 05: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] APIC: 05: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #3 initialized
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] Initializing CPU #5
|
|
[INFO ] Initializing CPU #4
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 07: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] APIC: 07: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #4 initialized
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #5 initialized
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 01: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #2 initialized
|
|
[INFO ] bsp_do_flight_plan done after 1391 msecs.
|
|
[DEBUG] model_x06ax: frequency set to 3200
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO2 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] MTRR: TEMPORARY Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x00000000feffffff size 0x7f000000 type 0
|
|
[DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
|
|
[DEBUG] 0x0000000100000000 - 0x00000004715fffff size 0x371600000 type 6
|
|
[DEBUG] 0x0000000ff0000000 - 0x0000000fffffffff size 0x10000000 type 0
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 9/10.
|
|
[DEBUG] MTRR: WB selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
|
|
[DEBUG] MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0
|
|
[DEBUG] MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 0
|
|
[DEBUG] MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff8000000 type 0
|
|
[DEBUG] MTRR: 4 base 0x00000000f8000000 mask 0x0000000ffc000000 type 0
|
|
[DEBUG] MTRR: 5 base 0x00000000fc000000 mask 0x0000000ffe000000 type 0
|
|
[DEBUG] MTRR: 6 base 0x00000000fe000000 mask 0x0000000fff000000 type 0
|
|
[DEBUG] MTRR: 7 base 0x00000000ff000000 mask 0x0000000fff000000 type 5
|
|
[DEBUG] MTRR: 8 base 0x0000000ff0000000 mask 0x0000000ff0000000 type 0
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 2129 msecs
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling PEG10.
|
|
[DEBUG] Disabling Device 4.
|
|
[DEBUG] Disabling PEG60.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Disabling PEG IO clock.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 35 Watts
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 45 msecs
|
|
[DEBUG] PCI: 00:00:02.0 init
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x4dfc0 size 0x116b in mcache @0x7ffdd1b4
|
|
[INFO ] Found a VBT of 4459 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[DEBUG] IVB GT2 25W-35W Power Meter Weights
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[INFO ] framebuffer_info: bytes_per_line: 5120, bits_per_pixel: 32
|
|
[INFO ] x_res x y_res: 1280 x 720, size: 3686400 at 0xe0000000
|
|
[DEBUG] PCI: 00:00:02.0 init finished in 219 msecs
|
|
[DEBUG] PCI: 00:00:14.0 init
|
|
[DEBUG] XHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:14.0 init finished in 7 msecs
|
|
[DEBUG] PCI: 00:00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[CRIT ] intel_me_path: mbp is not ready!
|
|
[NOTE ] ME: BIOS path: Error
|
|
[DEBUG] ME: me_state=1, me_state_prev=3
|
|
[DEBUG] PCI: 00:00:16.0: Disabling device
|
|
[DEBUG] PCI: 00:00:16.0 init finished in 130 msecs
|
|
[DEBUG] PCI: 00:00:19.0 init
|
|
[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1a.0 init finished in 7 msecs
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: base = 0xdf1cc000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: initializing codec #3...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x80862806
|
|
[DEBUG] azalia_audio: - verb size: 16
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] azalia_audio: initializing codec #0...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0269
|
|
[DEBUG] azalia_audio: - verb size: 44
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 74 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.0 init finished in 6 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.1 init finished in 6 msecs
|
|
[DEBUG] PCI: 00:00:1c.2 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.2 init finished in 6 msecs
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 7 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected QM77, device id: 0x1e55, rev id 0x4
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources enabled.
|
|
[DEBUG] PantherPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 88 msecs
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0xdf1ca000
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 17 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 init
|
|
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:01:00.0 init
|
|
[DEBUG] PCI: 00:01:00.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:02:00.0 init
|
|
[DEBUG] PCI: 00:02:00.0 init finished in 0 msecs
|
|
[DEBUG] PNP: 00ff.2 init
|
|
[DEBUG] PNP: 00ff.2 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:54 init
|
|
[DEBUG] I2C: 01:54 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:55 init
|
|
[DEBUG] I2C: 01:55 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:56 init
|
|
[DEBUG] I2C: 01:56 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:57 init
|
|
[DEBUG] I2C: 01:57 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5c init
|
|
[DEBUG] I2C: 01:5c init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5d init
|
|
[DEBUG] I2C: 01:5d init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5e init
|
|
[DEBUG] I2C: 01:5e init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5f init
|
|
[DEBUG] I2C: 01:5f init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 975 / 2147 ms
|
|
[DEBUG] TPM: Startup
|
|
[DEBUG] TPM: command 0x99 returned 0x0
|
|
[DEBUG] TPM: Asserting physical presence
|
|
[DEBUG] TPM: command 0x4000000a returned 0x0
|
|
[DEBUG] TPM: command 0x65 returned 0x0
|
|
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
|
|
[INFO ] TPM: setup succeeded
|
|
[DEBUG] clear_memory: Clearing DRAM 0000000000000000-0000000000005000
|
|
[ERROR] Null dereference at eip: 0x7feabd6c
|
|
[DEBUG] clear_memory: Clearing DRAM 000000000000a000-00000000000a0000
|
|
[DEBUG] clear_memory: Clearing DRAM 00000000000c0000-000000007fe71000
|
|
[DEBUG] clear_memory: Clearing DRAM 0000000100000000-0000000471600000
|
|
[DEBUG] memset_pae: Using virtual address 0x00400000 as scratchpad
|
|
[DEBUG] init_pae_pagetables: Using address 0x00005000 for page tables
|
|
[DEBUG] clear_memory: Clearing DRAM 0000000000005000-000000000000a000
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 1023 / 132 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[DEBUG] flash size 0xc00000 bytes
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0xc00000
|
|
[DEBUG] apm_control: Finalizing SMM.
|
|
[DEBUG] APMC done.
|
|
[INFO ] Devices finalized
|
|
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 43 ms
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x4a480 size 0x3b0d in mcache @0x7ffdd188
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7fe45000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 8 core(s) each.
|
|
[DEBUG] Supported C-states: C0 C1 C1E C3 C6 C7 C7S
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x471600000, len = 0xb8ea00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
|
|
[INFO ] ACPI: * H8
|
|
[INFO ] H8: BDC not installed
|
|
[INFO ] H8: WWAN not installed
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] TCPA log created at 0x7fe35000
|
|
[DEBUG] ACPI: * TCPA
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] current = 7fe4b640
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 26240 bytes.
|
|
[DEBUG] smbios_write_tables: 7fe2d000
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[DEBUG] SMBIOS tables: 1124 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum eff7
|
|
[DEBUG] Writing coreboot table at 0x7fe69000
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'cmos_layout.bin' @0x4f2c0 size 0x83c in mcache @0x7ffdd1fc
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000007fe2cfff: RAM
|
|
[DEBUG] 6. 000000007fe2d000-000000007fe85fff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007fe86000-000000007ffd1fff: RAMSTAGE
|
|
[DEBUG] 8. 000000007ffd2000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 0000000080000000-000000008e9fffff: RESERVED
|
|
[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 11. 00000000fec00000-00000000fec00fff: RESERVED
|
|
[DEBUG] 12. 00000000fed00000-00000000fed00fff: RESERVED
|
|
[DEBUG] 13. 00000000fed10000-00000000fed19fff: RESERVED
|
|
[DEBUG] 14. 00000000fed1c000-00000000fed8ffff: RESERVED
|
|
[DEBUG] 15. 00000000ff000000-00000000ffffffff: RESERVED
|
|
[DEBUG] 16. 0000000100000000-00000004715fffff: RAM
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] Wrote coreboot table at: 0x7fe69000, 0xc94 bytes, checksum 1e28
|
|
[DEBUG] coreboot table: 3244 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
|
|
[DEBUG] RO MCACHE 3. 0x7ffdd000 0x000003bc
|
|
[DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910
|
|
[DEBUG] MEM INFO 5. 0x7ffda000 0x000010c8
|
|
[DEBUG] AFTER CAR 6. 0x7ffd2000 0x00008000
|
|
[DEBUG] RAMSTAGE 7. 0x7fe85000 0x0014d000
|
|
[DEBUG] SMM BACKUP 8. 0x7fe75000 0x00010000
|
|
[DEBUG] IGD OPREGION 9. 0x7fe71000 0x00003200
|
|
[DEBUG] COREBOOT 10. 0x7fe69000 0x00008000
|
|
[DEBUG] ACPI 11. 0x7fe45000 0x00024000
|
|
[DEBUG] TCPA TCGLOG12. 0x7fe35000 0x00010000
|
|
[DEBUG] SMBIOS 13. 0x7fe2d000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7fffeb20 0x000000e0
|
|
[DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004
|
|
[DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8
|
|
[DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 9 / 1374 ms
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x839c0 size 0x1d49d8 in mcache @0x7ffdd2b8
|
|
[DEBUG] Checking segment from ROM address 0xff4b49ec
|
|
[DEBUG] Checking segment from ROM address 0xff4b4a08
|
|
[DEBUG] Checking segment from ROM address 0xff4b4a24
|
|
[DEBUG] Loading segment from ROM address 0xff4b49ec
|
|
[DEBUG] code (compression=0)
|
|
[DEBUG] New segment dstaddr 0x00009000 memsize 0x1a4e4 srcaddr 0xff4b4a40 filesize 0x12a4c
|
|
[DEBUG] Loading Segment: addr: 0x00009000 memsz: 0x000000000001a4e4 filesz: 0x0000000000012a4c
|
|
[DEBUG] it's not compressed!
|
|
[DEBUG] Clearing Segment: addr: 0x000000000001ba4c memsz: 0x0000000000007a98
|
|
[DEBUG] Loading segment from ROM address 0xff4b4a08
|
|
[DEBUG] code (compression=0)
|
|
[DEBUG] New segment dstaddr 0x00100000 memsize 0x1c1f38 srcaddr 0xff4c748c filesize 0x1c1f38
|
|
[DEBUG] Loading Segment: addr: 0x00100000 memsz: 0x00000000001c1f38 filesz: 0x00000000001c1f38
|
|
[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff4b4a24
|
|
[DEBUG] Entry Point 0x00009000
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 220 / 170 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x00009000(0x7fe69000)
|