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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CFG_GPIO_H
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#define CFG_GPIO_H
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#include <gpio.h>
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/* Pad configuration was generated automatically using intelp2m 2.5-149f0c750c */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_A ------- */
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_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* RCIN# */
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_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAD0 */
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_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAD1 */
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_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAD2 */
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_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAD3 */
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_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* LFRAME# */
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_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SERIRQ */
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_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PIRQA# */
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_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKRUN# */
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_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKOUT_LPC0 */
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_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKOUT_LPC1 */
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PAD_NC(GPP_A11, NONE), /* GPIO */
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PAD_NC(GPP_A12, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */
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PAD_NC(GPP_A14, NONE), /* GPIO */
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PAD_NC(GPP_A15, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* SD_1P8_SEL */
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_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SD_PWR_EN# */
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PAD_NC(GPP_A18, NONE), /* GPIO */
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PAD_NC(GPP_A19, NONE), /* GPIO */
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PAD_NC(GPP_A20, NONE), /* GPIO */
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PAD_NC(GPP_A21, NONE), /* GPIO */
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PAD_NC(GPP_A22, NONE), /* GPIO */
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PAD_NC(GPP_A23, NONE), /* GPIO */
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/* ------- GPIO Group GPP_B ------- */
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PAD_NC(GPP_B0, NONE), /* GPIO */
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PAD_NC(GPP_B1, NONE), /* GPIO */
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PAD_NC(GPP_B2, NONE), /* GPIO */
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PAD_NC(GPP_B3, NONE), /* GPIO */
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PAD_NC(GPP_B4, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SRCCLKREQ0# */
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_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SRCCLKREQ1# */
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_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ2# */
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PAD_NC(GPP_B8, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ4# */
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_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SRCCLKREQ5# */
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PAD_NC(GPP_B11, NONE), /* GPIO */
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PAD_NC(GPP_B12, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */
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_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */
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PAD_NC(GPP_B15, NONE), /* GPIO */
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PAD_NC(GPP_B16, NONE), /* GPIO */
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PAD_NC(GPP_B17, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_NC(GPP_B19, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* GPIO */
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_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_NC(GPP_B22, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1ALERT# */
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_C ------- */
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_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBCLK */
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_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBDATA */
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_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBALERT# */
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_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */
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_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */
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_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0ALERT# */
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/* GPP_C6 - RESERVED */
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/* GPP_C7 - RESERVED */
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PAD_NC(GPP_C8, NONE), /* GPIO */
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PAD_NC(GPP_C9, NONE), /* GPIO */
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PAD_NC(GPP_C10, NONE), /* GPIO */
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PAD_NC(GPP_C11, NONE), /* GPIO */
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PAD_NC(GPP_C12, NONE), /* GPIO */
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PAD_NC(GPP_C13, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_C14, 1, DEEP), /* GPIO */
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_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */
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_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */
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PAD_CFG_GPO(GPP_C18, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C19, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, DEEP, OFF, ACPI), /* GPIO */
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/* ------- GPIO Group GPP_D ------- */
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PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_NC(GPP_D1, NONE), /* GPIO */
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PAD_NC(GPP_D2, NONE), /* GPIO */
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PAD_NC(GPP_D3, NONE), /* GPIO */
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PAD_NC(GPP_D4, NONE), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */
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_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, ACPI), /* GPIO */
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_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_NC(GPP_D11, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_NC(GPP_D13, NONE), /* GPIO */
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PAD_NC(GPP_D14, NONE), /* GPIO */
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PAD_NC(GPP_D15, NONE), /* GPIO */
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PAD_NC(GPP_D16, NONE), /* GPIO */
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PAD_NC(GPP_D17, NONE), /* GPIO */
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PAD_NC(GPP_D18, NONE), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), /* GPIO */
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_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), /* GPIO */
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PAD_NC(GPP_D21, NONE), /* GPIO */
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PAD_NC(GPP_D22, NONE), /* GPIO */
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PAD_NC(GPP_D23, NONE), /* GPIO */
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/* ------- GPIO Group GPP_E ------- */
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_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAGP0 */
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_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAGP2 */
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PAD_NC(GPP_E3, NONE), /* GPIO */
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PAD_NC(GPP_E4, NONE), /* GPIO */
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PAD_NC(GPP_E5, NONE), /* GPIO */
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PAD_NC(GPP_E6, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI), /* GPIO */
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_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */
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_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */
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_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */
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_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */
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_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD0 */
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PAD_NC(GPP_E14, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */
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PAD_NC(GPP_E16, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* EDP_HPD */
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_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLCLK */
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_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */
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_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */
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_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */
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PAD_NC(GPP_E22, NONE), /* GPIO */
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PAD_NC(GPP_E23, NONE), /* GPIO */
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/* ------- GPIO Community 2 ------- */
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/* -------- GPIO Group GPD -------- */
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_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* BATLOW# */
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_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ACPRESENT */
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_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */
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_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PWRBTN# */
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_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */
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_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */
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_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_A# */
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_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), /* GPIO */
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_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */
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PAD_NC(GPD9, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */
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PAD_NC(GPD11, NONE), /* GPIO */
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_F ------- */
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PAD_NC(GPP_F0, NONE), /* GPIO */
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PAD_NC(GPP_F1, NONE), /* GPIO */
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PAD_NC(GPP_F2, NONE), /* GPIO */
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PAD_NC(GPP_F3, NONE), /* GPIO */
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PAD_NC(GPP_F4, NONE), /* GPIO */
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PAD_NC(GPP_F5, NONE), /* GPIO */
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PAD_NC(GPP_F6, NONE), /* GPIO */
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PAD_NC(GPP_F7, NONE), /* GPIO */
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_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C4_SDA */
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_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C4_SCL */
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PAD_NC(GPP_F10, NONE), /* GPIO */
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PAD_NC(GPP_F11, NONE), /* GPIO */
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PAD_NC(GPP_F12, NONE), /* GPIO */
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PAD_NC(GPP_F13, NONE), /* GPIO */
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PAD_NC(GPP_F14, NONE), /* GPIO */
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PAD_NC(GPP_F15, NONE), /* GPIO */
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PAD_NC(GPP_F16, NONE), /* GPIO */
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PAD_NC(GPP_F17, NONE), /* GPIO */
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PAD_NC(GPP_F18, NONE), /* GPIO */
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PAD_NC(GPP_F19, NONE), /* GPIO */
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PAD_NC(GPP_F20, NONE), /* GPIO */
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PAD_NC(GPP_F21, NONE), /* GPIO */
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PAD_NC(GPP_F22, NONE), /* GPIO */
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PAD_NC(GPP_F23, NONE), /* GPIO */
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE), /* GPIO */
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PAD_NC(GPP_G1, NONE), /* GPIO */
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PAD_NC(GPP_G2, NONE), /* GPIO */
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PAD_NC(GPP_G3, NONE), /* GPIO */
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PAD_NC(GPP_G4, NONE), /* GPIO */
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PAD_NC(GPP_G5, NONE), /* GPIO */
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PAD_NC(GPP_G6, NONE), /* GPIO */
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PAD_NC(GPP_G7, NONE), /* GPIO */
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};
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#endif /* CFG_GPIO_H */
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