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-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:00:53 --
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-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:00:53 --
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USB
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[0m
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[0m
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[1m[NOTE ] coreboot-25.12 Thu Dec 18 17:36:57 UTC 2025 x86_32 bootblock starting (log level: 7)...[0m
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[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x890000.[0m
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|
[0m[DEBUG] FMAP: base = 0x0 size = 0xc00000 #areas = 5[0m
|
|
[0m[DEBUG] FMAP: area COREBOOT found @ 891000 (3600384 bytes)[0m
|
|
[0m[INFO ] Booting from COREBOOT region[0m
|
|
[0m[INFO ] CBFS: mcache @0xff7e0e00 built for 15 files, used 0x318 of 0x4000 bytes[0m
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[0m[INFO ] CBFS: Found 'fallback/romstage' @0xf980 size 0x1ba48 in mcache @0xff7e0e8c[0m
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[0m[DEBUG] BS: bootblock times (exec / console): total (unknown) / 54 ms[0m
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[0m
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[0m
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[1m[NOTE ] coreboot-25.12 Thu Dec 18 17:36:57 UTC 2025 x86_32 romstage starting (log level: 7)...[0m
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[0m[DEBUG] Disabling Watchdog reboot... done.[0m
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[0m[DEBUG] SMBus controller enabled[0m
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|
[0m[DEBUG] Setting up static northbridge registers... done.[0m
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|
[0m[DEBUG] Started PEG11 link training.[0m
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|
[0m[DEBUG] Started PEG10 link training.[0m
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[0m[DEBUG] Initializing IGD...[0m
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[0m[DEBUG] Back from haswell_early_initialization()[0m
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[0m[DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i5-4300M CPU @ 2.60GHz[0m
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[0m[DEBUG] AES supported, TXT supported, VT supported[0m
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[0m[DEBUG] PCH type: QM87, device id: 8c4f, rev id 5[0m
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|
[0m[DEBUG] Starting native platform initialisation[0m
|
|
[0m[INFO ] Intel ME early init[0m
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|
[0m[INFO ] Intel ME firmware is ready[0m
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|
[0m[DEBUG] ME: Checking whether CPU was replaced... not replaced[0m
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|
[0m[DEBUG] HSIO lane owner: 0x05[0m
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[0m[DEBUG] SATA port enables: 0x3f[0m
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[0m[DEBUG] USB2 port 0 => mapped to OC pin 0[0m
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[0m[DEBUG] USB2 port 1 => mapped to OC pin 0[0m
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[0m[DEBUG] USB2 port 2 => mapped to OC pin 1[0m
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[0m[DEBUG] USB2 port 3 => not mapped to OC pin[0m
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[0m[DEBUG] USB2 port 4 => not mapped to OC pin[0m
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|
[0m[DEBUG] USB2 port 5 => mapped to OC pin 2[0m
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[0m[DEBUG] USB2 port 6 => mapped to OC pin 3[0m
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[0m[DEBUG] USB2 port 7 => mapped to OC pin 3[0m
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|
[0m[DEBUG] USB2 port 8 => mapped to OC pin 4[0m
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[0m[DEBUG] USB2 port 9 => mapped to OC pin 4[0m
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[0m[DEBUG] USB2 port 10 => mapped to OC pin 5[0m
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[0m[DEBUG] USB2 port 11 => mapped to OC pin 5[0m
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[0m[DEBUG] USB2 port 12 => mapped to OC pin 6[0m
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[0m[DEBUG] USB2 port 13 => mapped to OC pin 6[0m
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[0m
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[0m[DEBUG] USB3 port 0 => mapped to OC pin 0[0m
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[0m[DEBUG] USB3 port 1 => mapped to OC pin 0[0m
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[0m[DEBUG] USB3 port 2 => not mapped to OC pin[0m
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[0m[DEBUG] USB3 port 3 => not mapped to OC pin[0m
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[0m[DEBUG] USB3 port 4 => mapped to OC pin 1[0m
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[0m[DEBUG] USB3 port 5 => mapped to OC pin 1[0m
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[0m
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[0m[DEBUG] Retraining DMI at Gen2 speeds...[0m
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[0m[DEBUG] DMI: Running at Gen1 x4[0m
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[0m[DEBUG] DMI: Running at Gen1 x4[0m
|
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[0m[INFO ] DMI: Running at Gen2 x4[0m
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[0m[DEBUG] Programming SA DMI VC/TC mappings...[0m
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|
[0m[DEBUG] Programming PCH DMI VC/TC mappings...[0m
|
|
[0m[DEBUG] Waiting for PCH DMI VC negotiation... done![0m
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|
[0m[DEBUG] Waiting for SA DMI VC negotiation... done![0m
|
|
[0m[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)[0m
|
|
[0m[INFO ] Using cached memory parameters[0m
|
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[0m[DEBUG] Initial bootmode: BOOTMODE_COLD[0m
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[0m[DEBUG] Current bootmode: BOOTMODE_FAST[0m
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[0m
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[0m[DEBUG] Starting native raminit[0m
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[0m
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[0m[DEBUG] Executing raminit task PROCSPD[0m
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[0m[DEBUG] CH0S0 is slotted and DDR3[0m
|
|
[0m[DEBUG] CH1S0 is slotted and not DDR3, ignoring[0m
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|
[0m
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|
[0m[DEBUG] CH0S0 SPD:[0m
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|
[0m[DEBUG] Revision : 13[0m
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|
[0m[DEBUG] Type : b[0m
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|
[0m[DEBUG] Key : 3[0m
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|
[0m[DEBUG] Banks : 8[0m
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[0m[DEBUG] Capacity : 8 Gb[0m
|
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[0m[DEBUG] Supported voltages : 1.35V 1.5V[0m
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[0m[DEBUG] SDRAM width : 8[0m
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|
[0m[DEBUG] Bus extension : 0 bits[0m
|
|
[0m[DEBUG] Bus width : 64[0m
|
|
[0m[DEBUG] FTB timings : yes[0m
|
|
[0m[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6[0m
|
|
[0m[DEBUG] Thermal features : ASR ext_temp_range[0m
|
|
[0m[DEBUG] Thermal sensor : no[0m
|
|
[0m[DEBUG] Standard SDRAM : yes[0m
|
|
[0m[DEBUG] Rank1 Address bits : normal[0m
|
|
[0m[DEBUG] DIMM Reference card: F[0m
|
|
[0m[DEBUG] Manufacturer ID : 2c80[0m
|
|
[0m[DEBUG] Part number : 16KTF2G64HZ-1G6A[0m
|
|
[0m[INFO ] Row addr bits : 16[0m
|
|
[0m[INFO ] Column addr bits : 11[0m
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|
[0m[INFO ] Number of ranks : 2[0m
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|
[0m[INFO ] DIMM Capacity : 16384 MB[0m
|
|
[0m[INFO ] Vdd Min : 1300 mV[0m
|
|
[0m[INFO ] Vdd Max : 1500 mV[0m
|
|
[0m[INFO ] CAS latencies : 5 6 7 8 9 10 11[0m
|
|
[0m[INFO ] tCKmin : 1.250 ns[0m
|
|
[0m[INFO ] tAAmin : 13.125 ns[0m
|
|
[0m[INFO ] tWRmin : 15.000 ns[0m
|
|
[0m[INFO ] tRCDmin : 13.125 ns[0m
|
|
[0m[INFO ] tRRDmin : 7.500 ns[0m
|
|
[0m[INFO ] tRPmin : 13.125 ns[0m
|
|
[0m[INFO ] tRASmin : 35.000 ns[0m
|
|
[0m[INFO ] tRCmin : 48.125 ns[0m
|
|
[0m[INFO ] tRFCmin : 350.000 ns[0m
|
|
[0m[INFO ] tWTRmin : 7.500 ns[0m
|
|
[0m[INFO ] tRTPmin : 7.500 ns[0m
|
|
[0m[INFO ] tFAWmin : 40.000 ns[0m
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|
[0m
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[0m
|
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[0m[DEBUG] Executing raminit task RST_NONT[0m
|
|
[1;4m[WARN ] Cannot fast boot: DIMMs have changed[0m
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|
[0m
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[7m[ERROR] raminit failed on step RST_NONT[0m
|
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[0m[DEBUG] +------------------+------------+[0m
|
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[0m[DEBUG] | Task | msecs |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
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[0m[DEBUG] | PROCSPD | 194 |[0m
|
|
[0m[DEBUG] | RST_NONT | 5 |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | Total | 200 |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task PROCSPD[0m
|
|
[0m[DEBUG] CH0S0 is slotted and DDR3[0m
|
|
[0m[DEBUG] CH1S0 is slotted and not DDR3, ignoring[0m
|
|
[0m
|
|
[0m[DEBUG] CH0S0 SPD:[0m
|
|
[0m[DEBUG] Revision : 13[0m
|
|
[0m[DEBUG] Type : b[0m
|
|
[0m[DEBUG] Key : 3[0m
|
|
[0m[DEBUG] Banks : 8[0m
|
|
[0m[DEBUG] Capacity : 8 Gb[0m
|
|
[0m[DEBUG] Supported voltages : 1.35V 1.5V[0m
|
|
[0m[DEBUG] SDRAM width : 8[0m
|
|
[0m[DEBUG] Bus extension : 0 bits[0m
|
|
[0m[DEBUG] Bus width : 64[0m
|
|
[0m[DEBUG] FTB timings : yes[0m
|
|
[0m[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6[0m
|
|
[0m[DEBUG] Thermal features : ASR ext_temp_range[0m
|
|
[0m[DEBUG] Thermal sensor : no[0m
|
|
[0m[DEBUG] Standard SDRAM : yes[0m
|
|
[0m[DEBUG] Rank1 Address bits : normal[0m
|
|
[0m[DEBUG] DIMM Reference card: F[0m
|
|
[0m[DEBUG] Manufacturer ID : 2c80[0m
|
|
[0m[DEBUG] Part number : 16KTF2G64HZ-1G6A[0m
|
|
[0m[INFO ] Row addr bits : 16[0m
|
|
[0m[INFO ] Column addr bits : 11[0m
|
|
[0m[INFO ] Number of ranks : 2[0m
|
|
[0m[INFO ] DIMM Capacity : 16384 MB[0m
|
|
[0m[INFO ] Vdd Min : 1300 mV[0m
|
|
[0m[INFO ] Vdd Max : 1500 mV[0m
|
|
[0m[INFO ] CAS latencies : 5 6 7 8 9 10 11[0m
|
|
[0m[INFO ] tCKmin : 1.250 ns[0m
|
|
[0m[INFO ] tAAmin : 13.125 ns[0m
|
|
[0m[INFO ] tWRmin : 15.000 ns[0m
|
|
[0m[INFO ] tRCDmin : 13.125 ns[0m
|
|
[0m[INFO ] tRRDmin : 7.500 ns[0m
|
|
[0m[INFO ] tRPmin : 13.125 ns[0m
|
|
[0m[INFO ] tRASmin : 35.000 ns[0m
|
|
[0m[INFO ] tRCmin : 48.125 ns[0m
|
|
[0m[INFO ] tRFCmin : 350.000 ns[0m
|
|
[0m[INFO ] tWTRmin : 7.500 ns[0m
|
|
[0m[INFO ] tRTPmin : 7.500 ns[0m
|
|
[0m[INFO ] tFAWmin : 40.000 ns[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task INITMPLL[0m
|
|
[0m[DEBUG] PLL_REF100_CFG value: 0x2[0m
|
|
[0m[DEBUG] 100MHz reference clock support: yes[0m
|
|
[0m[DEBUG] With tCK 320, try CAS: 11 OK[0m
|
|
[0m[DEBUG] Found compatible clock / CAS settings[0m
|
|
[0m[DEBUG] Selected DRAM frequency: 800 MHz[0m
|
|
[0m[DEBUG] Selected CAS latency : 11T[0m
|
|
[0m[DEBUG] MC_BIOS_REQ = 0x80000006[0m
|
|
[0m[DEBUG] MPLL busy... done in 7 us[0m
|
|
[0m[DEBUG] MC_BIOS_DATA = 0x00000006[0m
|
|
[0m[DEBUG] MPLL frequency is set to: 800 MHz (period: 1250000 femtoseconds)[0m
|
|
[0m[DEBUG] Quadrature clock period: 625 picoseconds[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task CONVTIM[0m
|
|
[0m[DEBUG] tCMD was zero, picking a guesstimate value[0m
|
|
[0m[DEBUG] Selected tCK : 1250 ps[0m
|
|
[0m[DEBUG] Selected tAA : 11T[0m
|
|
[0m[DEBUG] Selected tWR : 12T[0m
|
|
[0m[DEBUG] Selected tRCD : 11T[0m
|
|
[0m[DEBUG] Selected tRRD : 6T[0m
|
|
[0m[DEBUG] Selected tRP : 11T[0m
|
|
[0m[DEBUG] Selected tRAS : 28T[0m
|
|
[0m[DEBUG] Selected tRC : 39T[0m
|
|
[0m[DEBUG] Selected tRFC : 280T[0m
|
|
[0m[DEBUG] Selected tWTR : 6T[0m
|
|
[0m[DEBUG] Selected tRTP : 6T[0m
|
|
[0m[DEBUG] Selected tFAW : 32T[0m
|
|
[0m[DEBUG] Selected tCWL : 8T[0m
|
|
[0m[DEBUG] Selected tCMD : 1T[0m
|
|
[0m[DEBUG] Selected tREFI : 6240T[0m
|
|
[0m[DEBUG] Selected tXP : 5T[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task CONFMC[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task MEMMAP[0m
|
|
[0m[DEBUG] ME: Requested 0MB UMA[0m
|
|
[0m[DEBUG] ============ MEMORY MAP ============[0m
|
|
[0m
|
|
[0m[DEBUG] dpr_size = 0 MiB[0m
|
|
[0m[DEBUG] tseg_size = 8 MiB[0m
|
|
[0m[DEBUG] gtt_size = 2 MiB[0m
|
|
[0m[DEBUG] gms_size = 64 MiB[0m
|
|
[0m[DEBUG] me_stolen_size = 0 MiB[0m
|
|
[0m
|
|
[0m[DEBUG] touud = 18366 MiB[0m
|
|
[0m[DEBUG] remaplimit = 18365 MiB[0m
|
|
[0m[DEBUG] remapbase = 16384 MiB[0m
|
|
[0m[DEBUG] tom = 16384 MiB[0m
|
|
[0m[DEBUG] tom_minus_me = 16384 MiB[0m
|
|
[0m[DEBUG] tolud = 2114 MiB[0m
|
|
[0m[DEBUG] bdsm_base = 2050 MiB[0m
|
|
[0m[DEBUG] gtt_base = 2048 MiB[0m
|
|
[0m[DEBUG] tseg_base = 2040 MiB[0m
|
|
[0m
|
|
[0m[DEBUG] reclaim_possible = Yes[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task JEDECINIT[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task PRETRAIN[0m
|
|
[0m[DEBUG] C0S0:[0m
|
|
[0m[DEBUG] MR0: 0x0d70[0m
|
|
[0m[DEBUG] MR1: 0x0002[0m
|
|
[0m[DEBUG] MR2: 0x0258[0m
|
|
[0m[DEBUG] MR3: 0x0000[0m
|
|
[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task SOT[0m
|
|
[0m[DEBUG] Stage 1: Vref offset training[0m
|
|
[0m[DEBUG] Plot of sum_bits across Vref settings[0m
|
|
[0m[DEBUG] Channel 0 [0m
|
|
[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
|
[0m[DEBUG] 1/2 Vref[0m
|
|
[0m[DEBUG] -15 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -14 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -13 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -12 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -11 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -10 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -9 0 0 1 0 0 0 0 0 [0m
|
|
[0m[DEBUG] -8 1 0 1 1 2 1 0 0 [0m
|
|
[0m[DEBUG] -7 1 0 2 2 3 1 2 2 [0m
|
|
[0m[DEBUG] -6 7 6 8 3 5 3 3 2 [0m
|
|
[0m[DEBUG] -5 7 6 8 6 7 4 7 6 [0m
|
|
[0m[DEBUG] -4 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] -3 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] -2 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] -1 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 0 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 1 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 2 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 3 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 4 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 5 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 6 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 7 8 8 8 8 8 8 8 8 [0m
|
|
[0m[DEBUG] 8 8 8 8 8 8 7 8 8 [0m
|
|
[0m[DEBUG] 9 8 8 7 6 8 7 8 7 [0m
|
|
[0m[DEBUG] 10 8 8 7 3 6 6 8 6 [0m
|
|
[0m[DEBUG] 11 4 2 3 3 4 5 4 2 [0m
|
|
[0m[DEBUG] 12 4 2 3 1 2 2 3 1 [0m
|
|
[0m[DEBUG] 13 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] 14 0 0 0 0 0 0 0 0 [0m
|
|
[0m[DEBUG] 15 0 0 0 0 0 0 0 0 [0m
|
|
[0m
|
|
[0m[DEBUG] Hi-Lo (XOR):[0m
|
|
[0m[DEBUG] C0: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff[0m
|
|
[0m
|
|
[0m[DEBUG] RdVref:[0m
|
|
[0m[DEBUG] C0: 2 2 1 1 1 1 2 1[0m
|
|
[0m
|
|
[0m[DEBUG] Stage 2: Samp offset training[0m
|
|
[0m[DEBUG] Channel 0 [0m
|
|
[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
|
[0m[DEBUG] Bits 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567 [0m
|
|
[0m[DEBUG] SAmp[0m
|
|
[0m[DEBUG] 1 ........ ........ ........ ........ ........ ........ ........ ........ [0m
|
|
[0m[DEBUG] 2 ........ ........ ........ ........ ........ ........ ........ ........ [0m
|
|
[0m[DEBUG] 3 ........ ........ ........ ........ ........ ........ ........ ........ [0m
|
|
[0m[DEBUG] 4 ........ ........ ........ ........ ........ ........ ........ ........ [0m
|
|
[0m[DEBUG] 5 ........ ........ ........ ........ ........ ........ ........ ........ [0m
|
|
[0m[DEBUG] 6 .......# ........ .......# ........ ........ .....#.. ........ ........ [0m
|
|
[0m[DEBUG] 7 ..####.# .#.#.### .......# #....... ........ ..#..#.. #..#.##. #...#... [0m
|
|
[0m[DEBUG] 8 ######## .###.### .###.#.# ##.#..#. ###...#. ..#..#.# ######## ##..#... [0m
|
|
[0m[DEBUG] 9 ######## ######## ######## ##.#.##. ####.##. ..#..#.# ######## #####... [0m
|
|
[0m[DEBUG] 10 ######## ######## ######## ######## ####.### ######## ######## ######## [0m
|
|
[0m[DEBUG] 11 ######## ######## ######## ######## ######## ######## ######## ######## [0m
|
|
[0m[DEBUG] 12 ######## ######## ######## ######## ######## ######## ######## ######## [0m
|
|
[0m[DEBUG] 13 ######## ######## ######## ######## ######## ######## ######## ######## [0m
|
|
[0m[DEBUG] 14 ######## ######## ######## ######## ######## ######## ######## ######## [0m
|
|
[0m[DEBUG] 15 ######## ######## ######## ######## ######## ######## ######## ######## [0m
|
|
[0m
|
|
[0m[DEBUG] BitSAmp 77666675 86768666 87778785 67979879 7778a879 99699597 67767667 67886999 [0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task RCVET[0m
|
|
[0m[DEBUG] Rank 0[0m
|
|
[0m[DEBUG] Steps 1 and 2: Find middle of high region[0m
|
|
[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
|
[0m[DEBUG] RcvEn[0m
|
|
[0m[DEBUG] 280 # . # . . # . # [0m
|
|
[0m[DEBUG] 288 . . # # . # # # [0m
|
|
[0m[DEBUG] 296 . . . # . # # # [0m
|
|
[0m[DEBUG] 304 . . . # . # # # [0m
|
|
[0m[DEBUG] 312 . . . # # . # # [0m
|
|
[0m[DEBUG] 320 . . . # # . # # [0m
|
|
[0m[DEBUG] 328 . # . # # . # # [0m
|
|
[0m[DEBUG] 336 . # . # # . # # [0m
|
|
[0m[DEBUG] 344 . # . # # . # . [0m
|
|
[0m[DEBUG] 352 # # . . # . . . [0m
|
|
[0m[DEBUG] 360 # # # . # . . . [0m
|
|
[0m[DEBUG] 368 # # # . # . . . [0m
|
|
[0m[DEBUG] 376 # # # . . # . . [0m
|
|
[0m[DEBUG] 384 # . # . . # . . [0m
|
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[0m[DEBUG] 392 # . # . . # . . [0m
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[0m[DEBUG] 400 # . # . . # . . [0m
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[0m
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[0m[DEBUG] Update RcvEn timing to be in the center of high region[0m
|
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[0m[DEBUG] C0.R0: Left Right Width Center[0m
|
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[0m[DEBUG] B0: 288 344 56 316[0m
|
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[0m[DEBUG] B1: 256 320 64 288[0m
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[0m[DEBUG] B2: 296 352 56 324[0m
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[0m[DEBUG] B3: 224 280 56 252[0m
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[0m[DEBUG] B4: 248 304 56 276[0m
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[0m[DEBUG] B5: 312 368 56 340[0m
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[0m[DEBUG] B6: 224 280 56 252[0m
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[0m[DEBUG] B7: 344 400 56 372[0m
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[0m
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[0m[DEBUG] Step 3: Quarter preamble - Walk backwards[0m
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[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
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[0m[DEBUG] IOLAT[0m
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[0m[DEBUG] 0 H H H H H H H H [0m
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[0m[DEBUG] 2 H H H H H H H H [0m
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[0m[DEBUG] 4 H H H H H H H H [0m
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[0m[DEBUG] 6 H H H H L H L H [0m
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[0m[DEBUG] 6 L L L L L L L L [0m
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[0m
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[0m[DEBUG] C0: Preamble[0m
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[0m[DEBUG] B0: 188[0m
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[0m[DEBUG] B1: 160[0m
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[0m[DEBUG] B2: 196[0m
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[0m[DEBUG] B3: 124[0m
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[0m[DEBUG] B4: 276[0m
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[0m[DEBUG] B5: 212[0m
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[0m[DEBUG] B6: 252[0m
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[0m[DEBUG] B7: 244[0m
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[0m
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[0m[DEBUG] Step 4: Add 1 qclk[0m
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[0m
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[0m[DEBUG] Step 5: Walk forward to find rising edge[0m
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[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
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[0m[DEBUG] inc[0m
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[0m[DEBUG] 0 # # # # # # # # [0m
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[0m[DEBUG] 1 # # # # # # # # [0m
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[0m[DEBUG] 2 # # # # # # # # [0m
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[0m[DEBUG] 14 # # # # # # # # [0m
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[0m[DEBUG] 15 # # # # # # # # [0m
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[0m[DEBUG] 16 # # # # # # # # [0m
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[0m[DEBUG] 17 # # # # # # # # [0m
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[0m[DEBUG] 18 # # # # # # # # [0m
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[0m[DEBUG] 19 # # # # # # # # [0m
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[0m[DEBUG] 20 # # # # # # # # [0m
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[0m[DEBUG] 21 # # # # # # # # [0m
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[0m[DEBUG] 22 # # # # # # # # [0m
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[0m[DEBUG] 23 # # # # # # # # [0m
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[0m[DEBUG] 24 # # # # # # # # [0m
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[0m[DEBUG] 25 # # # # # # # # [0m
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[0m[DEBUG] 26 # # # # . # # # [0m
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[0m[DEBUG] 27 # # # # . # . # [0m
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[0m[DEBUG] 28 # # # # . # . # [0m
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[0m[DEBUG] 29 # # # # . # . # [0m
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[0m[DEBUG] 30 # # # # . . . # [0m
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[0m[DEBUG] 31 . # # # . . . . [0m
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[0m[DEBUG] 32 . # # # . . . . [0m
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[0m[DEBUG] 33 . . . . . . . . [0m
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[0m
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[0m[DEBUG] Step 6: center on preamble and clean up rank[0m
|
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[0m[DEBUG] C0: Preamble increment[0m
|
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[0m[DEBUG] B0: 219 30[0m
|
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[0m[DEBUG] B1: 193 32[0m
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[0m[DEBUG] B2: 229 32[0m
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[0m[DEBUG] B3: 157 32[0m
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[0m[DEBUG] B4: 302 25[0m
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[0m[DEBUG] B5: 242 29[0m
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[0m[DEBUG] B6: 279 26[0m
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[0m[DEBUG] B7: 275 30[0m
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[0m
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[0m
|
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[0m[DEBUG] Rank 1[0m
|
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[0m[DEBUG] Steps 1 and 2: Find middle of high region[0m
|
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[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
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[0m[DEBUG] RcvEn[0m
|
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[0m[DEBUG] 280 # . # . . # . # [0m
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[0m[DEBUG] 288 . . # # . # # # [0m
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[0m[DEBUG] 296 . . . # . # # # [0m
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[0m[DEBUG] 304 . . . # # . # # [0m
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[0m[DEBUG] 312 . . . # # . # # [0m
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[0m[DEBUG] 320 . # . # # . # # [0m
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[0m[DEBUG] 328 . # . # # . # # [0m
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[0m[DEBUG] 336 . # . # # . # # [0m
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[0m[DEBUG] 344 . # . # # . . . [0m
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[0m[DEBUG] 352 # # . . # . . . [0m
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[0m[DEBUG] 360 # # # . # . . . [0m
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[0m[DEBUG] 368 # # # . . . . . [0m
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[0m[DEBUG] 376 # # # . . # . . [0m
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[0m[DEBUG] 384 # . # . . # . . [0m
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[0m[DEBUG] 392 # . # . . # . . [0m
|
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[0m[DEBUG] 400 # . # . . # . . [0m
|
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[0m
|
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[0m[DEBUG] Update RcvEn timing to be in the center of high region[0m
|
|
[0m[DEBUG] C0.R1: Left Right Width Center[0m
|
|
[0m[DEBUG] B0: 288 344 56 316[0m
|
|
[0m[DEBUG] B1: 256 312 56 284[0m
|
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[0m[DEBUG] B2: 296 352 56 324[0m
|
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[0m[DEBUG] B3: 224 280 56 252[0m
|
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[0m[DEBUG] B4: 240 296 56 268[0m
|
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[0m[DEBUG] B5: 304 368 64 336[0m
|
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[0m[DEBUG] B6: 216 280 64 248[0m
|
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[0m[DEBUG] B7: 344 400 56 372[0m
|
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[0m
|
|
[0m[DEBUG] Step 3: Quarter preamble - Walk backwards[0m
|
|
[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
|
[0m[DEBUG] IOLAT[0m
|
|
[0m[DEBUG] 0 H H H H H H H H [0m
|
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[0m[DEBUG] 2 H H H H H H H H [0m
|
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[0m[DEBUG] 4 H H H H H H H H [0m
|
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[0m[DEBUG] 6 H H H H L H L H [0m
|
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[0m[DEBUG] 6 L L L L L L L L [0m
|
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[0m
|
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[0m[DEBUG] C0: Preamble[0m
|
|
[0m[DEBUG] B0: 188[0m
|
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[0m[DEBUG] B1: 156[0m
|
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[0m[DEBUG] B2: 196[0m
|
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[0m[DEBUG] B3: 124[0m
|
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[0m[DEBUG] B4: 268[0m
|
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[0m[DEBUG] B5: 208[0m
|
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[0m[DEBUG] B6: 248[0m
|
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[0m[DEBUG] B7: 244[0m
|
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[0m
|
|
[0m[DEBUG] Step 4: Add 1 qclk[0m
|
|
[0m
|
|
[0m[DEBUG] Step 5: Walk forward to find rising edge[0m
|
|
[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
|
[0m[DEBUG] inc[0m
|
|
[0m[DEBUG] 0 # # # # # # # # [0m
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[0m[DEBUG] 1 # # # # # # # # [0m
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[0m[DEBUG] 2 # # # # # # # # [0m
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[0m[DEBUG] 3 # # # # # # # # [0m
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[0m[DEBUG] 4 # # # # # # # # [0m
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[0m[DEBUG] 5 # # # # # # # # [0m
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[0m[DEBUG] 6 # # # # # # # # [0m
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[0m[DEBUG] 7 # # # # # # # # [0m
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[0m[DEBUG] 8 # # # # # # # # [0m
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[0m[DEBUG] 9 # # # # # # # # [0m
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[0m[DEBUG] 10 # # # # # # # # [0m
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[0m[DEBUG] 11 # # # # # # # # [0m
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[0m[DEBUG] 12 # # # # # # # # [0m
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[0m[DEBUG] 13 # # # # # # # # [0m
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[0m[DEBUG] 14 # # # # # # # # [0m
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[0m[DEBUG] 15 # # # # # # # # [0m
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[0m[DEBUG] 16 # # # # # # # # [0m
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[0m[DEBUG] 17 # # # # # # # # [0m
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[0m[DEBUG] 18 # # # # # # # # [0m
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[0m[DEBUG] 19 # # # # # # # # [0m
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[0m[DEBUG] 20 # # # # # # # # [0m
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[0m[DEBUG] 21 # # # # # # # # [0m
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[0m[DEBUG] 22 # # # # # # # # [0m
|
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[0m[DEBUG] 23 # # # # # # # # [0m
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[0m[DEBUG] 24 # # # # # # # # [0m
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[0m[DEBUG] 25 # # # # # # # # [0m
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[0m[DEBUG] 26 # # # # # # # # [0m
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[0m[DEBUG] 27 . # # # # # # # [0m
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[0m[DEBUG] 28 . # # # # # # # [0m
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[0m[DEBUG] 29 . # # . # # # # [0m
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[0m[DEBUG] 30 . # # . # . # # [0m
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[0m[DEBUG] 31 . # # . # . . # [0m
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[0m[DEBUG] 32 . # # . . . . # [0m
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[0m[DEBUG] 33 . # . . . . . # [0m
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[0m[DEBUG] 34 . # . . . . . . [0m
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[0m[DEBUG] 35 . # . . . . . . [0m
|
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[0m[DEBUG] 36 . . . . . . . . [0m
|
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[0m
|
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[0m[DEBUG] Step 6: center on preamble and clean up rank[0m
|
|
[0m[DEBUG] C0: Preamble increment[0m
|
|
[0m[DEBUG] B0: 215 26[0m
|
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[0m[DEBUG] B1: 192 35[0m
|
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[0m[DEBUG] B2: 229 32[0m
|
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[0m[DEBUG] B3: 153 28[0m
|
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[0m[DEBUG] B4: 300 31[0m
|
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[0m[DEBUG] B5: 238 29[0m
|
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[0m[DEBUG] B6: 279 30[0m
|
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[0m[DEBUG] B7: 278 33[0m
|
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[0m
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[0m
|
|
[0m[DEBUG] Step 7: Sync IO latency across all ranks[0m
|
|
[0m
|
|
[0m[DEBUG] Final Receive Enable and IO latency settings:[0m
|
|
[0m[DEBUG] C0.R0: IOLAT = 7 rt_iocomp = 23[0m
|
|
[0m[DEBUG] B0: 283[0m
|
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[0m[DEBUG] B1: 257[0m
|
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[0m[DEBUG] B2: 293[0m
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[0m[DEBUG] B3: 221[0m
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[0m[DEBUG] B4: 366[0m
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[0m[DEBUG] B5: 306[0m
|
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[0m[DEBUG] B6: 343[0m
|
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[0m[DEBUG] B7: 339[0m
|
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[0m
|
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[0m[DEBUG] C0.R1: IOLAT = 7 rt_iocomp = 23[0m
|
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[0m[DEBUG] B0: 279[0m
|
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[0m[DEBUG] B1: 256[0m
|
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[0m[DEBUG] B2: 293[0m
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[0m[DEBUG] B3: 217[0m
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[0m[DEBUG] B4: 364[0m
|
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[0m[DEBUG] B5: 302[0m
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[0m[DEBUG] B6: 343[0m
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[0m[DEBUG] B7: 342[0m
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[0m
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[0m
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[0m
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[0m[DEBUG] Executing raminit task RDMPRT[0m
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[0m[DEBUG] Rank 0[0m
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[0m[DEBUG] Channel 0 [0m
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[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
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[0m[DEBUG] DqsDelay[0m
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[0m[DEBUG] -32 # # # # # # # # [0m
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[0m[DEBUG] -31 # # # # # # # # [0m
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[0m[DEBUG] -30 # # # # # # # # [0m
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[0m[DEBUG] -29 # # # # # # # # [0m
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[0m[DEBUG] -28 # # # # # # # # [0m
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[0m[DEBUG] -27 # # # # # # # # [0m
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[0m[DEBUG] -26 # # # # # # # # [0m
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[0m[DEBUG] -25 # # # # # # # # [0m
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[0m[DEBUG] -24 # # # # # # # # [0m
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[0m[DEBUG] -23 # # # # # # # # [0m
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[0m[DEBUG] -22 # # # # # # # # [0m
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[0m[DEBUG] -21 # # # # # # # # [0m
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[0m[DEBUG] -20 # # # # . # # # [0m
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[0m[DEBUG] -19 # # # # . # # # [0m
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[0m[DEBUG] -18 # . . # . # . # [0m
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[0m[DEBUG] -17 # . . . . . . # [0m
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[0m[DEBUG] -16 . . . . . . . . [0m
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[0m[DEBUG] -15 . . . . . . . . [0m
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[0m[DEBUG] -14 . . . . . . . . [0m
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[0m[DEBUG] -13 . . . . . . . . [0m
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[0m[DEBUG] -12 . . . . . . . . [0m
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[0m[DEBUG] -11 . . . . . . . . [0m
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[0m[DEBUG] -10 . . . . . . . . [0m
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[0m[DEBUG] -9 . . . . . . . . [0m
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[0m[DEBUG] -8 . . . . . . . . [0m
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[0m[DEBUG] -7 . . . . . . . . [0m
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[0m[DEBUG] -6 . . . . . . . . [0m
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[0m[DEBUG] -5 . . . . . . . . [0m
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[0m[DEBUG] -4 . . . . . . . . [0m
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[0m[DEBUG] -3 . . . . . . . . [0m
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[0m[DEBUG] -2 . . . . . . . . [0m
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[0m[DEBUG] -1 . . . . . . . . [0m
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[0m[DEBUG] 0 . . . . . . . . [0m
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[0m[DEBUG] 1 . . . . . . . . [0m
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[0m[DEBUG] 2 . . . . . . . . [0m
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[0m[DEBUG] 3 . . . . . . . . [0m
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[0m[DEBUG] 4 . . . . . . . . [0m
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[0m[DEBUG] 5 . . . . . . . . [0m
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[0m[DEBUG] 6 . . . . . . . . [0m
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[0m[DEBUG] 7 . . . . . . . . [0m
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[0m[DEBUG] 8 . . . . . . . . [0m
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[0m[DEBUG] 9 . . . . . . . . [0m
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[0m[DEBUG] 10 . . . . . . . . [0m
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[0m[DEBUG] 11 . . . . . . . . [0m
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[0m[DEBUG] 12 . . . . . . . . [0m
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[0m[DEBUG] 13 . . . . . . . . [0m
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[0m[DEBUG] 14 . . . . . . . . [0m
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[0m[DEBUG] 15 . . . . . . . . [0m
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[0m[DEBUG] 16 . . . . . . . . [0m
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[0m[DEBUG] 17 . . . . . . . . [0m
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[0m[DEBUG] 18 . . . . . . . . [0m
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[0m[DEBUG] 19 . . . . . . . . [0m
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[0m[DEBUG] 20 . . . . . . . . [0m
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[0m[DEBUG] 21 . . . . . . . . [0m
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[0m[DEBUG] 22 . . . . . . . . [0m
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[0m[DEBUG] 23 . . . . . . . . [0m
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[0m[DEBUG] 24 . . . . . . . . [0m
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[0m[DEBUG] 25 . . . . . . . . [0m
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[0m[DEBUG] 26 . . . . . . . . [0m
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[0m[DEBUG] 27 . . . . . . . . [0m
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[0m[DEBUG] 28 . . . . . . . . [0m
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[0m[DEBUG] 29 . . # . . . . . [0m
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[0m[DEBUG] 30 . . # . . . . . [0m
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[0m[DEBUG] 31 . . # . . . . . [0m
|
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[0m
|
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[0m[DEBUG] C0.R0: Left Right Width Center RxDqsPN[0m
|
|
[0m[DEBUG] B0: -16 31 47 7 39[0m
|
|
[0m[DEBUG] B1: -18 31 49 6 38[0m
|
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[0m[DEBUG] B2: -18 28 46 5 37[0m
|
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[0m[DEBUG] B3: -17 31 48 7 39[0m
|
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[0m[DEBUG] B4: -20 31 51 5 37[0m
|
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[0m[DEBUG] B5: -17 31 48 7 39[0m
|
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[0m[DEBUG] B6: -18 31 49 6 38[0m
|
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[0m[DEBUG] B7: -16 31 47 7 39[0m
|
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[0m
|
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[0m[DEBUG] Rank 1[0m
|
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[0m[DEBUG] Channel 0 [0m
|
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[0m[DEBUG] Byte 0 1 2 3 4 5 6 7 [0m
|
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[0m[DEBUG] DqsDelay[0m
|
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[0m[DEBUG] -32 # # # # # # # # [0m
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[0m[DEBUG] -31 # # # # # # # # [0m
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[0m[DEBUG] -30 # # # # # # # # [0m
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[0m[DEBUG] -29 # # # # # # # # [0m
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[0m[DEBUG] -28 # # # # # # # # [0m
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[0m[DEBUG] -27 # # # # # # # # [0m
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[0m[DEBUG] -26 # # # # # # # # [0m
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[0m[DEBUG] -25 # # # # # # # # [0m
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[0m[DEBUG] -24 # # # # # # # # [0m
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[0m[DEBUG] -23 # # # # # # # # [0m
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[0m[DEBUG] -22 # # # # . # # # [0m
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[0m[DEBUG] -21 # # # # . # # # [0m
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[0m[DEBUG] -20 # # # # . # # # [0m
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[0m[DEBUG] -19 # . # # . # # # [0m
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[0m[DEBUG] -18 # . . # . # . # [0m
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[0m[DEBUG] -17 # . . # . # . # [0m
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[0m[DEBUG] -16 . . . . . . . . [0m
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[0m[DEBUG] -15 . . . . . . . . [0m
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[0m[DEBUG] -14 . . . . . . . . [0m
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[0m[DEBUG] -13 . . . . . . . . [0m
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[0m[DEBUG] -12 . . . . . . . . [0m
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[0m[DEBUG] -11 . . . . . . . . [0m
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[0m[DEBUG] -10 . . . . . . . . [0m
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[0m[DEBUG] -9 . . . . . . . . [0m
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[0m[DEBUG] -8 . . . . . . . . [0m
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[0m[DEBUG] -7 . . . . . . . . [0m
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[0m[DEBUG] -6 . . . . . . . . [0m
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[0m[DEBUG] -5 . . . . . . . . [0m
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[0m[DEBUG] -4 . . . . . . . . [0m
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[0m[DEBUG] -3 . . . . . . . . [0m
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[0m[DEBUG] -2 . . . . . . . . [0m
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[0m[DEBUG] -1 . . . . . . . . [0m
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[0m[DEBUG] 0 . . . . . . . . [0m
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[0m[DEBUG] 1 . . . . . . . . [0m
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[0m[DEBUG] 2 . . . . . . . . [0m
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[0m[DEBUG] 3 . . . . . . . . [0m
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[0m[DEBUG] 4 . . . . . . . . [0m
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|
|
[0m
|
|
[0m[DEBUG] Executing raminit task OPTCOMP[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task POSTTRAIN[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task ACTIVATE[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task SAVE_TRAIN[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task SAVE_NONT[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task RAMINITEND[0m
|
|
[0m[DEBUG] Waiting for mc_init_done acknowledgement... DONE![0m
|
|
[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | Task | msecs |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | PROCSPD | 194 |[0m
|
|
[0m[DEBUG] | INITMPLL | 49 |[0m
|
|
[0m[DEBUG] | CONVTIM | 69 |[0m
|
|
[0m[DEBUG] | CONFMC | 0 |[0m
|
|
[0m[DEBUG] | MEMMAP | 66 |[0m
|
|
[0m[DEBUG] | JEDECINIT | 0 |[0m
|
|
[0m[DEBUG] | PRETRAIN | 14 |[0m
|
|
[0m[DEBUG] | SOT | 357 |[0m
|
|
[0m[DEBUG] | RCVET | 728 |[0m
|
|
[0m[DEBUG] | RDMPRT | 542 |[0m
|
|
[0m[DEBUG] | JWRL | 924 |[0m
|
|
[0m[DEBUG] | OPTCOMP | 0 |[0m
|
|
[0m[DEBUG] | POSTTRAIN | 0 |[0m
|
|
[0m[DEBUG] | ACTIVATE | 0 |[0m
|
|
[0m[DEBUG] | SAVE_TRAIN | 0 |[0m
|
|
[0m[DEBUG] | SAVE_NONT | 0 |[0m
|
|
[0m[DEBUG] | RAMINITEND | 5 |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | Total | 2954 |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] memcfg DDR3 clock 1600 MHz[0m
|
|
[0m[DEBUG] memcfg channel assignment: A: 0, B 1, C 2[0m
|
|
[0m[DEBUG] memcfg channel[0] config (00620040):[0m
|
|
[0m[DEBUG] ECC inactive[0m
|
|
[0m[DEBUG] enhanced interleave mode on[0m
|
|
[0m[DEBUG] rank interleave on[0m
|
|
[0m[DEBUG] DIMMA 16384 MB width x8 or x32 dual rank, selected[0m
|
|
[0m[DEBUG] DIMMB 0 MB width x8 or x32 single rank[0m
|
|
[0m[DEBUG] memcfg channel[1] config (00600000):[0m
|
|
[0m[DEBUG] ECC inactive[0m
|
|
[0m[DEBUG] enhanced interleave mode on[0m
|
|
[0m[DEBUG] rank interleave on[0m
|
|
[0m[DEBUG] DIMMA 0 MB width x8 or x32 single rank, selected[0m
|
|
[0m[DEBUG] DIMMB 0 MB width x8 or x32 single rank[0m
|
|
[0m[DEBUG] ME: Requested 0MB UMA[0m
|
|
[0m[DEBUG] ME: FW Partition Table : OK[0m
|
|
[0m[DEBUG] ME: Bringup Loader Failure : NO[0m
|
|
[0m[DEBUG] ME: Firmware Init Complete : NO[0m
|
|
[0m[DEBUG] ME: Manufacturing Mode : YES[0m
|
|
[0m[DEBUG] ME: Boot Options Present : NO[0m
|
|
[0m[DEBUG] ME: Update In Progress : NO[0m
|
|
[0m[DEBUG] ME: Current Working State : Initializing[0m
|
|
[0m[DEBUG] ME: Current Operation State : Bring up[0m
|
|
[0m[DEBUG] ME: Current Operation Mode : Debug[0m
|
|
[0m[DEBUG] ME: Error Code : No Error[0m
|
|
[0m[DEBUG] ME: Progress Phase : BUP Phase[0m
|
|
[0m[DEBUG] ME: Power Management Event : Clean Moff->Mx wake[0m
|
|
[0m[DEBUG] ME: Progress Phase State : 0x4d[0m
|
|
[0m[DEBUG] CBMEM:[0m
|
|
[0m[DEBUG] IMD: root @ 0x7f7ff000 254 entries.[0m
|
|
[0m[DEBUG] IMD: root @ 0x7f7fec00 62 entries.[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] External stage cache:[0m
|
|
[0m[DEBUG] IMD: root @ 0x7fbff000 254 entries.[0m
|
|
[0m[DEBUG] IMD: root @ 0x7fbfec00 62 entries.[0m
|
|
[0m[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)[0m
|
|
[0m[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.[0m
|
|
[0m[DEBUG] flash size 0x2800000 bytes[0m
|
|
[0m[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000[0m
|
|
[7m[ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!![0m
|
|
[0m[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.[0m
|
|
[0m[DEBUG] SF: Successfully written 2 bytes @ 0x800004[0m
|
|
[0m[DEBUG] SF: Successfully written 20 bytes @ 0x801040[0m
|
|
[0m[DEBUG] SF: Successfully written 4108 bytes @ 0x801054[0m
|
|
[0m[DEBUG] MRC: updated 'RW_MRC_CACHE'.[0m
|
|
[0m[DEBUG] SMM Memory Map[0m
|
|
[0m[DEBUG] SMRAM : 0x7f800000 0x800000[0m
|
|
[0m[DEBUG] Subregion 0: 0x7f800000 0x300000[0m
|
|
[0m[DEBUG] Subregion 1: 0x7fb00000 0x100000[0m
|
|
[0m[DEBUG] Subregion 2: 0x7fc00000 0x400000[0m
|
|
[0m[DEBUG] Normal boot[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/postcar' @0x500c0 size 0x6678 in mcache @0xff7e1064[0m
|
|
[0m[DEBUG] Loading module at 0x7f7cd000 with entry 0x7f7cd031. filesize: 0x6248 memsize: 0xc5f8[0m
|
|
[0m[DEBUG] Processing 252 relocs. Offset value of 0x7d7cd000[0m
|
|
[0m[DEBUG] BS: romstage times (exec / console): total (unknown) / 3819 ms[0m
|
|
[0m[DEBUG] usbdebug: postcar starting...[0m
|
|
[0m[DEBUG] Normal boot[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/ramstage' @0x2b440 size 0x1f537 in mcache @0x7f7dd0ec[0m
|
|
[0m[DEBUG] Loading module at 0x7f67e000 with entry 0x7f67e000. filesize: 0x3e0a0 memsize: 0x14d390[0m
|
|
[0m[DEBUG] Processing 4269 relocs. Offset value of 0x7b67e000[0m
|
|
[0m[DEBUG] BS: postcar times (exec / console): total (unknown) / 32 ms[0m
|
|
[0m[DEBUG] usbdebug: ramstage starting...[0m
|
|
[0m[DEBUG] Normal boot[0m
|
|
[0m[INFO ] Enumerating buses...[0m
|
|
[0m[DEBUG] Root Device scanning...[0m
|
|
[0m[DEBUG] CPU_CLUSTER: 0 enabled[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 enabled[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 [8086/0c04] enabled[0m
|
|
[0m[INFO ] PCI: Static device PCI: 00:00:01.0 not found, disabling it.[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 [8086/0c05] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 [8086/0416] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 [8086/0c0c] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 [8086/0c03] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 [8086/8c31] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 [8086/8c3a] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:16.1: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:16.2: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:16.3: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 [8086/153a] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 [8086/8c2d] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 [8086/8c20] enabled[0m
|
|
[0m[DEBUG] PCIe Root Port 1 ASPM is disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 [8086/8c10] enabled[0m
|
|
[0m[DEBUG] PCIe Root Port 2 ASPM is disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 [8086/8c12] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.2 [8086/8c14] disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.3 [8086/8c16] disabled[0m
|
|
[0m[DEBUG] Adjusted number of PCIe root ports to 5 as per strpfusecfg2[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.2: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.3: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.4: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.4 [8086/8c18] disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 [8086/8c26] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 [8086/8c4f] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 [8086/8c01] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 [8086/8c22] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.5: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.5 [8086/8c09] disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.6: Disabling device[0m
|
|
[1;4m[WARN ] PCI: Leftover static devices:[0m
|
|
[1;4m[WARN ] PCI: 00:00:01.0[0m
|
|
[1;4m[WARN ] PCI: 00:00:16.1[0m
|
|
[1;4m[WARN ] PCI: 00:00:16.2[0m
|
|
[1;4m[WARN ] PCI: 00:00:16.3[0m
|
|
[1;4m[WARN ] PCI: 00:00:1c.5[0m
|
|
[1;4m[WARN ] PCI: 00:00:1c.6[0m
|
|
[1;4m[WARN ] PCI: 00:00:1c.7[0m
|
|
[1;4m[WARN ] PCI: 00:00:1f.6[0m
|
|
[1;4m[WARN ] PCI: Check your devicetree.cb.[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01[0m
|
|
[0m[INFO ] PCI: 00:00:01.1: Setting Max_Payload_Size to 128 for devices under this root port[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:01.1 finished in 14 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 [10ec/5227] enabled[0m
|
|
[0m[INFO ] Enabling Common Clock Configuration[0m
|
|
[0m[INFO ] ASPM: Enabled L0s and L1[0m
|
|
[0m[INFO ] PCI: 00:02:00.0: Enabled LTR[0m
|
|
[0m[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 31 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03[0m
|
|
[0m[INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 14 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 scanning...[0m
|
|
[0m[DEBUG] No CMOS option 'touchpad'.[0m
|
|
[0m[INFO ] PMH7: ID 05 Revision 01[0m
|
|
[0m[DEBUG] PNP: 00ff.1 enabled[0m
|
|
[0m[INFO ] H8: EC Firmware ID GLHT30WW-3.23, Version 3.01B[0m
|
|
[0m[DEBUG] No CMOS option 'bluetooth'.[0m
|
|
[0m[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed[0m
|
|
[0m[DEBUG] No CMOS option 'wwan'.[0m
|
|
[0m[DEBUG] PNP: 00ff.2 enabled[0m
|
|
[0m[INFO ] Found TPM 1.2 ST33ZP24 (0x0000) by ST Microelectronics (0x104a)[0m
|
|
[0m[DEBUG] PNP: 0c31.0 enabled[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 45 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 scanning...[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs[0m
|
|
[0m[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 346 msecs[0m
|
|
[0m[DEBUG] scan_bus: bus Root Device finished in 363 msecs[0m
|
|
[0m[INFO ] done[0m
|
|
[0m[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 375 ms[0m
|
|
[0m[DEBUG] found VGA at PCI: 00:00:02.0[0m
|
|
[0m[DEBUG] Setting up VGA for PCI: 00:00:02.0[0m
|
|
[0m[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000[0m
|
|
[0m[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device[0m
|
|
[0m[INFO ] Allocating resources...[0m
|
|
[0m[INFO ] Reading resources...[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.[0m
|
|
[0m[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.[0m
|
|
[0m[DEBUG] MC MAP: TOM: 0x400000000[0m
|
|
[0m[DEBUG] MC MAP: TOUUD: 0x47be00000[0m
|
|
[0m[DEBUG] MC MAP: MESEG_BASE: 0x7ffff00000[0m
|
|
[0m[DEBUG] MC MAP: MESEG_LIMIT: 0xfffff[0m
|
|
[0m[DEBUG] MC MAP: REMAP_BASE: 0x400000000[0m
|
|
[0m[DEBUG] MC MAP: REMAP_LIMIT: 0x47bdfffff[0m
|
|
[0m[DEBUG] MC MAP: TOLUD: 0x84200000[0m
|
|
[0m[DEBUG] MC MAP: BGSM: 0x80000000[0m
|
|
[0m[DEBUG] MC MAP: BDSM: 0x80200000[0m
|
|
[0m[DEBUG] MC MAP: TSEGMB: 0x7f800000[0m
|
|
[0m[DEBUG] MC MAP: GGC: 0x211[0m
|
|
[0m[DEBUG] MC MAP: DPR: 0x7f800001[0m
|
|
[0m[INFO ] Available memory above 4GB: 14270M[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 EHCI BAR hook registered[0m
|
|
[0m[DEBUG] More than one caller of pci_ehci_read_resources from PCI: 00:00:1d.0[0m
|
|
[7m[ERROR] PNP: 00ff.1 missing read_resources[0m
|
|
[7m[ERROR] PNP: 00ff.2 missing read_resources[0m
|
|
[0m[INFO ] Done reading resources.[0m
|
|
[0m[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0xfff] mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done[0m
|
|
[0m[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00001600 limit 0000167f io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 000015e0 limit 000015ef io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)[0m
|
|
[0m[INFO ] DOMAIN: 00000000: Resource ranges:[0m
|
|
[0m[INFO ] * Base: 1000, Size: 5e0, Tag: 100[0m
|
|
[0m[INFO ] * Base: 15f0, Size: 10, Tag: 100[0m
|
|
[0m[INFO ] * Base: 1680, Size: e980, Tag: 100[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 18 * [0xffa0 - 0xffbf] limit: ffbf io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 20 * [0xff80 - 0xff9f] limit: ff9f io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 10 * [0xff78 - 0xff7f] limit: ff7f io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 18 * [0xff70 - 0xff77] limit: ff77 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 14 * [0xff6c - 0xff6f] limit: ff6f io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 1c * [0xff68 - 0xff6b] limit: ff6b io[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 48 base fed10000 limit fed17fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 68 base fed18000 limit fed18fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 40 base fed19000 limit fed19fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5420 base fed84000 limit fed84fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5408 base fed80000 limit fed83fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base fed90000 limit fed90fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed91000 limit fed91fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base 00000000 limit 0009ffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 000a0000 limit 000bffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 000c0000 limit 000fffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 00100000 limit 7f7fffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 7f800000 limit 7fffffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 80000000 limit 841fffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 47bdfffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 31fe base fec00000 limit ffffffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)[0m
|
|
[0m[INFO ] DOMAIN: 00000000: Resource ranges:[0m
|
|
[0m[INFO ] * Base: 84200000, Size: 6be00000, Tag: 200[0m
|
|
[0m[INFO ] * Base: 47be00000, Size: 7b84200000, Tag: 200[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 20 * [0xdfb00000 - 0xdfbfffff] limit: dfbfffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 10 * [0xdfae0000 - 0xdfafffff] limit: dfafffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 10 * [0xdfad0000 - 0xdfadffff] limit: dfadffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 10 * [0xdfac8000 - 0xdfacffff] limit: dfacffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 10 * [0xdfac4000 - 0xdfac7fff] limit: dfac7fff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 10 * [0xdfac0000 - 0xdfac3fff] limit: dfac3fff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 14 * [0xdfabf000 - 0xdfabffff] limit: dfabffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 24 * [0xdfabe000 - 0xdfabe7ff] limit: dfabe7ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 10 * [0xdfabd000 - 0xdfabd3ff] limit: dfabd3ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 10 * [0xdfabc000 - 0xdfabc3ff] limit: dfabc3ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 10 * [0xdfabb000 - 0xdfabb0ff] limit: dfabb0ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 10 * [0xdfaba000 - 0xdfaba00f] limit: dfaba00f mem[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff done[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 10 * [0xdfb00000 - 0xdfb00fff] limit: dfb00fff mem[0m
|
|
[0m[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 10 <- [0x00000000dfac4000 - 0x00000000dfac7fff] size 0x00004000 gran 0x0e mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 10 <- [0x00000000dfac8000 - 0x00000000dfacffff] size 0x00008000 gran 0x0f mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000dfad0000 - 0x00000000dfadffff] size 0x00010000 gran 0x10 mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000dfaba000 - 0x00000000dfaba00f] size 0x00000010 gran 0x04 mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 10 <- [0x00000000dfae0000 - 0x00000000dfafffff] size 0x00020000 gran 0x11 mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 14 <- [0x00000000dfabf000 - 0x00000000dfabffff] size 0x00001000 gran 0x0c mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 EHCI Debug Port hook triggered[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000dfabd000 - 0x00000000dfabd3ff] size 0x00000400 gran 0x0a mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 EHCI Debug Port relocated[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000dfac0000 - 0x00000000dfac3fff] size 0x00004000 gran 0x0e mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000dfb00000 - 0x00000000dfbfffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 10 <- [0x00000000dfb00000 - 0x00000000dfb00fff] size 0x00001000 gran 0x0c mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000dfabc000 - 0x00000000dfabc3ff] size 0x00000400 gran 0x0a mem[0m
|
|
[7m[ERROR] PNP: 00ff.1 missing set_resources[0m
|
|
[7m[ERROR] PNP: 00ff.2 missing set_resources[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff6c - 0x000000000000ff6f] size 0x00000004 gran 0x02 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff68 - 0x000000000000ff6b] size 0x00000004 gran 0x02 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000dfabe000 - 0x00000000dfabe7ff] size 0x00000800 gran 0x0b mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000dfabb000 - 0x00000000dfabb0ff] size 0x00000100 gran 0x08 mem64[0m
|
|
[0m[INFO ] Done setting resources.[0m
|
|
[0m[INFO ] Done allocating resources.[0m
|
|
[0m[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 993 ms[0m
|
|
[0m[INFO ] Enabling resources...[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 cmd <- 06[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 bridge ctrl <- 0013[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 cmd <- 00[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 cmd <- 03[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 cmd <- 02[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 cmd <- 02[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 cmd <- 102[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 cmd <- 02[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 cmd <- 103[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 cmd <- 106[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 cmd <- 102[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 cmd <- 06[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 cmd <- 00[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 cmd <- 106[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 cmd <- 107[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 cmd <- 103[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 cmd <- 103[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 cmd <- 02[0m
|
|
[0m[INFO ] done.[0m
|
|
[0m[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 159 ms[0m
|
|
[0m[INFO ] Initializing devices...[0m
|
|
[0m[DEBUG] CPU_CLUSTER: 0 init[0m
|
|
[0m[INFO ] LAPIC 0x0 in XAPIC mode.[0m
|
|
[0m[DEBUG] MTRR: Physical address space:[0m
|
|
[0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m
|
|
[0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m
|
|
[0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m
|
|
[0m[DEBUG] 0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0[0m
|
|
[0m[DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1[0m
|
|
[0m[DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0[0m
|
|
[0m[DEBUG] 0x0000000100000000 - 0x000000047bdfffff size 0x37be00000 type 6[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits[0m
|
|
[0m[DEBUG] MTRR: default type WB/UC MTRR counts: 4/5.[0m
|
|
[0m[DEBUG] MTRR: WB selected as default type.[0m
|
|
[0m[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0[0m
|
|
[0m[DEBUG] MTRR: 1 base 0x00000000c0000000 mask 0x0000007fe0000000 type 0[0m
|
|
[0m[DEBUG] MTRR: 2 base 0x00000000e0000000 mask 0x0000007ff0000000 type 1[0m
|
|
[0m[DEBUG] MTRR: 3 base 0x00000000f0000000 mask 0x0000007ff0000000 type 0[0m
|
|
[0m
|
|
[0m[DEBUG] MTRR check[0m
|
|
[0m[DEBUG] Fixed MTRRs : Enabled[0m
|
|
[0m[DEBUG] Variable MTRRs: Enabled[0m
|
|
[0m
|
|
[0m[DEBUG] Initializing VR config.[0m
|
|
[0m[DEBUG] CPU has 2 cores, 4 threads enabled.[0m
|
|
[0m[DEBUG] Setting up SMI for CPU[0m
|
|
[0m[INFO ] Will perform SMM setup.[0m
|
|
[0m[DEBUG] microcode: sig=0x306c3 pf=0x10 revision=0x28[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0xf800 in mcache @0x7f7dd02c[0m
|
|
[0m[INFO ] CPU: Intel(R) Core(TM) i5-4300M CPU @ 2.60GHz.[0m
|
|
[0m[INFO ] LAPIC 0x0 in XAPIC mode.[0m
|
|
[0m[DEBUG] CPU: APIC: 00 enabled[0m
|
|
[0m[DEBUG] CPU: APIC: 01 enabled[0m
|
|
[0m[DEBUG] CPU: APIC: 02 enabled[0m
|
|
[0m[DEBUG] CPU: APIC: 03 enabled[0m
|
|
[0m[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178[0m
|
|
[0m[DEBUG] Processing 16 relocs. Offset value of 0x00030000[0m
|
|
[0m[DEBUG] Attempting to start 3 APs[0m
|
|
[0m[DEBUG] Waiting for 10ms after sending INIT.[0m
|
|
[0m[DEBUG] Waiting for SIPI to complete...[0m
|
|
[0m[INFO ] LAPIC 0x1 in XAPIC mode.[0m
|
|
[0m[DEBUG] done.[0m
|
|
[0m[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000028[0m
|
|
[0m[DEBUG] Waiting for SIPI to complete...[0m
|
|
[0m[DEBUG] done.[0m
|
|
[0m[INFO ] LAPIC 0x3 in XAPIC mode.[0m
|
|
[0m[INFO ] LAPIC 0x2 in XAPIC mode.[0m
|
|
[0m[INFO ] AP: slot 3 apic_id 3, MCU rev: 0x00000028[0m
|
|
[0m[INFO ] AP: slot 2 apic_id 2, MCU rev: 0x00000028[0m
|
|
[0m[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0[0m
|
|
[0m[DEBUG] Processing 9 relocs. Offset value of 0x00038000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: stack_top = 0x7f801000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400[0m
|
|
[0m[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000[0m
|
|
[0m[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f6a002d[0m
|
|
[0m[DEBUG] Installing permanent SMM handler to 0x7f800000[0m
|
|
[0m[DEBUG] HANDLER [0x7fafb000-0x7faff46f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 0[0m
|
|
[0m[DEBUG] ss0 [0x7fafac00-0x7fafafff][0m
|
|
[0m[DEBUG] stub0 [0x7faf3000-0x7faf319f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 1[0m
|
|
[0m[DEBUG] ss1 [0x7fafa800-0x7fafabff][0m
|
|
[0m[DEBUG] stub1 [0x7faf2c00-0x7faf2d9f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 2[0m
|
|
[0m[DEBUG] ss2 [0x7fafa400-0x7fafa7ff][0m
|
|
[0m[DEBUG] stub2 [0x7faf2800-0x7faf299f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 3[0m
|
|
[0m[DEBUG] ss3 [0x7fafa000-0x7fafa3ff][0m
|
|
[0m[DEBUG] stub3 [0x7faf2400-0x7faf259f][0m
|
|
[0m
|
|
[0m[DEBUG] stacks [0x7f800000-0x7f800fff][0m
|
|
[0m[DEBUG] Loading module at 0x7fafb000 with entry 0x7fafbaba. filesize: 0x4318 memsize: 0x4470[0m
|
|
[0m[DEBUG] Processing 270 relocs. Offset value of 0x7fafb000[0m
|
|
[0m[DEBUG] FMAP: area SMMSTORE found @ 810000 (524288 bytes)[0m
|
|
[0m[DEBUG] flash size 0x2800000 bytes[0m
|
|
[0m[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000[0m
|
|
[7m[ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!![0m
|
|
[0m[DEBUG] smm store: 8 # blocks with size 0x10000[0m
|
|
[0m[DEBUG] Loading module at 0x7faf3000 with entry 0x7faf3000. filesize: 0x1a0 memsize: 0x1a0[0m
|
|
[0m[DEBUG] Processing 9 relocs. Offset value of 0x7faf3000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: stack_top = 0x7f801000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400[0m
|
|
[0m[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000[0m
|
|
[0m[DEBUG] SMM Module: placing smm entry code at 7faf2c00, cpu # 0x1[0m
|
|
[0m[DEBUG] SMM Module: placing smm entry code at 7faf2800, cpu # 0x2[0m
|
|
[0m[DEBUG] SMM Module: placing smm entry code at 7faf2400, cpu # 0x3[0m
|
|
[0m[DEBUG] SMM Module: stub loaded at 7faf3000. Will call 0x7fafbaba[0m
|
|
[0m[DEBUG] SMI_STS: MCSMI PM1 [0m
|
|
[0m[DEBUG] BM TMROF TCO_STS: INTRD_DET [0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeb000, cpu = 0[0m
|
|
[0m[DEBUG] In relocation handler: CPU 0[0m
|
|
[0m[DEBUG] New SMBASE=0x7faeb000 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeac00, cpu = 1[0m
|
|
[0m[DEBUG] In relocation handler: CPU 1[0m
|
|
[0m[DEBUG] New SMBASE=0x7faeac00 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea400, cpu = 3[0m
|
|
[0m[DEBUG] In relocation handler: CPU 3[0m
|
|
[0m[DEBUG] New SMBASE=0x7faea400 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea800, cpu = 2[0m
|
|
[0m[DEBUG] In relocation handler: CPU 2[0m
|
|
[0m[DEBUG] New SMBASE=0x7faea800 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] Initializing CPU #0[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] VMX status: enabled[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] Turbo is available but hidden[0m
|
|
[0m[INFO ] Turbo is available and visible[0m
|
|
[0m[INFO ] CPU #0 initialized[0m
|
|
[0m[INFO ] Initializing CPU #1[0m
|
|
[0m[INFO ] Initializing CPU #3[0m
|
|
[0m[INFO ] Initializing CPU #2[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] VMX status: enabled[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
|
|
[0m[DEBUG] VMX status: enabled[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] CPU #3 initialized[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] CPU #2 initialized[0m
|
|
[0m[DEBUG] VMX status: enabled[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] CPU #1 initialized[0m
|
|
[0m[INFO ] bsp_do_flight_plan done after 475 msecs.[0m
|
|
[0m[DEBUG] CPU: frequency set to 3300[0m
|
|
[0m[DEBUG] Enabling SMIs.[0m
|
|
[0m[DEBUG] Locking SMM.[0m
|
|
[0m[DEBUG] MTRR: TEMPORARY Physical address space:[0m
|
|
[0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m
|
|
[0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m
|
|
[0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m
|
|
[0m[DEBUG] 0x0000000080000000 - 0x00000000ff7fffff size 0x7f800000 type 0[0m
|
|
[0m[DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5[0m
|
|
[0m[DEBUG] 0x0000000100000000 - 0x000000047bdfffff size 0x37be00000 type 6[0m
|
|
[0m[DEBUG] MTRR: default type WB/UC MTRR counts: 9/5.[0m
|
|
[0m[DEBUG] MTRR: UC selected as default type.[0m
|
|
[0m[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6[0m
|
|
[0m[DEBUG] MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 5[0m
|
|
[0m[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6[0m
|
|
[0m[DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000007e00000000 type 6[0m
|
|
[0m[DEBUG] MTRR: 4 base 0x0000000400000000 mask 0x0000007f80000000 type 6[0m
|
|
[0m[DEBUG] CPU_CLUSTER: 0 init finished in 873 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 init[0m
|
|
[0m[DEBUG] Disabling PEG12.[0m
|
|
[0m[DEBUG] Disabling PEG10.[0m
|
|
[0m[DEBUG] Disabling "device 7".[0m
|
|
[0m[DEBUG] Set BIOS_RESET_CPL[0m
|
|
[0m[DEBUG] CPU TDP: 37 Watts[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 init finished in 16 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 init[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 init[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'vbt.bin' @0x4f480 size 0x582 in mcache @0x7f7dd1e4[0m
|
|
[0m[INFO ] Found a VBT of 4608 bytes[0m
|
|
[0m[INFO ] GMA: Found VBT in CBFS[0m
|
|
[0m[INFO ] GMA: Found valid VBT in CBFS[0m
|
|
[0m[DEBUG] GT Power Management Init[0m
|
|
[0m[INFO ] GMA: Setting backlight PWM frequency to 135MHz / 128 / 4794 = 220Hz[0m
|
|
[0m[INFO ] framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32[0m
|
|
[0m[INFO ] x_res x y_res: 1366 x 768, size: 4227072 at 0xe0000000[0m
|
|
[0m[DEBUG] GT Power Management Init (post VBIOS)[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 init finished in 368 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 init[0m
|
|
[0m[DEBUG] Mini-HD: base = 0xdfac4000[0m
|
|
[0m[DEBUG] azalia_audio: initializing codec #0...[0m
|
|
[0m[DEBUG] azalia_audio: - vendor/device id: 0x80862807[0m
|
|
[0m[DEBUG] azalia_audio: - verb size: 16[0m
|
|
[0m[DEBUG] azalia_audio: - verb loaded[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 init finished in 25 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 init[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 init[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 init[0m
|
|
[0m[DEBUG] ME: FW Partition Table : OK[0m
|
|
[0m[DEBUG] ME: Bringup Loader Failure : NO[0m
|
|
[0m[DEBUG] ME: Firmware Init Complete : NO[0m
|
|
[0m[DEBUG] ME: Manufacturing Mode : YES[0m
|
|
[0m[DEBUG] ME: Boot Options Present : NO[0m
|
|
[0m[DEBUG] ME: Update In Progress : NO[0m
|
|
[0m[DEBUG] ME: Current Working State : Initializing[0m
|
|
[0m[DEBUG] ME: Current Operation State : Bring up[0m
|
|
[0m[DEBUG] ME: Current Operation Mode : Debug[0m
|
|
[0m[DEBUG] ME: Error Code : No Error[0m
|
|
[0m[DEBUG] ME: Progress Phase : BUP Phase[0m
|
|
[0m[DEBUG] ME: Power Management Event : Clean Moff->Mx wake[0m
|
|
[0m[DEBUG] ME: Progress Phase State : 0x4d[0m
|
|
[1;7m[CRIT ] intel_me_path: mbp is not ready![0m
|
|
[1m[NOTE ] ME: BIOS path: Error[0m
|
|
[7m[ERROR] ME: MBP not ready[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 init finished in 73 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 init[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 init[0m
|
|
[0m[DEBUG] EHCI: Setting up controller.. done.[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 init[0m
|
|
[0m[DEBUG] Azalia: base = 0xdfac0000[0m
|
|
[0m[DEBUG] Azalia: codec_mask = 01[0m
|
|
[0m[DEBUG] azalia_audio: initializing codec #0...[0m
|
|
[0m[DEBUG] azalia_audio: - vendor/device id: 0x10ec0292[0m
|
|
[0m[DEBUG] azalia_audio: - verb size: 128[0m
|
|
[0m[DEBUG] azalia_audio: - verb loaded[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 init finished in 33 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 init[0m
|
|
[0m[DEBUG] Initializing PCH PCIe bridge.[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 init[0m
|
|
[0m[DEBUG] Initializing PCH PCIe bridge.[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 init finished in 3 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 init[0m
|
|
[0m[DEBUG] EHCI: Setting up controller.. done.[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 init[0m
|
|
[0m[DEBUG] pch: lpc_init[0m
|
|
[0m[DEBUG] IOAPIC: Initializing IOAPIC at fec00000[0m
|
|
[0m[DEBUG] IOAPIC: ID = 0x00[0m
|
|
[0m[DEBUG] IOAPIC: 24 interrupts[0m
|
|
[0m[DEBUG] IOAPIC: Clearing IOAPIC at fec00000[0m
|
|
[0m[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00[0m
|
|
[0m[INFO ] Set power on after power failure.[0m
|
|
[0m[INFO ] NMI sources enabled.[0m
|
|
[0m[DEBUG] LynxPoint H PM init[0m
|
|
[0m[DEBUG] RTC: failed = 0x0[0m
|
|
[0m[DEBUG] RTC Init[0m
|
|
[0m[DEBUG] apm_control: Disabling ACPI.[0m
|
|
[0m[DEBUG] APMC done.[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 init finished in 48 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 init[0m
|
|
[0m[DEBUG] SATA: Initializing...[0m
|
|
[0m[DEBUG] SATA: Controller in AHCI mode.[0m
|
|
[0m[DEBUG] ABAR: 0xdfabe000[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 init finished in 11 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 init[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 init[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PNP: 00ff.2 init[0m
|
|
[0m[DEBUG] PNP: 00ff.2 init finished in 0 msecs[0m
|
|
[0m[INFO ] Devices initialized[0m
|
|
[0m[DEBUG] BS: BS_DEV_INIT run times (exec / console): 549 / 1085 ms[0m
|
|
[0m[DEBUG] TPM: Startup[0m
|
|
[0m[DEBUG] TPM: command 0x99 returned 0x0[0m
|
|
[0m[DEBUG] TPM: Asserting physical presence[0m
|
|
[0m[DEBUG] TPM: command 0x4000000a returned 0x0[0m
|
|
[0m[DEBUG] TPM: command 0x65 returned 0x0[0m
|
|
[0m[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1[0m
|
|
[0m[INFO ] TPM: setup succeeded[0m
|
|
[0m[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 54 / 26 ms[0m
|
|
[0m[INFO ] Finalize devices...[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 final[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 final[0m
|
|
[0m[INFO ] ME: MBP cleared[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 final[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 final[0m
|
|
[0m[DEBUG] apm_control: Finalizing SMM.[0m
|
|
[0m[DEBUG] APMC done.[0m
|
|
[0m[INFO ] Devices finalized[0m
|
|
[0m[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 1 / 29 ms[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x4bc00 size 0x3820 in mcache @0x7f7dd1b8[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[1;4m[WARN ] CBFS: 'fallback/slic' not found.[0m
|
|
[0m[INFO ] ACPI: Writing ACPI tables at 7f62d000.[0m
|
|
[0m[DEBUG] ACPI: * FACS[0m
|
|
[0m[DEBUG] ACPI: * FACP[0m
|
|
[0m[DEBUG] ACPI: added table 1/32, length now 44[0m
|
|
[0m[DEBUG] Found 1 CPU(s) with 4 core(s) each.[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] Generating ACPI PIRQ entries[0m
|
|
[0m[INFO ] ACPI: * H8[0m
|
|
[0m[INFO ] H8: BDC detection not implemented. Assuming BDC installed[0m
|
|
[0m[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed[0m
|
|
[0m[DEBUG] PPI: Pending OS request: 0xff3410cf (0xb8e7488c)[0m
|
|
[0m[DEBUG] PPI: OS response: CMD 0x561cf211 = 0xce6cccda[0m
|
|
[0m[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0[0m
|
|
[0m[DEBUG] ACPI: * SSDT[0m
|
|
[0m[DEBUG] ACPI: added table 2/32, length now 52[0m
|
|
[0m[DEBUG] ACPI: * MCFG[0m
|
|
[0m[DEBUG] ACPI: added table 3/32, length now 60[0m
|
|
[0m[DEBUG] TCPA log created at 0x7f61d000[0m
|
|
[0m[DEBUG] ACPI: * TCPA[0m
|
|
[0m[DEBUG] ACPI: added table 4/32, length now 68[0m
|
|
[0m[DEBUG] IOAPIC: 24 interrupts[0m
|
|
[0m[DEBUG] ACPI: * APIC[0m
|
|
[0m[DEBUG] ACPI: added table 5/32, length now 76[0m
|
|
[0m[DEBUG] current = 7f632610[0m
|
|
[0m[DEBUG] ACPI: * DMAR[0m
|
|
[0m[DEBUG] ACPI: added table 6/32, length now 84[0m
|
|
[0m[DEBUG] ACPI: * HPET[0m
|
|
[0m[DEBUG] ACPI: added table 7/32, length now 92[0m
|
|
[0m[DEBUG] current = 7f632710[0m
|
|
[0m[INFO ] ACPI: done.[0m
|
|
[0m[DEBUG] ACPI tables: 22288 bytes.[0m
|
|
[0m[DEBUG] smbios_write_tables: 7f615000[0m
|
|
[0m[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.12'[0m
|
|
[0m[INFO ] Create SMBIOS type 16[0m
|
|
[0m[INFO ] Create SMBIOS type 17[0m
|
|
[0m[INFO ] Create SMBIOS type 20[0m
|
|
[0m[DEBUG] SMBIOS tables: 909 bytes.[0m
|
|
[0m[DEBUG] Writing table forward entry at 0x00000500[0m
|
|
[0m[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7079[0m
|
|
[0m[DEBUG] Writing coreboot table at 0x7f651000[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'cmos_layout.bin' @0x4fb80 size 0x510 in mcache @0x7f7dd23c[0m
|
|
[0m[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 1. 0000000000001000-000000000009ffff: RAM[0m
|
|
[0m[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED[0m
|
|
[0m[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED[0m
|
|
[0m[DEBUG] 5. 0000000000100000-000000007f614fff: RAM[0m
|
|
[0m[DEBUG] 6. 000000007f615000-000000007f67dfff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 7. 000000007f67e000-000000007f7cbfff: RAMSTAGE[0m
|
|
[0m[DEBUG] 8. 000000007f7cc000-000000007f7fffff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 9. 000000007f800000-00000000841fffff: RESERVED[0m
|
|
[0m[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED[0m
|
|
[0m[DEBUG] 11. 00000000fed10000-00000000fed19fff: RESERVED[0m
|
|
[0m[DEBUG] 12. 00000000fed40000-00000000fed44fff: RESERVED[0m
|
|
[0m[DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED[0m
|
|
[0m[DEBUG] 14. 00000000fed90000-00000000fed91fff: RESERVED[0m
|
|
[0m[DEBUG] 15. 0000000100000000-000000047bdfffff: RAM[0m
|
|
[0m[DEBUG] FMAP: area SMMSTORE found @ 810000 (524288 bytes)[0m
|
|
[0m[DEBUG] smm store: 8 # blocks with size 0x10000[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] Wrote coreboot table at: 0x7f651000, 0x9c8 bytes, checksum c996[0m
|
|
[0m[DEBUG] coreboot table: 2528 bytes.[0m
|
|
[0m[DEBUG] IMD ROOT 0. 0x7f7ff000 0x00001000[0m
|
|
[0m[DEBUG] IMD SMALL 1. 0x7f7fe000 0x00001000[0m
|
|
[0m[DEBUG] CONSOLE 2. 0x7f7de000 0x00020000[0m
|
|
[0m[DEBUG] RO MCACHE 3. 0x7f7dd000 0x00000318[0m
|
|
[0m[DEBUG] TIME STAMP 4. 0x7f7dc000 0x00000910[0m
|
|
[0m[DEBUG] MEM INFO 5. 0x7f7da000 0x000010c8[0m
|
|
[0m[DEBUG] AFTER CAR 6. 0x7f7cc000 0x0000e000[0m
|
|
[0m[DEBUG] RAMSTAGE 7. 0x7f67d000 0x0014f000[0m
|
|
[0m[DEBUG] SMM BACKUP 8. 0x7f66d000 0x00010000[0m
|
|
[0m[DEBUG] SMM COMBUFFER 9. 0x7f65d000 0x00010000[0m
|
|
[0m[DEBUG] IGD OPREGION10. 0x7f659000 0x00003200[0m
|
|
[0m[DEBUG] COREBOOT 11. 0x7f651000 0x00008000[0m
|
|
[0m[DEBUG] ACPI 12. 0x7f62d000 0x00024000[0m
|
|
[0m[DEBUG] TCPA TCGLOG13. 0x7f61d000 0x00010000[0m
|
|
[0m[DEBUG] SMBIOS 14. 0x7f615000 0x00008000[0m
|
|
[0m[DEBUG] IMD small region:[0m
|
|
[0m[DEBUG] IMD ROOT 0. 0x7f7fec00 0x00000400[0m
|
|
[0m[DEBUG] USBDEBUG 1. 0x7f7feba0 0x00000050[0m
|
|
[0m[DEBUG] FMAP 2. 0x7f7fea80 0x0000010a[0m
|
|
[0m[DEBUG] ROMSTAGE 3. 0x7f7fea60 0x00000004[0m
|
|
[0m[DEBUG] ROMSTG STCK 4. 0x7f7fe9a0 0x000000a8[0m
|
|
[0m[DEBUG] ACPI GNVS 5. 0x7f7fe8e0 0x000000b0[0m
|
|
[0m[DEBUG] TPM PPI 6. 0x7f7fe780 0x0000015a[0m
|
|
[0m[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 1 / 573 ms[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/payload' @0x56780 size 0x169919 in mcache @0x7f7dd2a8[0m
|
|
[0m[DEBUG] Checking segment from ROM address 0xffce77ac[0m
|
|
[0m[DEBUG] Checking segment from ROM address 0xffce77c8[0m
|
|
[0m[DEBUG] Loading segment from ROM address 0xffce77ac[0m
|
|
[0m[DEBUG] code (compression=1)[0m
|
|
[0m[DEBUG] New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffce77e4 filesize 0x1698e1[0m
|
|
[0m[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000001698e1[0m
|
|
[0m[DEBUG] using LZMA[0m
|
|
[0m[DEBUG] Loading segment from ROM address 0xffce77c8[0m
|
|
[0m[DEBUG] Entry Point 0x00802677[0m
|
|
[0m[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 132 / 61 ms[0m
|
|
[0m[DEBUG] ICH-NM10-PCH: watchdog disabled[0m
|
|
[0m[DEBUG] Jumping to boot code at 0x00802677(0x7f651000)[0m
|
|
-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:01:03 --
|
|
-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:02:27 --
|
|
USB
|
|
[0m
|
|
[0m
|
|
[1m[NOTE ] coreboot-25.12 Thu Dec 18 17:36:57 UTC 2025 x86_32 bootblock starting (log level: 7)...[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x890000.[0m
|
|
[0m[DEBUG] FMAP: base = 0x0 size = 0xc00000 #areas = 5[0m
|
|
[0m[DEBUG] FMAP: area COREBOOT found @ 891000 (3600384 bytes)[0m
|
|
[0m[INFO ] Booting from COREBOOT region[0m
|
|
[0m[INFO ] CBFS: mcache @0xff7e0e00 built for 15 files, used 0x318 of 0x4000 bytes[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/romstage' @0xf980 size 0x1ba48 in mcache @0xff7e0e8c[0m
|
|
[0m[DEBUG] BS: bootblock times (exec / console): total (unknown) / 54 ms[0m
|
|
[0m
|
|
[0m
|
|
[1m[NOTE ] coreboot-25.12 Thu Dec 18 17:36:57 UTC 2025 x86_32 romstage starting (log level: 7)...[0m
|
|
[0m[DEBUG] Disabling Watchdog reboot... done.[0m
|
|
[0m[DEBUG] SMBus controller enabled[0m
|
|
[0m[DEBUG] Setting up static northbridge registers... done.[0m
|
|
[0m[DEBUG] Started PEG11 link training.[0m
|
|
[0m[DEBUG] Started PEG10 link training.[0m
|
|
[0m[DEBUG] Initializing IGD...[0m
|
|
[0m[DEBUG] Back from haswell_early_initialization()[0m
|
|
[0m[DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i5-4300M CPU @ 2.60GHz[0m
|
|
[0m[DEBUG] AES supported, TXT supported, VT supported[0m
|
|
[0m[DEBUG] PCH type: QM87, device id: 8c4f, rev id 5[0m
|
|
[0m[DEBUG] Starting native platform initialisation[0m
|
|
[0m[INFO ] Intel ME early init[0m
|
|
[0m[INFO ] Intel ME firmware is ready[0m
|
|
[0m[DEBUG] HSIO lane owner: 0x05[0m
|
|
[0m[DEBUG] SATA port enables: 0x3f[0m
|
|
[0m[DEBUG] warm_reset_usb3_ports: took 8 usecs[0m
|
|
[0m[DEBUG] USB2 port 0 => mapped to OC pin 0[0m
|
|
[0m[DEBUG] USB2 port 1 => mapped to OC pin 0[0m
|
|
[0m[DEBUG] USB2 port 2 => mapped to OC pin 1[0m
|
|
[0m[DEBUG] USB2 port 3 => not mapped to OC pin[0m
|
|
[0m[DEBUG] USB2 port 4 => not mapped to OC pin[0m
|
|
[0m[DEBUG] USB2 port 5 => mapped to OC pin 2[0m
|
|
[0m[DEBUG] USB2 port 6 => mapped to OC pin 3[0m
|
|
[0m[DEBUG] USB2 port 7 => mapped to OC pin 3[0m
|
|
[0m[DEBUG] USB2 port 8 => mapped to OC pin 4[0m
|
|
[0m[DEBUG] USB2 port 9 => mapped to OC pin 4[0m
|
|
[0m[DEBUG] USB2 port 10 => mapped to OC pin 5[0m
|
|
[0m[DEBUG] USB2 port 11 => mapped to OC pin 5[0m
|
|
[0m[DEBUG] USB2 port 12 => mapped to OC pin 6[0m
|
|
[0m[DEBUG] USB2 port 13 => mapped to OC pin 6[0m
|
|
[0m
|
|
[0m[DEBUG] USB3 port 0 => mapped to OC pin 0[0m
|
|
[0m[DEBUG] USB3 port 1 => mapped to OC pin 0[0m
|
|
[0m[DEBUG] USB3 port 2 => not mapped to OC pin[0m
|
|
[0m[DEBUG] USB3 port 3 => not mapped to OC pin[0m
|
|
[0m[DEBUG] USB3 port 4 => mapped to OC pin 1[0m
|
|
[0m[DEBUG] USB3 port 5 => mapped to OC pin 1[0m
|
|
[0m
|
|
[0m[DEBUG] Retraining DMI at Gen2 speeds...[0m
|
|
[0m[DEBUG] DMI: Running at Gen1 x4[0m
|
|
[0m[DEBUG] DMI: Running at Gen1 x4[0m
|
|
[0m[INFO ] DMI: Running at Gen2 x4[0m
|
|
[0m[DEBUG] Programming SA DMI VC/TC mappings...[0m
|
|
[0m[DEBUG] Programming PCH DMI VC/TC mappings...[0m
|
|
[0m[DEBUG] Waiting for PCH DMI VC negotiation... done![0m
|
|
[0m[DEBUG] Waiting for SA DMI VC negotiation... done![0m
|
|
[0m[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)[0m
|
|
[0m[INFO ] Using cached memory parameters[0m
|
|
[0m[DEBUG] Initial bootmode: BOOTMODE_WARM[0m
|
|
[0m[DEBUG] Current bootmode: BOOTMODE_WARM[0m
|
|
[0m
|
|
[0m[DEBUG] Starting native raminit[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task PROCSPD[0m
|
|
[0m[DEBUG] CH0S0 is slotted and DDR3[0m
|
|
[0m[DEBUG] CH1S0 is slotted and not DDR3, ignoring[0m
|
|
[0m
|
|
[0m[DEBUG] CH0S0 SPD:[0m
|
|
[0m[DEBUG] Revision : 13[0m
|
|
[0m[DEBUG] Type : b[0m
|
|
[0m[DEBUG] Key : 3[0m
|
|
[0m[DEBUG] Banks : 8[0m
|
|
[0m[DEBUG] Capacity : 8 Gb[0m
|
|
[0m[DEBUG] Supported voltages : 1.35V 1.5V[0m
|
|
[0m[DEBUG] SDRAM width : 8[0m
|
|
[0m[DEBUG] Bus extension : 0 bits[0m
|
|
[0m[DEBUG] Bus width : 64[0m
|
|
[0m[DEBUG] FTB timings : yes[0m
|
|
[0m[DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6[0m
|
|
[0m[DEBUG] Thermal features : ASR ext_temp_range[0m
|
|
[0m[DEBUG] Thermal sensor : no[0m
|
|
[0m[DEBUG] Standard SDRAM : yes[0m
|
|
[0m[DEBUG] Rank1 Address bits : normal[0m
|
|
[0m[DEBUG] DIMM Reference card: F[0m
|
|
[0m[DEBUG] Manufacturer ID : 2c80[0m
|
|
[0m[DEBUG] Part number : 16KTF2G64HZ-1G6A[0m
|
|
[0m[INFO ] Row addr bits : 16[0m
|
|
[0m[INFO ] Column addr bits : 11[0m
|
|
[0m[INFO ] Number of ranks : 2[0m
|
|
[0m[INFO ] DIMM Capacity : 16384 MB[0m
|
|
[0m[INFO ] Vdd Min : 1300 mV[0m
|
|
[0m[INFO ] Vdd Max : 1500 mV[0m
|
|
[0m[INFO ] CAS latencies : 5 6 7 8 9 10 11[0m
|
|
[0m[INFO ] tCKmin : 1.250 ns[0m
|
|
[0m[INFO ] tAAmin : 13.125 ns[0m
|
|
[0m[INFO ] tWRmin : 15.000 ns[0m
|
|
[0m[INFO ] tRCDmin : 13.125 ns[0m
|
|
[0m[INFO ] tRRDmin : 7.500 ns[0m
|
|
[0m[INFO ] tRPmin : 13.125 ns[0m
|
|
[0m[INFO ] tRASmin : 35.000 ns[0m
|
|
[0m[INFO ] tRCmin : 48.125 ns[0m
|
|
[0m[INFO ] tRFCmin : 350.000 ns[0m
|
|
[0m[INFO ] tWTRmin : 7.500 ns[0m
|
|
[0m[INFO ] tRTPmin : 7.500 ns[0m
|
|
[0m[INFO ] tFAWmin : 40.000 ns[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task RST_NONT[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task INITMPLL[0m
|
|
[0m[DEBUG] MC_BIOS_REQ = 0x80000006[0m
|
|
[0m[DEBUG] MPLL busy... done in 14 us[0m
|
|
[0m[DEBUG] MC_BIOS_DATA = 0x00000006[0m
|
|
[0m[DEBUG] MPLL frequency is set to: 800 MHz (period: 1250000 femtoseconds)[0m
|
|
[0m[DEBUG] Quadrature clock period: 625 picoseconds[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task CONFMC[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task MEMMAP[0m
|
|
[0m[DEBUG] ME: Requested 0MB UMA[0m
|
|
[0m[DEBUG] ============ MEMORY MAP ============[0m
|
|
[0m
|
|
[0m[DEBUG] dpr_size = 0 MiB[0m
|
|
[0m[DEBUG] tseg_size = 8 MiB[0m
|
|
[0m[DEBUG] gtt_size = 2 MiB[0m
|
|
[0m[DEBUG] gms_size = 64 MiB[0m
|
|
[0m[DEBUG] me_stolen_size = 0 MiB[0m
|
|
[0m
|
|
[0m[DEBUG] touud = 18366 MiB[0m
|
|
[0m[DEBUG] remaplimit = 18365 MiB[0m
|
|
[0m[DEBUG] remapbase = 16384 MiB[0m
|
|
[0m[DEBUG] tom = 16384 MiB[0m
|
|
[0m[DEBUG] tom_minus_me = 16384 MiB[0m
|
|
[0m[DEBUG] tolud = 2114 MiB[0m
|
|
[0m[DEBUG] bdsm_base = 2050 MiB[0m
|
|
[0m[DEBUG] gtt_base = 2048 MiB[0m
|
|
[0m[DEBUG] tseg_base = 2040 MiB[0m
|
|
[0m
|
|
[0m[DEBUG] reclaim_possible = Yes[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task JEDECINIT[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task PRETRAIN[0m
|
|
[0m[DEBUG] C0S0:[0m
|
|
[0m[DEBUG] MR0: 0x0d70[0m
|
|
[0m[DEBUG] MR1: 0x0002[0m
|
|
[0m[DEBUG] MR2: 0x0258[0m
|
|
[0m[DEBUG] MR3: 0x0000[0m
|
|
[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task RST_TRAIN[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task EXIT_SR[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task NORMALMODE[0m
|
|
[0m
|
|
[0m
|
|
[0m[DEBUG] Executing raminit task RAMINITEND[0m
|
|
[0m[DEBUG] Waiting for mc_init_done acknowledgement... DONE![0m
|
|
[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | Task | msecs |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | PROCSPD | 194 |[0m
|
|
[0m[DEBUG] | RST_NONT | 0 |[0m
|
|
[0m[DEBUG] | INITMPLL | 24 |[0m
|
|
[0m[DEBUG] | CONFMC | 0 |[0m
|
|
[0m[DEBUG] | MEMMAP | 66 |[0m
|
|
[0m[DEBUG] | JEDECINIT | 0 |[0m
|
|
[0m[DEBUG] | PRETRAIN | 14 |[0m
|
|
[0m[DEBUG] | RST_TRAIN | 0 |[0m
|
|
[0m[DEBUG] | EXIT_SR | 0 |[0m
|
|
[0m[DEBUG] | NORMALMODE | 0 |[0m
|
|
[0m[DEBUG] | RAMINITEND | 5 |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] | Total | 306 |[0m
|
|
[0m[DEBUG] +------------------+------------+[0m
|
|
[0m[DEBUG] memcfg DDR3 clock 1600 MHz[0m
|
|
[0m[DEBUG] memcfg channel assignment: A: 0, B 1, C 2[0m
|
|
[0m[DEBUG] memcfg channel[0] config (00620040):[0m
|
|
[0m[DEBUG] ECC inactive[0m
|
|
[0m[DEBUG] enhanced interleave mode on[0m
|
|
[0m[DEBUG] rank interleave on[0m
|
|
[0m[DEBUG] DIMMA 16384 MB width x8 or x32 dual rank, selected[0m
|
|
[0m[DEBUG] DIMMB 0 MB width x8 or x32 single rank[0m
|
|
[0m[DEBUG] memcfg channel[1] config (00600000):[0m
|
|
[0m[DEBUG] ECC inactive[0m
|
|
[0m[DEBUG] enhanced interleave mode on[0m
|
|
[0m[DEBUG] rank interleave on[0m
|
|
[0m[DEBUG] DIMMA 0 MB width x8 or x32 single rank, selected[0m
|
|
[0m[DEBUG] DIMMB 0 MB width x8 or x32 single rank[0m
|
|
[0m[DEBUG] ME: Requested 0MB UMA[0m
|
|
[0m[DEBUG] ME: FW Partition Table : OK[0m
|
|
[0m[DEBUG] ME: Bringup Loader Failure : NO[0m
|
|
[0m[DEBUG] ME: Firmware Init Complete : NO[0m
|
|
[0m[DEBUG] ME: Manufacturing Mode : YES[0m
|
|
[0m[DEBUG] ME: Boot Options Present : NO[0m
|
|
[0m[DEBUG] ME: Update In Progress : NO[0m
|
|
[0m[DEBUG] ME: Current Working State : Initializing[0m
|
|
[0m[DEBUG] ME: Current Operation State : Bring up[0m
|
|
[0m[DEBUG] ME: Current Operation Mode : Debug[0m
|
|
[0m[DEBUG] ME: Error Code : No Error[0m
|
|
[0m[DEBUG] ME: Progress Phase : BUP Phase[0m
|
|
[0m[DEBUG] ME: Power Management Event : Pseudo-global reset[0m
|
|
[0m[DEBUG] ME: Progress Phase State : 0x4d[0m
|
|
[0m[DEBUG] CBMEM:[0m
|
|
[0m[DEBUG] IMD: root @ 0x7f7ff000 254 entries.[0m
|
|
[0m[DEBUG] IMD: root @ 0x7f7fec00 62 entries.[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] External stage cache:[0m
|
|
[0m[DEBUG] IMD: root @ 0x7fbff000 254 entries.[0m
|
|
[0m[DEBUG] IMD: root @ 0x7fbfec00 62 entries.[0m
|
|
[0m[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)[0m
|
|
[0m[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.[0m
|
|
[0m[DEBUG] flash size 0x2800000 bytes[0m
|
|
[0m[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000[0m
|
|
[7m[ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!![0m
|
|
[0m[DEBUG] MRC: 'RW_MRC_CACHE' does not need update.[0m
|
|
[0m[DEBUG] SMM Memory Map[0m
|
|
[0m[DEBUG] SMRAM : 0x7f800000 0x800000[0m
|
|
[0m[DEBUG] Subregion 0: 0x7f800000 0x300000[0m
|
|
[0m[DEBUG] Subregion 1: 0x7fb00000 0x100000[0m
|
|
[0m[DEBUG] Subregion 2: 0x7fc00000 0x400000[0m
|
|
[0m[DEBUG] Normal boot[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/postcar' @0x500c0 size 0x6678 in mcache @0xff7e1064[0m
|
|
[0m[DEBUG] Loading module at 0x7f7cd000 with entry 0x7f7cd031. filesize: 0x6248 memsize: 0xc5f8[0m
|
|
[0m[DEBUG] Processing 252 relocs. Offset value of 0x7d7cd000[0m
|
|
[0m[DEBUG] BS: romstage times (exec / console): total (unknown) / 877 ms[0m
|
|
[0m[DEBUG] usbdebug: postcar starting...[0m
|
|
[0m[DEBUG] Normal boot[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/ramstage' @0x2b440 size 0x1f537 in mcache @0x7f7dd0ec[0m
|
|
[0m[DEBUG] Loading module at 0x7f67e000 with entry 0x7f67e000. filesize: 0x3e0a0 memsize: 0x14d390[0m
|
|
[0m[DEBUG] Processing 4269 relocs. Offset value of 0x7b67e000[0m
|
|
[0m[DEBUG] BS: postcar times (exec / console): total (unknown) / 32 ms[0m
|
|
[0m[DEBUG] usbdebug: ramstage starting...[0m
|
|
[0m[DEBUG] Normal boot[0m
|
|
[0m[INFO ] Enumerating buses...[0m
|
|
[0m[DEBUG] Root Device scanning...[0m
|
|
[0m[DEBUG] CPU_CLUSTER: 0 enabled[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 enabled[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 [8086/0c04] enabled[0m
|
|
[0m[INFO ] PCI: Static device PCI: 00:00:01.0 not found, disabling it.[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 [8086/0c05] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 [8086/0416] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 [8086/0c0c] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 [8086/0c03] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 [8086/8c31] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 [8086/8c3a] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:16.1: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:16.2: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:16.3: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 [8086/153a] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 [8086/8c2d] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 [8086/8c20] enabled[0m
|
|
[0m[DEBUG] PCIe Root Port 1 ASPM is disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 [8086/8c10] enabled[0m
|
|
[0m[DEBUG] PCIe Root Port 2 ASPM is disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 [8086/8c12] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.2 [8086/8c14] disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.3 [8086/8c16] disabled[0m
|
|
[0m[DEBUG] Adjusted number of PCIe root ports to 5 as per strpfusecfg2[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.2: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.3: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.4: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.4 [8086/8c18] disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 [8086/8c26] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 [8086/8c4f] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 [8086/8c01] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 [8086/8c22] enabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.5: Disabling device[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.5 [8086/8c09] disabled[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.6: Disabling device[0m
|
|
[1;4m[WARN ] PCI: Leftover static devices:[0m
|
|
[1;4m[WARN ] PCI: 00:00:01.0[0m
|
|
[1;4m[WARN ] PCI: 00:00:16.1[0m
|
|
[1;4m[WARN ] PCI: 00:00:16.2[0m
|
|
[1;4m[WARN ] PCI: 00:00:16.3[0m
|
|
[1;4m[WARN ] PCI: 00:00:1c.5[0m
|
|
[1;4m[WARN ] PCI: 00:00:1c.6[0m
|
|
[1;4m[WARN ] PCI: 00:00:1c.7[0m
|
|
[1;4m[WARN ] PCI: 00:00:1f.6[0m
|
|
[1;4m[WARN ] PCI: Check your devicetree.cb.[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01[0m
|
|
[0m[INFO ] PCI: 00:00:01.1: Setting Max_Payload_Size to 128 for devices under this root port[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:01.1 finished in 14 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 [10ec/5227] enabled[0m
|
|
[0m[INFO ] Enabling Common Clock Configuration[0m
|
|
[0m[INFO ] ASPM: Enabled L0s and L1[0m
|
|
[0m[INFO ] PCI: 00:02:00.0: Enabled LTR[0m
|
|
[0m[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 31 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 scanning...[0m
|
|
[0m[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03[0m
|
|
[0m[INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 14 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 scanning...[0m
|
|
[0m[DEBUG] No CMOS option 'touchpad'.[0m
|
|
[0m[INFO ] PMH7: ID 05 Revision 01[0m
|
|
[0m[DEBUG] PNP: 00ff.1 enabled[0m
|
|
[0m[INFO ] H8: EC Firmware ID GLHT30WW-3.23, Version 3.01B[0m
|
|
[0m[DEBUG] No CMOS option 'bluetooth'.[0m
|
|
[0m[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed[0m
|
|
[0m[DEBUG] No CMOS option 'wwan'.[0m
|
|
[0m[DEBUG] PNP: 00ff.2 enabled[0m
|
|
[0m[INFO ] Found TPM 1.2 ST33ZP24 (0x0000) by ST Microelectronics (0x104a)[0m
|
|
[0m[DEBUG] PNP: 0c31.0 enabled[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 45 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 scanning...[0m
|
|
[0m[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs[0m
|
|
[0m[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 346 msecs[0m
|
|
[0m[DEBUG] scan_bus: bus Root Device finished in 363 msecs[0m
|
|
[0m[INFO ] done[0m
|
|
[0m[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 375 ms[0m
|
|
[0m[DEBUG] found VGA at PCI: 00:00:02.0[0m
|
|
[0m[DEBUG] Setting up VGA for PCI: 00:00:02.0[0m
|
|
[0m[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000[0m
|
|
[0m[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device[0m
|
|
[0m[INFO ] Allocating resources...[0m
|
|
[0m[INFO ] Reading resources...[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.[0m
|
|
[0m[DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.[0m
|
|
[0m[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.[0m
|
|
[0m[DEBUG] MC MAP: TOM: 0x400000000[0m
|
|
[0m[DEBUG] MC MAP: TOUUD: 0x47be00000[0m
|
|
[0m[DEBUG] MC MAP: MESEG_BASE: 0x7ffff00000[0m
|
|
[0m[DEBUG] MC MAP: MESEG_LIMIT: 0xfffff[0m
|
|
[0m[DEBUG] MC MAP: REMAP_BASE: 0x400000000[0m
|
|
[0m[DEBUG] MC MAP: REMAP_LIMIT: 0x47bdfffff[0m
|
|
[0m[DEBUG] MC MAP: TOLUD: 0x84200000[0m
|
|
[0m[DEBUG] MC MAP: BGSM: 0x80000000[0m
|
|
[0m[DEBUG] MC MAP: BDSM: 0x80200000[0m
|
|
[0m[DEBUG] MC MAP: TSEGMB: 0x7f800000[0m
|
|
[0m[DEBUG] MC MAP: GGC: 0x211[0m
|
|
[0m[DEBUG] MC MAP: DPR: 0x7f800001[0m
|
|
[0m[INFO ] Available memory above 4GB: 14270M[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 EHCI BAR hook registered[0m
|
|
[0m[DEBUG] More than one caller of pci_ehci_read_resources from PCI: 00:00:1d.0[0m
|
|
[7m[ERROR] PNP: 00ff.1 missing read_resources[0m
|
|
[7m[ERROR] PNP: 00ff.2 missing read_resources[0m
|
|
[0m[INFO ] Done reading resources.[0m
|
|
[0m[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0xfff] mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done[0m
|
|
[0m[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00001600 limit 0000167f io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 000015e0 limit 000015ef io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)[0m
|
|
[0m[INFO ] DOMAIN: 00000000: Resource ranges:[0m
|
|
[0m[INFO ] * Base: 1000, Size: 5e0, Tag: 100[0m
|
|
[0m[INFO ] * Base: 15f0, Size: 10, Tag: 100[0m
|
|
[0m[INFO ] * Base: 1680, Size: e980, Tag: 100[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 18 * [0xffa0 - 0xffbf] limit: ffbf io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 20 * [0xff80 - 0xff9f] limit: ff9f io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 10 * [0xff78 - 0xff7f] limit: ff7f io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 18 * [0xff70 - 0xff77] limit: ff77 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 14 * [0xff6c - 0xff6f] limit: ff6f io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 1c * [0xff68 - 0xff6b] limit: ff6b io[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 48 base fed10000 limit fed17fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 68 base fed18000 limit fed18fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 40 base fed19000 limit fed19fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5420 base fed84000 limit fed84fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5408 base fed80000 limit fed83fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base fed90000 limit fed90fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed91000 limit fed91fff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base 00000000 limit 0009ffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 000a0000 limit 000bffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 000c0000 limit 000fffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 00100000 limit 7f7fffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 7f800000 limit 7fffffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 80000000 limit 841fffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 47bdfffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 31fe base fec00000 limit ffffffff mem (fixed)[0m
|
|
[0m[DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)[0m
|
|
[0m[INFO ] DOMAIN: 00000000: Resource ranges:[0m
|
|
[0m[INFO ] * Base: 84200000, Size: 6be00000, Tag: 200[0m
|
|
[0m[INFO ] * Base: 47be00000, Size: 7b84200000, Tag: 200[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 20 * [0xdfb00000 - 0xdfbfffff] limit: dfbfffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 10 * [0xdfae0000 - 0xdfafffff] limit: dfafffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 10 * [0xdfad0000 - 0xdfadffff] limit: dfadffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 10 * [0xdfac8000 - 0xdfacffff] limit: dfacffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 10 * [0xdfac4000 - 0xdfac7fff] limit: dfac7fff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 10 * [0xdfac0000 - 0xdfac3fff] limit: dfac3fff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 14 * [0xdfabf000 - 0xdfabffff] limit: dfabffff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 24 * [0xdfabe000 - 0xdfabe7ff] limit: dfabe7ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 10 * [0xdfabd000 - 0xdfabd3ff] limit: dfabd3ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 10 * [0xdfabc000 - 0xdfabc3ff] limit: dfabc3ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 10 * [0xdfabb000 - 0xdfabb0ff] limit: dfabb0ff mem[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 10 * [0xdfaba000 - 0xdfaba00f] limit: dfaba00f mem[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff done[0m
|
|
[0m[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 10 * [0xdfb00000 - 0xdfb00fff] limit: dfb00fff mem[0m
|
|
[0m[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 10 <- [0x00000000dfac4000 - 0x00000000dfac7fff] size 0x00004000 gran 0x0e mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 10 <- [0x00000000dfac8000 - 0x00000000dfacffff] size 0x00008000 gran 0x0f mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000dfad0000 - 0x00000000dfadffff] size 0x00010000 gran 0x10 mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000dfaba000 - 0x00000000dfaba00f] size 0x00000010 gran 0x04 mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 10 <- [0x00000000dfae0000 - 0x00000000dfafffff] size 0x00020000 gran 0x11 mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 14 <- [0x00000000dfabf000 - 0x00000000dfabffff] size 0x00001000 gran 0x0c mem[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 EHCI Debug Port hook triggered[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000dfabd000 - 0x00000000dfabd3ff] size 0x00000400 gran 0x0a mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 EHCI Debug Port relocated[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000dfac0000 - 0x00000000dfac3fff] size 0x00004000 gran 0x0e mem64[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000dfb00000 - 0x00000000dfbfffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 10 <- [0x00000000dfb00000 - 0x00000000dfb00fff] size 0x00001000 gran 0x0c mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000dfabc000 - 0x00000000dfabc3ff] size 0x00000400 gran 0x0a mem[0m
|
|
[7m[ERROR] PNP: 00ff.1 missing set_resources[0m
|
|
[7m[ERROR] PNP: 00ff.2 missing set_resources[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff6c - 0x000000000000ff6f] size 0x00000004 gran 0x02 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff68 - 0x000000000000ff6b] size 0x00000004 gran 0x02 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000dfabe000 - 0x00000000dfabe7ff] size 0x00000800 gran 0x0b mem[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000dfabb000 - 0x00000000dfabb0ff] size 0x00000100 gran 0x08 mem64[0m
|
|
[0m[INFO ] Done setting resources.[0m
|
|
[0m[INFO ] Done allocating resources.[0m
|
|
[0m[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 993 ms[0m
|
|
[0m[INFO ] Enabling resources...[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 cmd <- 06[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 bridge ctrl <- 0013[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 cmd <- 00[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 cmd <- 03[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 cmd <- 02[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 cmd <- 02[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 cmd <- 102[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 cmd <- 02[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 cmd <- 103[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 cmd <- 106[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 cmd <- 102[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 cmd <- 06[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 cmd <- 00[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 cmd <- 106[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 cmd <- 107[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 cmd <- 103[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 subsystem <- 17aa/220e[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 cmd <- 103[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 cmd <- 02[0m
|
|
[0m[INFO ] done.[0m
|
|
[0m[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 159 ms[0m
|
|
[0m[INFO ] Initializing devices...[0m
|
|
[0m[DEBUG] CPU_CLUSTER: 0 init[0m
|
|
[0m[INFO ] LAPIC 0x0 in XAPIC mode.[0m
|
|
[0m[DEBUG] MTRR: Physical address space:[0m
|
|
[0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m
|
|
[0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m
|
|
[0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m
|
|
[0m[DEBUG] 0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0[0m
|
|
[0m[DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1[0m
|
|
[0m[DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0[0m
|
|
[0m[DEBUG] 0x0000000100000000 - 0x000000047bdfffff size 0x37be00000 type 6[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606[0m
|
|
[0m[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits[0m
|
|
[0m[DEBUG] MTRR: default type WB/UC MTRR counts: 4/5.[0m
|
|
[0m[DEBUG] MTRR: WB selected as default type.[0m
|
|
[0m[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0[0m
|
|
[0m[DEBUG] MTRR: 1 base 0x00000000c0000000 mask 0x0000007fe0000000 type 0[0m
|
|
[0m[DEBUG] MTRR: 2 base 0x00000000e0000000 mask 0x0000007ff0000000 type 1[0m
|
|
[0m[DEBUG] MTRR: 3 base 0x00000000f0000000 mask 0x0000007ff0000000 type 0[0m
|
|
[0m
|
|
[0m[DEBUG] MTRR check[0m
|
|
[0m[DEBUG] Fixed MTRRs : Enabled[0m
|
|
[0m[DEBUG] Variable MTRRs: Enabled[0m
|
|
[0m
|
|
[0m[DEBUG] Initializing VR config.[0m
|
|
[0m[DEBUG] CPU has 2 cores, 4 threads enabled.[0m
|
|
[0m[DEBUG] Setting up SMI for CPU[0m
|
|
[0m[INFO ] Will perform SMM setup.[0m
|
|
[0m[DEBUG] microcode: sig=0x306c3 pf=0x10 revision=0x28[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0xf800 in mcache @0x7f7dd02c[0m
|
|
[0m[INFO ] CPU: Intel(R) Core(TM) i5-4300M CPU @ 2.60GHz.[0m
|
|
[0m[INFO ] LAPIC 0x0 in XAPIC mode.[0m
|
|
[0m[DEBUG] CPU: APIC: 00 enabled[0m
|
|
[0m[DEBUG] CPU: APIC: 01 enabled[0m
|
|
[0m[DEBUG] CPU: APIC: 02 enabled[0m
|
|
[0m[DEBUG] CPU: APIC: 03 enabled[0m
|
|
[0m[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178[0m
|
|
[0m[DEBUG] Processing 16 relocs. Offset value of 0x00030000[0m
|
|
[0m[DEBUG] Attempting to start 3 APs[0m
|
|
[0m[DEBUG] Waiting for 10ms after sending INIT.[0m
|
|
[0m[DEBUG] Waiting for SIPI to complete...[0m
|
|
[0m[INFO ] LAPIC 0x1 in XAPIC mode.[0m
|
|
[0m[DEBUG] done.[0m
|
|
[0m[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000028[0m
|
|
[0m[DEBUG] Waiting for SIPI to complete...[0m
|
|
[0m[DEBUG] done.[0m
|
|
[0m[INFO ] LAPIC 0x2 in XAPIC mode.[0m
|
|
[0m[INFO ] LAPIC 0x3 in XAPIC mode.[0m
|
|
[0m[INFO ] AP: slot 2 apic_id 2, MCU rev: 0x00000028[0m
|
|
[0m[INFO ] AP: slot 3 apic_id 3, MCU rev: 0x00000028[0m
|
|
[0m[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0[0m
|
|
[0m[DEBUG] Processing 9 relocs. Offset value of 0x00038000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: stack_top = 0x7f801000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400[0m
|
|
[0m[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000[0m
|
|
[0m[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f6a002d[0m
|
|
[0m[DEBUG] Installing permanent SMM handler to 0x7f800000[0m
|
|
[0m[DEBUG] HANDLER [0x7fafb000-0x7faff46f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 0[0m
|
|
[0m[DEBUG] ss0 [0x7fafac00-0x7fafafff][0m
|
|
[0m[DEBUG] stub0 [0x7faf3000-0x7faf319f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 1[0m
|
|
[0m[DEBUG] ss1 [0x7fafa800-0x7fafabff][0m
|
|
[0m[DEBUG] stub1 [0x7faf2c00-0x7faf2d9f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 2[0m
|
|
[0m[DEBUG] ss2 [0x7fafa400-0x7fafa7ff][0m
|
|
[0m[DEBUG] stub2 [0x7faf2800-0x7faf299f][0m
|
|
[0m
|
|
[0m[DEBUG] CPU 3[0m
|
|
[0m[DEBUG] ss3 [0x7fafa000-0x7fafa3ff][0m
|
|
[0m[DEBUG] stub3 [0x7faf2400-0x7faf259f][0m
|
|
[0m
|
|
[0m[DEBUG] stacks [0x7f800000-0x7f800fff][0m
|
|
[0m[DEBUG] Loading module at 0x7fafb000 with entry 0x7fafbaba. filesize: 0x4318 memsize: 0x4470[0m
|
|
[0m[DEBUG] Processing 270 relocs. Offset value of 0x7fafb000[0m
|
|
[0m[DEBUG] FMAP: area SMMSTORE found @ 810000 (524288 bytes)[0m
|
|
[0m[DEBUG] flash size 0x2800000 bytes[0m
|
|
[0m[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000[0m
|
|
[7m[ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!![0m
|
|
[0m[DEBUG] smm store: 8 # blocks with size 0x10000[0m
|
|
[0m[DEBUG] Loading module at 0x7faf3000 with entry 0x7faf3000. filesize: 0x1a0 memsize: 0x1a0[0m
|
|
[0m[DEBUG] Processing 9 relocs. Offset value of 0x7faf3000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: stack_top = 0x7f801000[0m
|
|
[0m[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400[0m
|
|
[0m[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000[0m
|
|
[0m[DEBUG] SMM Module: placing smm entry code at 7faf2c00, cpu # 0x1[0m
|
|
[0m[DEBUG] SMM Module: placing smm entry code at 7faf2800, cpu # 0x2[0m
|
|
[0m[DEBUG] SMM Module: placing smm entry code at 7faf2400, cpu # 0x3[0m
|
|
[0m[DEBUG] SMM Module: stub loaded at 7faf3000. Will call 0x7fafbaba[0m
|
|
[0m[DEBUG] SMI_STS: MCSMI PM1 [0m
|
|
[0m[DEBUG] BM TMROF TCO_STS: INTRD_DET [0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeb000, cpu = 0[0m
|
|
[0m[DEBUG] In relocation handler: CPU 0[0m
|
|
[0m[DEBUG] New SMBASE=0x7faeb000 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeac00, cpu = 1[0m
|
|
[0m[DEBUG] In relocation handler: CPU 1[0m
|
|
[0m[DEBUG] New SMBASE=0x7faeac00 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea800, cpu = 2[0m
|
|
[0m[DEBUG] In relocation handler: CPU 2[0m
|
|
[0m[DEBUG] New SMBASE=0x7faea800 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea400, cpu = 3[0m
|
|
[0m[DEBUG] In relocation handler: CPU 3[0m
|
|
[0m[DEBUG] New SMBASE=0x7faea400 IEDBASE=0x7fc00000[0m
|
|
[0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
|
|
[0m[DEBUG] Relocation complete.[0m
|
|
[0m[INFO ] microcode: Update skipped, already up-to-date[0m
|
|
[0m[INFO ] Initializing CPU #0[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] Turbo is available but hidden[0m
|
|
[0m[INFO ] Turbo is available and visible[0m
|
|
[0m[INFO ] CPU #0 initialized[0m
|
|
[0m[INFO ] Initializing CPU #1[0m
|
|
[0m[INFO ] Initializing CPU #2[0m
|
|
[0m[INFO ] Initializing CPU #3[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] CPU #2 initialized[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] CPU #3 initialized[0m
|
|
[0m[DEBUG] CPU: vendor Intel device 306c3[0m
|
|
[0m[DEBUG] CPU: family 06, model 3c, stepping 03[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled[0m
|
|
[0m[DEBUG] IA32_FEATURE_CONTROL already locked[0m
|
|
[0m[DEBUG] cpu: energy policy set to 6[0m
|
|
[0m[INFO ] CPU #1 initialized[0m
|
|
[0m[INFO ] bsp_do_flight_plan done after 488 msecs.[0m
|
|
[0m[DEBUG] CPU: frequency set to 3300[0m
|
|
[0m[DEBUG] Enabling SMIs.[0m
|
|
[0m[DEBUG] Locking SMM.[0m
|
|
[0m[DEBUG] MTRR: TEMPORARY Physical address space:[0m
|
|
[0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m
|
|
[0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m
|
|
[0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m
|
|
[0m[DEBUG] 0x0000000080000000 - 0x00000000ff7fffff size 0x7f800000 type 0[0m
|
|
[0m[DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5[0m
|
|
[0m[DEBUG] 0x0000000100000000 - 0x000000047bdfffff size 0x37be00000 type 6[0m
|
|
[0m[DEBUG] MTRR: default type WB/UC MTRR counts: 9/5.[0m
|
|
[0m[DEBUG] MTRR: UC selected as default type.[0m
|
|
[0m[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6[0m
|
|
[0m[DEBUG] MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 5[0m
|
|
[0m[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6[0m
|
|
[0m[DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000007e00000000 type 6[0m
|
|
[0m[DEBUG] MTRR: 4 base 0x0000000400000000 mask 0x0000007f80000000 type 6[0m
|
|
[0m[DEBUG] CPU_CLUSTER: 0 init finished in 886 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 init[0m
|
|
[0m[DEBUG] Disabling PEG12.[0m
|
|
[0m[DEBUG] Disabling PEG10.[0m
|
|
[0m[DEBUG] Disabling "device 7".[0m
|
|
[0m[DEBUG] Set BIOS_RESET_CPL[0m
|
|
[0m[DEBUG] CPU TDP: 37 Watts[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 init finished in 16 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 init[0m
|
|
[0m[DEBUG] PCI: 00:00:01.1 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 init[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'vbt.bin' @0x4f480 size 0x582 in mcache @0x7f7dd1e4[0m
|
|
[0m[INFO ] Found a VBT of 4608 bytes[0m
|
|
[0m[INFO ] GMA: Found VBT in CBFS[0m
|
|
[0m[INFO ] GMA: Found valid VBT in CBFS[0m
|
|
[0m[DEBUG] GT Power Management Init[0m
|
|
[0m[INFO ] GMA: Setting backlight PWM frequency to 135MHz / 128 / 4794 = 220Hz[0m
|
|
[0m[INFO ] framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32[0m
|
|
[0m[INFO ] x_res x y_res: 1366 x 768, size: 4227072 at 0xe0000000[0m
|
|
[0m[DEBUG] GT Power Management Init (post VBIOS)[0m
|
|
[0m[DEBUG] PCI: 00:00:02.0 init finished in 368 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 init[0m
|
|
[0m[DEBUG] Mini-HD: base = 0xdfac4000[0m
|
|
[0m[DEBUG] azalia_audio: initializing codec #0...[0m
|
|
[0m[DEBUG] azalia_audio: - vendor/device id: 0x80862807[0m
|
|
[0m[DEBUG] azalia_audio: - verb size: 16[0m
|
|
[0m[DEBUG] azalia_audio: - verb loaded[0m
|
|
[0m[DEBUG] PCI: 00:00:03.0 init finished in 25 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 init[0m
|
|
[0m[DEBUG] PCI: 00:00:04.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 init[0m
|
|
[0m[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 init[0m
|
|
[0m[DEBUG] ME: FW Partition Table : OK[0m
|
|
[0m[DEBUG] ME: Bringup Loader Failure : NO[0m
|
|
[0m[DEBUG] ME: Firmware Init Complete : NO[0m
|
|
[0m[DEBUG] ME: Manufacturing Mode : YES[0m
|
|
[0m[DEBUG] ME: Boot Options Present : NO[0m
|
|
[0m[DEBUG] ME: Update In Progress : NO[0m
|
|
[0m[DEBUG] ME: Current Working State : Initializing[0m
|
|
[0m[DEBUG] ME: Current Operation State : Bring up[0m
|
|
[0m[DEBUG] ME: Current Operation Mode : Debug[0m
|
|
[0m[DEBUG] ME: Error Code : No Error[0m
|
|
[0m[DEBUG] ME: Progress Phase : BUP Phase[0m
|
|
[0m[DEBUG] ME: Power Management Event : Pseudo-global reset[0m
|
|
[0m[DEBUG] ME: Progress Phase State : 0x4d[0m
|
|
[1;7m[CRIT ] intel_me_path: mbp is not ready![0m
|
|
[1m[NOTE ] ME: BIOS path: Error[0m
|
|
[7m[ERROR] ME: MBP not ready[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 init finished in 73 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 init[0m
|
|
[0m[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 init[0m
|
|
[0m[DEBUG] EHCI: Setting up controller.. done.[0m
|
|
[0m[DEBUG] PCI: 00:00:1a.0 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 init[0m
|
|
[0m[DEBUG] Azalia: base = 0xdfac0000[0m
|
|
[0m[DEBUG] Azalia: codec_mask = 01[0m
|
|
[0m[DEBUG] azalia_audio: initializing codec #0...[0m
|
|
[0m[DEBUG] azalia_audio: - vendor/device id: 0x10ec0292[0m
|
|
[0m[DEBUG] azalia_audio: - verb size: 128[0m
|
|
[0m[DEBUG] azalia_audio: - verb loaded[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 init finished in 33 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 init[0m
|
|
[0m[DEBUG] Initializing PCH PCIe bridge.[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 init[0m
|
|
[0m[DEBUG] Initializing PCH PCIe bridge.[0m
|
|
[0m[DEBUG] PCI: 00:00:1c.1 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 init[0m
|
|
[0m[DEBUG] EHCI: Setting up controller.. done.[0m
|
|
[0m[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 init[0m
|
|
[0m[DEBUG] pch: lpc_init[0m
|
|
[0m[DEBUG] IOAPIC: Initializing IOAPIC at fec00000[0m
|
|
[0m[DEBUG] IOAPIC: ID = 0x00[0m
|
|
[0m[DEBUG] IOAPIC: 24 interrupts[0m
|
|
[0m[DEBUG] IOAPIC: Clearing IOAPIC at fec00000[0m
|
|
[0m[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00[0m
|
|
[0m[INFO ] Set power on after power failure.[0m
|
|
[0m[INFO ] NMI sources enabled.[0m
|
|
[0m[DEBUG] LynxPoint H PM init[0m
|
|
[0m[DEBUG] RTC: failed = 0x0[0m
|
|
[0m[DEBUG] RTC Init[0m
|
|
[0m[DEBUG] apm_control: Disabling ACPI.[0m
|
|
[0m[DEBUG] APMC done.[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 init finished in 48 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 init[0m
|
|
[0m[DEBUG] SATA: Initializing...[0m
|
|
[0m[DEBUG] SATA: Controller in AHCI mode.[0m
|
|
[0m[DEBUG] ABAR: 0xdfabe000[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.2 init finished in 11 msecs[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 init[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 init[0m
|
|
[0m[DEBUG] PCI: 00:02:00.0 init finished in 0 msecs[0m
|
|
[0m[DEBUG] PNP: 00ff.2 init[0m
|
|
[0m[DEBUG] PNP: 00ff.2 init finished in 0 msecs[0m
|
|
[0m[INFO ] Devices initialized[0m
|
|
[0m[DEBUG] BS: BS_DEV_INIT run times (exec / console): 557 / 1089 ms[0m
|
|
[0m[DEBUG] TPM: Startup[0m
|
|
[0m[DEBUG] TPM: command 0x99 returned 0x0[0m
|
|
[0m[DEBUG] TPM: Asserting physical presence[0m
|
|
[0m[DEBUG] TPM: command 0x4000000a returned 0x0[0m
|
|
[0m[DEBUG] TPM: command 0x65 returned 0x0[0m
|
|
[0m[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1[0m
|
|
[0m[INFO ] TPM: setup succeeded[0m
|
|
[0m[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 57 / 26 ms[0m
|
|
[0m[INFO ] Finalize devices...[0m
|
|
[0m[DEBUG] PCI: 00:00:00.0 final[0m
|
|
[0m[DEBUG] PCI: 00:00:16.0 final[0m
|
|
[0m[INFO ] ME: MBP cleared[0m
|
|
[0m[DEBUG] PCI: 00:00:1b.0 final[0m
|
|
[0m[DEBUG] PCI: 00:00:1f.0 final[0m
|
|
[0m[DEBUG] apm_control: Finalizing SMM.[0m
|
|
[0m[DEBUG] APMC done.[0m
|
|
[0m[INFO ] Devices finalized[0m
|
|
[0m[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 1 / 29 ms[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x4bc00 size 0x3820 in mcache @0x7f7dd1b8[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[1;4m[WARN ] CBFS: 'fallback/slic' not found.[0m
|
|
[0m[INFO ] ACPI: Writing ACPI tables at 7f62d000.[0m
|
|
[0m[DEBUG] ACPI: * FACS[0m
|
|
[0m[DEBUG] ACPI: * FACP[0m
|
|
[0m[DEBUG] ACPI: added table 1/32, length now 44[0m
|
|
[0m[DEBUG] Found 1 CPU(s) with 4 core(s) each.[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] PSS: 2601MHz power 37000 control 0x2100 status 0x2100[0m
|
|
[0m[DEBUG] PSS: 2600MHz power 37000 control 0x1a00 status 0x1a00[0m
|
|
[0m[DEBUG] PSS: 2000MHz power 26518 control 0x1400 status 0x1400[0m
|
|
[0m[DEBUG] PSS: 1600MHz power 20229 control 0x1000 status 0x1000[0m
|
|
[0m[DEBUG] PSS: 1200MHz power 14447 control 0xc00 status 0xc00[0m
|
|
[0m[DEBUG] PSS: 800MHz power 9143 control 0x800 status 0x800[0m
|
|
[0m[DEBUG] Generating ACPI PIRQ entries[0m
|
|
[0m[INFO ] ACPI: * H8[0m
|
|
[0m[INFO ] H8: BDC detection not implemented. Assuming BDC installed[0m
|
|
[0m[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed[0m
|
|
[0m[DEBUG] PPI: Pending OS request: 0x1f7fe8 (0x90000000)[0m
|
|
[0m[DEBUG] PPI: OS response: CMD 0x1f7fe8 = 0x88000000[0m
|
|
[0m[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0[0m
|
|
[0m[DEBUG] ACPI: * SSDT[0m
|
|
[0m[DEBUG] ACPI: added table 2/32, length now 52[0m
|
|
[0m[DEBUG] ACPI: * MCFG[0m
|
|
[0m[DEBUG] ACPI: added table 3/32, length now 60[0m
|
|
[0m[DEBUG] TCPA log created at 0x7f61d000[0m
|
|
[0m[DEBUG] ACPI: * TCPA[0m
|
|
[0m[DEBUG] ACPI: added table 4/32, length now 68[0m
|
|
[0m[DEBUG] IOAPIC: 24 interrupts[0m
|
|
[0m[DEBUG] ACPI: * APIC[0m
|
|
[0m[DEBUG] ACPI: added table 5/32, length now 76[0m
|
|
[0m[DEBUG] current = 7f632610[0m
|
|
[0m[DEBUG] ACPI: * DMAR[0m
|
|
[0m[DEBUG] ACPI: added table 6/32, length now 84[0m
|
|
[0m[DEBUG] ACPI: * HPET[0m
|
|
[0m[DEBUG] ACPI: added table 7/32, length now 92[0m
|
|
[0m[DEBUG] current = 7f632710[0m
|
|
[0m[INFO ] ACPI: done.[0m
|
|
[0m[DEBUG] ACPI tables: 22288 bytes.[0m
|
|
[0m[DEBUG] smbios_write_tables: 7f615000[0m
|
|
[0m[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.12'[0m
|
|
[0m[INFO ] Create SMBIOS type 16[0m
|
|
[0m[INFO ] Create SMBIOS type 17[0m
|
|
[0m[INFO ] Create SMBIOS type 20[0m
|
|
[0m[DEBUG] SMBIOS tables: 909 bytes.[0m
|
|
[0m[DEBUG] Writing table forward entry at 0x00000500[0m
|
|
[0m[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7079[0m
|
|
[0m[DEBUG] Writing coreboot table at 0x7f651000[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'cmos_layout.bin' @0x4fb80 size 0x510 in mcache @0x7f7dd23c[0m
|
|
[0m[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 1. 0000000000001000-000000000009ffff: RAM[0m
|
|
[0m[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED[0m
|
|
[0m[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED[0m
|
|
[0m[DEBUG] 5. 0000000000100000-000000007f614fff: RAM[0m
|
|
[0m[DEBUG] 6. 000000007f615000-000000007f67dfff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 7. 000000007f67e000-000000007f7cbfff: RAMSTAGE[0m
|
|
[0m[DEBUG] 8. 000000007f7cc000-000000007f7fffff: CONFIGURATION TABLES[0m
|
|
[0m[DEBUG] 9. 000000007f800000-00000000841fffff: RESERVED[0m
|
|
[0m[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED[0m
|
|
[0m[DEBUG] 11. 00000000fed10000-00000000fed19fff: RESERVED[0m
|
|
[0m[DEBUG] 12. 00000000fed40000-00000000fed44fff: RESERVED[0m
|
|
[0m[DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED[0m
|
|
[0m[DEBUG] 14. 00000000fed90000-00000000fed91fff: RESERVED[0m
|
|
[0m[DEBUG] 15. 0000000100000000-000000047bdfffff: RAM[0m
|
|
[0m[DEBUG] FMAP: area SMMSTORE found @ 810000 (524288 bytes)[0m
|
|
[0m[DEBUG] smm store: 8 # blocks with size 0x10000[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[DEBUG] Wrote coreboot table at: 0x7f651000, 0x9c8 bytes, checksum 4e02[0m
|
|
[0m[DEBUG] coreboot table: 2528 bytes.[0m
|
|
[0m[DEBUG] IMD ROOT 0. 0x7f7ff000 0x00001000[0m
|
|
[0m[DEBUG] IMD SMALL 1. 0x7f7fe000 0x00001000[0m
|
|
[0m[DEBUG] CONSOLE 2. 0x7f7de000 0x00020000[0m
|
|
[0m[DEBUG] RO MCACHE 3. 0x7f7dd000 0x00000318[0m
|
|
[0m[DEBUG] TIME STAMP 4. 0x7f7dc000 0x00000910[0m
|
|
[0m[DEBUG] MEM INFO 5. 0x7f7da000 0x000010c8[0m
|
|
[0m[DEBUG] AFTER CAR 6. 0x7f7cc000 0x0000e000[0m
|
|
[0m[DEBUG] RAMSTAGE 7. 0x7f67d000 0x0014f000[0m
|
|
[0m[DEBUG] SMM BACKUP 8. 0x7f66d000 0x00010000[0m
|
|
[0m[DEBUG] SMM COMBUFFER 9. 0x7f65d000 0x00010000[0m
|
|
[0m[DEBUG] IGD OPREGION10. 0x7f659000 0x00003200[0m
|
|
[0m[DEBUG] COREBOOT 11. 0x7f651000 0x00008000[0m
|
|
[0m[DEBUG] ACPI 12. 0x7f62d000 0x00024000[0m
|
|
[0m[DEBUG] TCPA TCGLOG13. 0x7f61d000 0x00010000[0m
|
|
[0m[DEBUG] SMBIOS 14. 0x7f615000 0x00008000[0m
|
|
[0m[DEBUG] IMD small region:[0m
|
|
[0m[DEBUG] IMD ROOT 0. 0x7f7fec00 0x00000400[0m
|
|
[0m[DEBUG] USBDEBUG 1. 0x7f7feba0 0x00000050[0m
|
|
[0m[DEBUG] FMAP 2. 0x7f7fea80 0x0000010a[0m
|
|
[0m[DEBUG] ROMSTAGE 3. 0x7f7fea60 0x00000004[0m
|
|
[0m[DEBUG] ROMSTG STCK 4. 0x7f7fe9a0 0x000000a8[0m
|
|
[0m[DEBUG] ACPI GNVS 5. 0x7f7fe8e0 0x000000b0[0m
|
|
[0m[DEBUG] TPM PPI 6. 0x7f7fe780 0x0000015a[0m
|
|
[0m[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 2 / 572 ms[0m
|
|
[0m[DEBUG] Starting cbfs_boot_device[0m
|
|
[0m[INFO ] CBFS: Found 'fallback/payload' @0x56780 size 0x169919 in mcache @0x7f7dd2a8[0m
|
|
[0m[DEBUG] Checking segment from ROM address 0xffce77ac[0m
|
|
[0m[DEBUG] Checking segment from ROM address 0xffce77c8[0m
|
|
[0m[DEBUG] Loading segment from ROM address 0xffce77ac[0m
|
|
[0m[DEBUG] code (compression=1)[0m
|
|
[0m[DEBUG] New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffce77e4 filesize 0x1698e1[0m
|
|
[0m[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000001698e1[0m
|
|
[0m[DEBUG] using LZMA[0m
|
|
-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:02:33 --
|
|
-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:02:33 --
|
|
[0m[DEBUG] Loading segment from ROM address 0xffce77c8[0m
|
|
[0m[DEBUG] Entry Point 0x00802677[0m
|
|
[0m[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 132 / 61 ms[0m
|
|
[0m[DEBUG] ICH-NM10-PCH: watchdog disabled[0m
|
|
[0m[DEBUG] Jumping to boot code at 0x00802677(0x7f651000)[0m
|
|
-- 0:ttyAMA0 -- time-stamp -- Jän/29/26 10:02:43 --
|