|
|
|
*** Pre-CBMEM romstage console overflowed, log truncated! ***
|
|
und compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 800 MHz
|
|
[DEBUG] Selected CAS latency : 10T
|
|
[DEBUG] MPLL busy... done in 60 us
|
|
[DEBUG] MPLL frequency is set at : 800 MHz
|
|
[DEBUG] Selected CWL latency : 8T
|
|
[DEBUG] Selected tRCD : 10T
|
|
[DEBUG] Selected tRP : 10T
|
|
[DEBUG] Selected tRAS : 28T
|
|
[DEBUG] Selected tWR : 12T
|
|
[DEBUG] Selected tFAW : 20T
|
|
[DEBUG] Selected tRRD : 4T
|
|
[DEBUG] Selected tRTP : 6T
|
|
[DEBUG] Selected tWTR : 6T
|
|
[DEBUG] Selected tRFC : 208T
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 4
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 7d600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 4
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] Done jedec reset
|
|
[DEBUG] Done MRS commands
|
|
[WARN ] Logic delay 2 greater than 1: 0 0
|
|
[WARN ] Logic delay 2 greater than 1: 0 1
|
|
[DEBUG] t123: 1767, 6000, 7620
|
|
[NOTE ] ME: Wrong mode : 2
|
|
[NOTE ] ME: FWS2: 0x100a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: ME is reporting as disabled, so not waiting for a response.
|
|
[NOTE ] ME: FWS2: 0x100a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: No DID Ack received
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1596 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00620020):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 8192 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] memcfg channel[1] config (00620020):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 8192 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[INFO ] Timestamp - after RAM initialization: 3632630596
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[DEBUG] flash size 0xc00000 bytes
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x100, total 0xc00000
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[DEBUG] SF: Successfully written 2 bytes @ 0x20000
|
|
[DEBUG] SF: Successfully written 2 bytes @ 0x20002
|
|
[DEBUG] SF: Successfully written 20 bytes @ 0x20050
|
|
[DEBUG] SF: Successfully written 1588 bytes @ 0x20064
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ff79000
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 1: 0x80300000 0x100000
|
|
[DEBUG] Subregion 2: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x63d80 size 0x9b54 in mcache @0xfeff18a8
|
|
[INFO ] VB2:vb2_digest_init() 39764 bytes, hash algo 1, HW acceleration unsupported
|
|
[DEBUG] TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged
|
|
[DEBUG] Loading module at 0x7ff69000 with entry 0x7ff69031. filesize: 0x9248 memsize: 0xf5a0
|
|
[DEBUG] Processing 563 relocs. Offset value of 0x7df69000
|
|
[INFO ] Timestamp - end of romstage: 3729023647
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
|
|
|
|
|
|
[NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2176-g7e822dc-dirty Thu Jan 01 00:00:00 UTC 1970 x86_32 postcar starting (log level: 7)...
|
|
[INFO ] Timestamp - start of postcar: 3733379543
|
|
[INFO ] Timestamp - end of postcar: 3733388031
|
|
[DEBUG] Normal boot
|
|
[INFO ] Timestamp - starting to load ramstage: 3733397320
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x20b80 size 0x22dfe in mcache @0x7ff7d0dc
|
|
[INFO ] VB2:vb2_digest_init() 142846 bytes, hash algo 1, HW acceleration unsupported
|
|
[DEBUG] TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged
|
|
[INFO ] Timestamp - starting LZMA decompress (ignore for x86): 3777500627
|
|
[INFO ] Timestamp - finished LZMA decompress (ignore for x86): 3866366757
|
|
[DEBUG] Loading module at 0x7ff08000 with entry 0x7ff08000. filesize: 0x4cb40 memsize: 0x5fcf0
|
|
[DEBUG] Processing 6840 relocs. Offset value of 0x7bf08000
|
|
[INFO ] Timestamp - finished loading ramstage: 3867031158
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
|
|
|
|
|
|
[NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2176-g7e822dc-dirty Thu Jan 01 00:00:00 UTC 1970 x86_32 ramstage starting (log level: 7)...
|
|
[INFO ] Timestamp - start of ramstage: 3867244288
|
|
[DEBUG] Normal boot
|
|
[INFO ] Timestamp - device enumeration: 3867263477
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 0000 enabled
|
|
[DEBUG] DOMAIN: 0000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 00
|
|
[DEBUG] PCI: 00:00.0 [8086/0154] enabled
|
|
[DEBUG] PCI: 00:01.0 [8086/0151] disabled
|
|
[DEBUG] PCI: 00:02.0 [8086/0166] enabled
|
|
[DEBUG] PCI: 00:04.0 [8086/0153] disabled
|
|
[DEBUG] PCI: 00:14.0 [8086/1e31] enabled
|
|
[DEBUG] PCI: 00:16.0 [8086/1e3a] enabled
|
|
[DEBUG] PCI: 00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:16.3: Disabling device
|
|
[DEBUG] PCI: 00:19.0 [8086/1502] enabled
|
|
[DEBUG] PCI: 00:1a.0 [8086/1e2d] enabled
|
|
[DEBUG] PCI: 00:1b.0 [8086/1e20] enabled
|
|
[DEBUG] PCI: 00:1c.0: Found a downstream device
|
|
[INFO ] PCH: PCIe Root Port coalescing is enabled
|
|
[DEBUG] PCI: 00:1c.0 [8086/1e10] enabled
|
|
[DEBUG] PCI: 00:1c.1: Found a downstream device
|
|
[DEBUG] PCI: 00:1c.1 [8086/1e12] enabled
|
|
[DEBUG] PCI: 00:1c.2: No downstream device
|
|
[DEBUG] PCI: 00:1c.2 [8086/1e14] enabled
|
|
[DEBUG] PCI: 00:1c.3: No downstream device
|
|
[DEBUG] PCI: 00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:1c.3 [8086/1e16] disabled
|
|
[DEBUG] PCI: 00:1c.4: No downstream device
|
|
[DEBUG] PCI: 00:1c.4: Disabling device
|
|
[DEBUG] PCI: 00:1c.4: check set enabled
|
|
[DEBUG] PCI: 00:1c.5: No downstream device
|
|
[DEBUG] PCI: 00:1c.5: Disabling device
|
|
[DEBUG] PCI: 00:1c.6: No downstream device
|
|
[DEBUG] PCI: 00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:1c.7: No downstream device
|
|
[DEBUG] PCI: 00:1c.7: Disabling device
|
|
[DEBUG] PCI: 00:1d.0 [8086/1e26] enabled
|
|
[DEBUG] PCI: 00:1e.0: Disabling device
|
|
[DEBUG] PCI: 00:1e.0 [8086/2448] disabled
|
|
[DEBUG] PCI: 00:1f.0 [8086/1e55] enabled
|
|
[DEBUG] PCI: 00:1f.2 [8086/1e01] enabled
|
|
[DEBUG] PCI: 00:1f.3 [8086/1e22] enabled
|
|
[DEBUG] PCI: 00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:1f.5 [8086/1e09] disabled No operations
|
|
[DEBUG] PCI: 00:1f.6 [8086/1e24] enabled
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:01.1
|
|
[WARN ] PCI: 00:01.2
|
|
[WARN ] PCI: 00:06.0
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 01
|
|
[DEBUG] PCI: 01:00.0 [1180/e823] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L0s and L1
|
|
[INFO ] PCIe: Max_Payload_Size adjusted to 128
|
|
[DEBUG] PCI: 01:00.0: No LTR support
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 02
|
|
[DEBUG] PCI: 02:00.0 [8086/2723] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L1
|
|
[INFO ] PCIe: Max_Payload_Size adjusted to 128
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.2 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 03
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.0 scanning...
|
|
[INFO ] PMH7: ID 05 Revision 12
|
|
[DEBUG] PNP: 00ff.1 enabled
|
|
[DEBUG] PNP: 0c31.0 enabled
|
|
[INFO ] H8: EC Firmware ID G2HT35WW-3.22, Version 4.01B
|
|
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
|
|
[INFO ] H8: WWAN not installed
|
|
[DEBUG] PNP: 00ff.2 enabled
|
|
[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 2 msecs
|
|
[DEBUG] PCI: 00:1f.3 scanning...
|
|
[DEBUG] I2C: 01:54 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 3 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 3 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 0 ms
|
|
[DEBUG] BM-LOCKDOWN: Enabling boot media protection scheme 'readonly' using CTRL...
|
|
[DEBUG] flash size 0xc00000 bytes
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x100, total 0xc00000
|
|
[INFO ] spi_flash_protect: FPR 0 is enabled for range 0x00000000-0x00bfffff
|
|
[INFO ] BM-LOCKDOWN: Enabled bootmedia protection
|
|
[INFO ] Timestamp - device configuration: 3878615806
|
|
[DEBUG] found VGA at PCI: 00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x47d600000 TOLUD 0x82a00000 TOM 0x400000000
|
|
[DEBUG] MEBASE 0x7ffff00000
|
|
[DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 14294M
|
|
[ERROR] PNP: 00ff.1 missing read_resources
|
|
[ERROR] PNP: 00ff.2 missing read_resources
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (relative placement) ===
|
|
[DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 01:00.0 10 * [0x0 - 0xff] mem
|
|
[DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 02:00.0 10 * [0x0 - 0x3fff] mem
|
|
[DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] NONE 18 * [0x0 - 0x1fff] io
|
|
[DEBUG] PCI: 00:1c.2 io: size: 2000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] NONE 10 * [0x0 - 0x7fffff] mem
|
|
[DEBUG] PCI: 00:1c.2 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem
|
|
[DEBUG] PCI: 00:1c.2 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: 5e0, Tag: 100
|
|
[INFO ] * Base: 15f0, Size: 10, Tag: 100
|
|
[INFO ] * Base: 167c, Size: e984, Tag: 100
|
|
[DEBUG] PCI: 00:1c.2 1c * [0x2000 - 0x3fff] limit: 3fff io
|
|
[DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
|
|
[DEBUG] PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io
|
|
[DEBUG] PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io
|
|
[DEBUG] PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io
|
|
[DEBUG] PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io
|
|
[DEBUG] PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io
|
|
[DEBUG] PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 0000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: fdffffff
|
|
[DEBUG] DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 05 base 100000000 limit 47d5fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 09 base fed90000 limit fed90fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00.0 0a base fed91000 limit fed91fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200
|
|
[INFO ] * Base: f4000000, Size: a000000, Tag: 200
|
|
[INFO ] * Base: 47d600000, Size: b82a00000, Tag: 200
|
|
[DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
|
|
[DEBUG] PCI: 00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem
|
|
[DEBUG] PCI: 00:1c.2 24 * [0xa0000000 - 0xafffffff] limit: afffffff prefmem
|
|
[DEBUG] PCI: 00:1c.2 20 * [0x83000000 - 0x837fffff] limit: 837fffff mem
|
|
[DEBUG] PCI: 00:1c.0 20 * [0x82a00000 - 0x82afffff] limit: 82afffff mem
|
|
[DEBUG] PCI: 00:1c.1 20 * [0x82b00000 - 0x82bfffff] limit: 82bfffff mem
|
|
[DEBUG] PCI: 00:19.0 10 * [0x83800000 - 0x8381ffff] limit: 8381ffff mem
|
|
[DEBUG] PCI: 00:14.0 10 * [0x83820000 - 0x8382ffff] limit: 8382ffff mem
|
|
[DEBUG] PCI: 00:1b.0 10 * [0x83830000 - 0x83833fff] limit: 83833fff mem
|
|
[DEBUG] PCI: 00:19.0 14 * [0x83834000 - 0x83834fff] limit: 83834fff mem
|
|
[DEBUG] PCI: 00:1f.6 10 * [0x83835000 - 0x83835fff] limit: 83835fff mem
|
|
[DEBUG] PCI: 00:1f.2 24 * [0x83836000 - 0x838367ff] limit: 838367ff mem
|
|
[DEBUG] PCI: 00:1a.0 10 * [0x83837000 - 0x838373ff] limit: 838373ff mem
|
|
[DEBUG] PCI: 00:1d.0 10 * [0x83838000 - 0x838383ff] limit: 838383ff mem
|
|
[DEBUG] PCI: 00:1f.3 10 * [0x83839000 - 0x838390ff] limit: 838390ff mem
|
|
[DEBUG] PCI: 00:16.0 10 * [0x8383a000 - 0x8383a00f] limit: 8383a00f mem
|
|
[DEBUG] DOMAIN: 0000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: fdffffff done
|
|
[DEBUG] DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 01:00.0 10 * [0x82a00000 - 0x82a000ff] limit: 82a000ff mem
|
|
[DEBUG] PCI: 02:00.0 10 * [0x82b00000 - 0x82b03fff] limit: 82b03fff mem
|
|
[DEBUG] NONE 18 * [0x2000 - 0x3fff] limit: 3fff io
|
|
[DEBUG] NONE 14 * [0xa0000000 - 0xafffffff] limit: afffffff prefmem
|
|
[DEBUG] NONE 10 * [0x83000000 - 0x837fffff] limit: 837fffff mem
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:02.0 10 <- [0x0000000082c00000 - 0x0000000082ffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:14.0 10 <- [0x0000000083820000 - 0x000000008382ffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:16.0 10 <- [0x000000008383a000 - 0x000000008383a00f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:19.0 10 <- [0x0000000083800000 - 0x000000008381ffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:19.0 14 <- [0x0000000083834000 - 0x0000000083834fff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:19.0 18 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1a.0 10 <- [0x0000000083837000 - 0x00000000838373ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:1b.0 10 <- [0x0000000083830000 - 0x0000000083833fff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
|
[DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
[DEBUG] PCI: 00:1c.0 20 <- [0x0000000082a00000 - 0x0000000082afffff] size 0x00100000 gran 0x14 bus 01 mem
|
|
[DEBUG] PCI: 01:00.0 10 <- [0x0000000082a00000 - 0x0000000082a000ff] size 0x00000100 gran 0x08 mem
|
|
[DEBUG] PCI: 00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
|
[DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
|
[DEBUG] PCI: 00:1c.1 20 <- [0x0000000082b00000 - 0x0000000082bfffff] size 0x00100000 gran 0x14 bus 02 mem
|
|
[DEBUG] PCI: 02:00.0 10 <- [0x0000000082b00000 - 0x0000000082b03fff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:1c.2 1c <- [0x0000000000002000 - 0x0000000000003fff] size 0x00002000 gran 0x0c bus 03 io
|
|
[DEBUG] PCI: 00:1c.2 24 <- [0x00000000a0000000 - 0x00000000afffffff] size 0x10000000 gran 0x14 bus 03 prefmem
|
|
[DEBUG] PCI: 00:1c.2 20 <- [0x0000000083000000 - 0x00000000837fffff] size 0x00800000 gran 0x14 bus 03 mem
|
|
[DEBUG] PCI: 00:1d.0 10 <- [0x0000000083838000 - 0x00000000838383ff] size 0x00000400 gran 0x0a mem
|
|
[ERROR] PNP: 00ff.1 missing set_resources
|
|
[ERROR] PNP: 00ff.2 missing set_resources
|
|
[DEBUG] PCI: 00:1f.2 10 <- [0x0000000000001080 - 0x0000000000001087] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:1f.2 14 <- [0x0000000000001090 - 0x0000000000001093] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:1f.2 18 <- [0x0000000000001088 - 0x000000000000108f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:1f.2 1c <- [0x0000000000001094 - 0x0000000000001097] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:1f.2 20 <- [0x0000000000001060 - 0x000000000000107f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1f.2 24 <- [0x0000000083836000 - 0x00000000838367ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:1f.3 10 <- [0x0000000083839000 - 0x00000000838390ff] size 0x00000100 gran 0x08 mem64
|
|
[DEBUG] PCI: 00:1f.6 10 <- [0x0000000083835000 - 0x0000000083835fff] size 0x00001000 gran 0x0c mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
|
|
[INFO ] Timestamp - device enable: 3885836023
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00.0 subsystem <- 8086/0154
|
|
[DEBUG] PCI: 00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:02.0 subsystem <- 8086/0166
|
|
[DEBUG] PCI: 00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:14.0 subsystem <- 8086/1e31
|
|
[DEBUG] PCI: 00:14.0 cmd <- 102
|
|
[DEBUG] PCI: 00:16.0 subsystem <- 8086/1e3a
|
|
[DEBUG] PCI: 00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:19.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:1a.0 subsystem <- 8086/1e2d
|
|
[DEBUG] PCI: 00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1b.0 subsystem <- 8086/1e20
|
|
[DEBUG] PCI: 00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.0 subsystem <- 8086/1e10
|
|
[DEBUG] PCI: 00:1c.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.1 subsystem <- 8086/1e12
|
|
[DEBUG] PCI: 00:1c.1 cmd <- 102
|
|
[DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.2 subsystem <- 8086/1e14
|
|
[DEBUG] PCI: 00:1c.2 cmd <- 103
|
|
[DEBUG] PCI: 00:1d.0 subsystem <- 8086/1e26
|
|
[DEBUG] PCI: 00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1f.0 subsystem <- 8086/1e55
|
|
[DEBUG] PCI: 00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:1f.2 subsystem <- 8086/1e03
|
|
[DEBUG] PCI: 00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:1f.3 subsystem <- 8086/1e22
|
|
[DEBUG] PCI: 00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 00:1f.6 subsystem <- 8086/1e24
|
|
[DEBUG] PCI: 00:1f.6 cmd <- 02
|
|
[DEBUG] PCI: 01:00.0 subsystem <- 1180/e823
|
|
[DEBUG] PCI: 01:00.0 cmd <- 02
|
|
[DEBUG] PCI: 02:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[INFO ] Timestamp - device initialization: 3886554382
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000047d5fffff size 0x37d600000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 4/5.
|
|
[DEBUG] MTRR: WB selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000000ff0000000 type 0
|
|
[DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 2 base 0x00000000a0000000 mask 0x0000000fe0000000 type 0
|
|
[DEBUG] MTRR: 3 base 0x00000000c0000000 mask 0x0000000fc0000000 type 0
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 2 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[DEBUG] microcode: sig=0x306a9 pf=0x10 revision=0x21
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x1a340 size 0x6800 in mcache @0x7ff7d0ac
|
|
[INFO ] VB2:vb2_digest_init() 26624 bytes, hash algo 1, HW acceleration unsupported
|
|
[DEBUG] TPM: Digest of `CBFS: cpu_microcode_blob.bin` to PCR 2 logged
|
|
[INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[DEBUG] done.
|
|
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[INFO ] LAPIC 0x3 in XAPIC mode.
|
|
[INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 2 apic_id 3, MCU rev: 0x00000021
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ff2f2dd
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] HANDLER [0x802fe000-0x802ffff8]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fdc00-0x802fe000]
|
|
[DEBUG] stub0 [0x802f6000-0x802f61a0]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fd800-0x802fdc00]
|
|
[DEBUG] stub1 [0x802f5c00-0x802f5da0]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fd400-0x802fd800]
|
|
[DEBUG] stub2 [0x802f5800-0x802f59a0]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fd000-0x802fd400]
|
|
[DEBUG] stub3 [0x802f5400-0x802f55a0]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80001000]
|
|
[DEBUG] Loading module at 0x802fe000 with entry 0x802fe7f9. filesize: 0x1f98 memsize: 0x1ff8
|
|
[DEBUG] Processing 90 relocs. Offset value of 0x802fe000
|
|
[DEBUG] Loading module at 0x802f6000 with entry 0x802f6000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x802f6000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 802f6000. Will call 0x802fe7f9
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ee000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802ee000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802edc00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802edc00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed800, cpu = 2
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ed800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ed400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
|
|
[INFO ] CPU: platform id 4
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #2
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
|
|
[INFO ] CPU: platform id 4
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: platform id 4
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: platform id 4
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] CPU #3 initialized
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] CPU #2 initialized
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2900
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 9 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 39 msecs
|
|
[DEBUG] PCI: 00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling PEG10.
|
|
[DEBUG] Disabling Device 4.
|
|
[DEBUG] Disabling PEG60.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Disabling PEG IO clock.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 35 Watts
|
|
[DEBUG] PCI: 00:00.0 init finished in 1 msecs
|
|
[DEBUG] PCI: 00:02.0 init
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x52dc0 size 0x599 in mcache @0x7ff7d1fc
|
|
[INFO ] VB2:vb2_digest_init() 1433 bytes, hash algo 1, HW acceleration unsupported
|
|
[DEBUG] TPM: Digest of `CBFS: vbt.bin` to PCR 2 logged
|
|
[INFO ] Timestamp - starting LZMA decompress (ignore for x86): 4007995795
|
|
[INFO ] Timestamp - finished LZMA decompress (ignore for x86): 4009110119
|
|
[INFO ] Found a VBT of 4281 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[DEBUG] IVB GT2 25W-35W Power Meter Weights
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[0.048955] HW.GFX.GMA.Initialize
|
|
[0.048957] HW.GFX.GMA.Panel.Setup_PP_Sequencer
|
|
[0.048957] HW.GFX.GMA.Panel.Setup_PP_Sequencer
|
|
[0.048959] HW.GFX.GMA.Registers.Read: 0x00640834 <- 0x000c7208:PCH_PP_ON_DELAYS
|
|
[0.048962] HW.GFX.GMA.Registers.Read: 0x00640834 <- 0x000c720c:PCH_PP_OFF_DELAYS
|
|
[0.048964] HW.GFX.GMA.Registers.Read: 0x00186906 <- 0x000c7210:PCH_PP_DIVISOR
|
|
[0.048965] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL
|
|
[0.048967] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.048968] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.048970] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_LVDS
|
|
[0.048971] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000e1180:PCH_LVDS
|
|
[0.048972] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
|
|
[0.048973] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x00064000:DDI_BUF_CTL_A
|
|
[0.048974] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB
|
|
[0.048975] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB
|
|
[0.048976] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B
|
|
[0.048977] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4100:PCH_DP_B
|
|
[0.048978] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
|
|
[0.048980] HW.GFX.GMA.Registers.Read: 0x00180000 <- 0x000c4030:SHOTPLUG_CTL
|
|
[0.048981] HW.GFX.GMA.Registers.Write: 0x00180013 -> 0x000c4030:SHOTPLUG_CTL
|
|
[0.048983] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC
|
|
[0.048984] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1150:PCH_HDMIC
|
|
[0.048985] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C
|
|
[0.048986] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4200:PCH_DP_C
|
|
[0.048987] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
|
|
[0.048988] HW.GFX.GMA.Registers.Read: 0x00180010 <- 0x000c4030:SHOTPLUG_CTL
|
|
[0.048989] HW.GFX.GMA.Registers.Write: 0x00181310 -> 0x000c4030:SHOTPLUG_CTL
|
|
[0.048991] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID
|
|
[0.048992] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1160:PCH_HDMID
|
|
[0.048993] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D
|
|
[0.048994] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4300:PCH_DP_D
|
|
[0.048995] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
|
|
[0.048996] HW.GFX.GMA.Registers.Read: 0x00181010 <- 0x000c4030:SHOTPLUG_CTL
|
|
[0.048997] HW.GFX.GMA.Registers.Write: 0x00131010 -> 0x000c4030:SHOTPLUG_CTL
|
|
[0.049100] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
|
|
[0.049101] HW.GFX.GMA.Registers.Read: 0x00002900 <- 0x00041000:CPU_VGACNTRL
|
|
[0.049102] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
|
|
[0.049103] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL
|
|
[0.049105] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL
|
|
[0.049108] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
|
|
[0.049110] HW.GFX.GMA.Registers.Read: 0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ
|
|
[0.049111] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ
|
|
[0.049113] HW.GFX.GMA.Panel.On
|
|
[0.049113] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
|
|
[0.049115] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.049116] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
|
|
[0.049118] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.049119] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.049121] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.049122] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.049123] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049124] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
|
|
[0.049126] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.049127] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049128] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049130] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049631] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049632] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.049633] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049634] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
|
|
[0.049636] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.049637] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049638] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.049640] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050135] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050136] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.050137] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050138] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
|
|
[0.050139] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.050140] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050141] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050143] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050640] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.050641] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.050641] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.050643] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.050644] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1
|
|
[0.050646] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.050647] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.050648] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.050650] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051153] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051154] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.051155] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051156] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1
|
|
[0.051158] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.051159] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051160] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051162] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051659] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051660] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.051661] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051662] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1
|
|
[0.051664] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.051665] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051666] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.051668] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.052173] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.052174] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.052174] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.052176] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052177] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1
|
|
[0.052179] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.052180] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052181] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052183] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052687] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052688] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.052689] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052690] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1
|
|
[0.052692] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.052693] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052694] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.052696] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053198] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053199] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.053200] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053201] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1
|
|
[0.053203] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.053204] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053205] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053207] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053702] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.053703] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.053703] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.053704] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.053704] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.053706] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.053708] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.053710] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
|
|
[0.053712] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.053713] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
|
|
[0.053714] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.053716] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.553718] HW.GFX.GMA.Registers.Wait: Timed Out!
|
|
[0.553720] HW.GFX.GMA.Registers.Read: 0x00008200 <- 0x000c5108:PCH_GMBUS2
|
|
[0.553721] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.553721] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.553723] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.553725] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.553725] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.553726] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.553726] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.553727] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.553729] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.553731] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
|
|
[0.553733] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.553734] HW.GFX.GMA.Registers.Read: 0x00008200 <- 0x000c5108:PCH_GMBUS2
|
|
[0.553735] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553736] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.553836] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.553837] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553839] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553841] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
|
|
[0.553842] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553844] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.553944] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.553945] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.553947] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553949] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553950] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.553950] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.553952] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.553954] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.553954] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.553955] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.553955] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.553957] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.553959] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.553961] HW.GFX.GMA.Registers.Write: 0x00000006 -> 0x000c5100:PCH_GMBUS0
|
|
[0.553963] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.553964] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
|
|
[0.553965] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.553966] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.554064] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.554065] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.554067] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554068] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554070] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.554070] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.554072] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.554074] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.554074] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.554075] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.554075] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.554077] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.554079] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.554081] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0
|
|
[0.554083] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.554084] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
|
|
[0.554085] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554087] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.554184] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.554185] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.554187] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554189] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554191] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.554191] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.554193] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.554195] HW.GFX.GMA.Panel.Wait_On
|
|
[0.554195] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
|
|
[0.554197] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
|
|
[0.554199] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.554200] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.554202] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.554202] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.554203] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.554203] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.554204] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.554206] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.554208] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c5100:PCH_GMBUS0
|
|
[0.554210] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.554211] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
|
|
[0.554212] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554213] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.554472] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.554473] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.554475] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554477] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.554479] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.554479] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.554481] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.554483] HW.GFX.GMA.Panel.Off
|
|
[0.554483] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
|
|
[0.554485] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.554486] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL
|
|
[0.554487] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.554488] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.564491] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
|
|
[DEBUG] PCI: 00:02.0 init finished in 517 msecs
|
|
[DEBUG] PCI: 00:14.0 init
|
|
[DEBUG] XHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:14.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[CRIT ] intel_me_path: mbp is not ready!
|
|
[NOTE ] ME: BIOS path: Error
|
|
[DEBUG] ME: me_state=0, me_state_prev=0
|
|
[DEBUG] PCI: 00:16.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:19.0 init
|
|
[DEBUG] PCI: 00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:1a.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1b.0 init
|
|
[DEBUG] Azalia: base = 0x83830000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: Initializing codec #3
|
|
[DEBUG] azalia_audio: codec viddid: 80862806
|
|
[DEBUG] azalia_audio: verb_size: 16
|
|
[DEBUG] azalia_audio: verb loaded.
|
|
[DEBUG] azalia_audio: Initializing codec #0
|
|
[DEBUG] azalia_audio: codec viddid: 10ec0269
|
|
[DEBUG] azalia_audio: verb_size: 76
|
|
[DEBUG] azalia_audio: verb loaded.
|
|
[DEBUG] PCI: 00:1b.0 init finished in 5 msecs
|
|
[DEBUG] PCI: 00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:1c.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.1 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:1c.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.2 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:1c.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:1d.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected QM77, device id: 0x1e55, rev id 0x4
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources enabled.
|
|
[DEBUG] PantherPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:1f.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0x83836000
|
|
[DEBUG] PCI: 00:1f.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.3 init
|
|
[DEBUG] PCI: 00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.6 init
|
|
[DEBUG] PCI: 00:1f.6 init finished in 0 msecs
|
|
[DEBUG] PCI: 01:00.0 init
|
|
[DEBUG] PCI: 01:00.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 02:00.0 init
|
|
[DEBUG] PCI: 02:00.0 init finished in 0 msecs
|
|
[DEBUG] PNP: 00ff.2 init
|
|
[DEBUG] Keyboard init...
|
|
[ERROR] Keyboard reset failed ACK: 0xaa
|
|
[DEBUG] PNP: 00ff.2 init finished in 397 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
|
[DEBUG] I2C: 01:54 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
|
[DEBUG] I2C: 01:55 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
|
[DEBUG] I2C: 01:56 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
|
[DEBUG] I2C: 01:57 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
|
[DEBUG] Locking EEPROM RFID
|
|
[DEBUG] init EEPROM done
|
|
[DEBUG] I2C: 01:5c init finished in 26 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
|
[DEBUG] I2C: 01:5d init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
|
[DEBUG] I2C: 01:5e init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
|
[DEBUG] I2C: 01:5f init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 988 / 1 ms
|
|
[INFO ] Found TPM ST33ZP24 by ST Microelectronics
|
|
[DEBUG] TPM: Startup
|
|
[DEBUG] TPM: command 0x99 returned 0x0
|
|
[DEBUG] TPM: Asserting physical presence
|
|
[DEBUG] TPM: command 0x4000000a returned 0x0
|
|
[DEBUG] TPM: command 0x65 returned 0x0
|
|
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
|
|
[DEBUG] TPM: Write digests cached in TPM log to PCR
|
|
[DEBUG] TPM: Write digest for FMAP: FMAP into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: bootblock into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: cmos.default into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: fallback/romstage into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: cmos_layout.bin into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: fallback/postcar into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: fallback/ramstage into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: cpu_microcode_blob.bin into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Write digest for CBFS: vbt.bin into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[INFO ] TPM: setup succeeded
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 135 / 0 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:1f.0 final
|
|
[INFO ] Devices finalized
|
|
[INFO ] Timestamp - device setup done: 7676593627
|
|
[INFO ] Timestamp - cbmem post: 7676597631
|
|
[INFO ] Timestamp - write tables: 7676600747
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x4f480 size 0x38fe in mcache @0x7ff7d1d0
|
|
[INFO ] VB2:vb2_digest_init() 14590 bytes, hash algo 1, HW acceleration unsupported
|
|
[DEBUG] TPM: Extending digest for `CBFS: fallback/dsdt.aml` into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Digest of `CBFS: fallback/dsdt.aml` to PCR 2 measured
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7fec7000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] Supported C-states: C0 C1 C1E C3 C6 C7 C7S
|
|
[DEBUG] PSS: 2901MHz power 35000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2400MHz power 27295 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 21703 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 16527 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 11795 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2901MHz power 35000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2400MHz power 27295 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 21703 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 16527 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 11795 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2901MHz power 35000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2400MHz power 27295 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 21703 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 16527 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 11795 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2901MHz power 35000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
|
|
[DEBUG] PSS: 2400MHz power 27295 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 21703 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 16527 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 11795 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x47d600000, len = 0xb82a00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
|
|
[INFO ] ACPI: * H8
|
|
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
|
|
[INFO ] H8: WWAN not installed
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] TCPA log found at 0x7ff7a000
|
|
[DEBUG] ACPI: * TCPA
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] current = 7fecc3c0
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[DEBUG] current = 7fecc480
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 7/32, length now 92
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 21696 bytes.
|
|
[DEBUG] smbios_write_tables: 7febf000
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[DEBUG] SMBIOS tables: 1122 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum cfef
|
|
[DEBUG] Writing coreboot table at 0x7feeb000
|
|
[INFO ] CBFS: Found 'cmos_layout.bin' @0x53500 size 0x7dc in mcache @0x7ff7d254
|
|
[INFO ] VB2:vb2_digest_init() 2012 bytes, hash algo 1, HW acceleration unsupported
|
|
[DEBUG] TPM: Extending digest for `CBFS: cmos_layout.bin` into PCR 2
|
|
[DEBUG] TPM: command 0x14 returned 0x0
|
|
[DEBUG] TPM: Digest of `CBFS: cmos_layout.bin` to PCR 2 measured
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
|
|
[DEBUG] 3. 0000000000100000-000000007febefff: RAM
|
|
[DEBUG] 4. 000000007febf000-000000007ff07fff: CONFIGURATION TABLES
|
|
[DEBUG] 5. 000000007ff08000-000000007ff67fff: RAMSTAGE
|
|
[DEBUG] 6. 000000007ff68000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 0000000080000000-00000000829fffff: RESERVED
|
|
[DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 9. 00000000fed40000-00000000fed44fff: RESERVED
|
|
[DEBUG] 10. 00000000fed90000-00000000fed91fff: RESERVED
|
|
[DEBUG] 11. 0000000100000000-000000047d5fffff: RAM
|
|
[DEBUG] Wrote coreboot table at: 0x7feeb000, 0xbc0 bytes, checksum c2e0
|
|
[DEBUG] coreboot table: 3032 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ff7e000 0x00080000
|
|
[DEBUG] RO MCACHE 3. 0x7ff7d000 0x0000035c
|
|
[DEBUG] TIME STAMP 4. 0x7ff7c000 0x00000910
|
|
[DEBUG] TCPA TCGLOG 5. 0x7ff7a000 0x0000104c
|
|
[DEBUG] MEM INFO 6. 0x7ff79000 0x00000f48
|
|
[DEBUG] AFTER CAR 7. 0x7ff68000 0x00011000
|
|
[DEBUG] RAMSTAGE 8. 0x7ff07000 0x00061000
|
|
[DEBUG] SMM BACKUP 9. 0x7fef7000 0x00010000
|
|
[DEBUG] IGD OPREGION10. 0x7fef3000 0x000030b8
|
|
[DEBUG] COREBOOT 11. 0x7feeb000 0x00008000
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[DEBUG] ACPI 12. 0x7fec7000 0x00024000
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[DEBUG] SMBIOS 13. 0x7febf000 0x00008000
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[DEBUG] IMD small region:
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[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
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[DEBUG] FMAP 1. 0x7fffeb20 0x000000e0
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[DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004
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[DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8
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[DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100
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[INFO ] Timestamp - finalize chips: 7827708171
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[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 52 / 0 ms
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[INFO ] Timestamp - starting to load payload: 7827715607
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[INFO ] CBFS: Found 'fallback/payload' @0x6d940 size 0x6c1211 in mcache @0x7ff7d2ec
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[INFO ] VB2:vb2_digest_init() 7082513 bytes, hash algo 1, HW acceleration unsupported
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[DEBUG] TPM: Extending digest for `CBFS: fallback/payload` into PCR 2
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[DEBUG] TPM: command 0x14 returned 0x0
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[DEBUG] TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured
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[DEBUG] Checking segment from ROM address 0xff49db6c
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[DEBUG] Checking segment from ROM address 0xff49db88
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[DEBUG] Checking segment from ROM address 0xff49dba4
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[DEBUG] Checking segment from ROM address 0xff49dbc0
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[DEBUG] Checking segment from ROM address 0xff49dbdc
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[DEBUG] Checking segment from ROM address 0xff49dbf8
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[DEBUG] Loading segment from ROM address 0xff49db6c
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[DEBUG] data (compression=0)
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[DEBUG] New segment dstaddr 0x00090000 memsize 0x1000 srcaddr 0xff49dc14 filesize 0x1000
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[DEBUG] Loading Segment: addr: 0x00090000 memsz: 0x0000000000001000 filesz: 0x0000000000001000
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[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff49db88
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|
[DEBUG] code (compression=0)
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|
[DEBUG] New segment dstaddr 0x01000000 memsize 0x25fe00 srcaddr 0xff49ec14 filesize 0x25fe00
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|
[DEBUG] Loading Segment: addr: 0x01000000 memsz: 0x000000000025fe00 filesz: 0x000000000025fe00
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[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff49dba4
|
|
[DEBUG] code (compression=0)
|
|
[DEBUG] New segment dstaddr 0x00040000 memsize 0x158 srcaddr 0xff6fea14 filesize 0x158
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|
[DEBUG] Loading Segment: addr: 0x00040000 memsz: 0x0000000000000158 filesz: 0x0000000000000158
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|
[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff49dbc0
|
|
[DEBUG] data (compression=0)
|
|
[DEBUG] New segment dstaddr 0x00091000 memsize 0x11 srcaddr 0xff6feb6c filesize 0x11
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|
[DEBUG] Loading Segment: addr: 0x00091000 memsz: 0x0000000000000011 filesz: 0x0000000000000011
|
|
[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff49dbdc
|
|
[DEBUG] data (compression=0)
|
|
[DEBUG] New segment dstaddr 0x04000000 memsize 0x460200 srcaddr 0xff6feb7d filesize 0x460200
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|
[DEBUG] Loading Segment: addr: 0x04000000 memsz: 0x0000000000460200 filesz: 0x0000000000460200
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[DEBUG] it's not compressed!
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|
[DEBUG] Loading segment from ROM address 0xff49dbf8
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[DEBUG] Entry Point 0x00040000
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[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 5966 / 0 ms
|
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[INFO ] coreboot TPM 1.2 measurements:
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|
|
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[INFO ] PCR-2 3964868c3e32c845d2279b6276b5b980c79272f2 SHA1 [FMAP: FMAP]
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[INFO ] PCR-2 6c78cd7898a5c5bc150a59bafbcffb159ce5ffc0 SHA1 [CBFS: bootblock]
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[INFO ] PCR-2 0bd578da91cc0f6f570e39a813be4aaa1991f0ba SHA1 [CBFS: cmos.default]
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[INFO ] PCR-2 261c565b0a350e78080849d4876c9bb24d68d48e SHA1 [CBFS: fallback/romstage]
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[INFO ] PCR-2 b273aac8a885c56c80e9cf94764a36cd90780622 SHA1 [CBFS: cmos_layout.bin]
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[INFO ] PCR-2 976fe33aad3f08647de6cf00bd23edc9e4a3402e SHA1 [CBFS: fallback/postcar]
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|
[INFO ] PCR-2 fa370be7805543bfd08517e4466bd602316d9db8 SHA1 [CBFS: fallback/ramstage]
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|
[INFO ] PCR-2 8efffbbf487c06d4328ce4fbba2314554f2a2925 SHA1 [CBFS: cpu_microcode_blob.bin]
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|
[INFO ] PCR-2 c2335cc62820e8acd97f7b94ead60f73575cdf71 SHA1 [CBFS: vbt.bin]
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|
[INFO ] PCR-2 131e3a6af66408e638fadb06ec6d212df9dbdd01 SHA1 [CBFS: fallback/dsdt.aml]
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|
[INFO ] PCR-2 b273aac8a885c56c80e9cf94764a36cd90780622 SHA1 [CBFS: cmos_layout.bin]
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|
[INFO ] PCR-2 4312eebc4d2f907fb03b520649c4a865a0948272 SHA1 [CBFS: fallback/payload]
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|
|
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[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x00040000(0x7feeb000)
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|
[INFO ] Timestamp - selfboot jump: 25130360551
|