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coreboot-6f73573-dirty Sun May 1 15:09:55 CEST 2016 starting...
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CBFS: loading stage fallback/romstage @ 0x4002c000 (76356 bytes), entry @ 0x4002c001
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Ungating power partition 0.
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Power gate toggle request accepted.
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Ungated power partition 0.
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Ungating power partition 15.
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Ungated power partition 15.
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Ungating power partition 14.
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Power gate toggle request accepted.
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Ungated power partition 14.
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coreboot-6f73573-dirty Sun May 1 15:09:55 CEST 2016 starting...
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Exception handlers installed.
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get_sdram_config: RAMCODE=4
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Initializing SDRAM of type 2 with 792000KHz
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sdram_size_mb: Total SDRAM (MB): 4096
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LPAE Translation tables are @ 40000000
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Setting dcache policy: [0x00000000:0x80000000) [off]
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Setting dcache policy: [0x40000000:0x40200000) [writeback]
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Setting dcache policy: [0x80000000:0x00000000) [writeback]
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Setting dcache policy: [0x90000000:0x90200000) [off]
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Disabling: [0x00000000:0x00100000)
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sromstage: soc is 00000000
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CBMEM: root @ fdfff000 254 entries.
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out: cmd=0x87: 03 70 87 00 00 00 04 00 02 00 00 00
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in-header: 03 d5 00 00 04 00 00 00
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in-data: 04 20 00 00
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FMAP: Found "FLASH" version 1.1 at 40006000.
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FMAP: base = 0 size = 400000 #areas = 21
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FMAP: area GBB found
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FMAP: offset: 101000
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FMAP: size: 978688 bytes
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FMAP: GBB at 00101000 (offset 101000)
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FMAP: area VBLOCK_A found
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FMAP: offset: 200000
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FMAP: size: 8192 bytes
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FMAP: VBLOCK_A at 00200000 (offset 200000)
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FMAP: area VBLOCK_B found
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FMAP: offset: 280000
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FMAP: size: 8192 bytes
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FMAP: VBLOCK_B at 00280000 (offset 280000)
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FMAP: area FW_MAIN_A found
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FMAP: offset: 202000
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FMAP: size: 483072 bytes
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FMAP: FW_MAIN_A at 00202000 (offset 202000)
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FMAP: area FW_MAIN_B found
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FMAP: offset: 282000
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FMAP: size: 483072 bytes
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FMAP: FW_MAIN_B at 00282000 (offset 282000)
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No RW firmware selected: 0x00000003
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CBFS: loading stage fallback/coreboot_ram @ 0x80200000 (109128 bytes), entry @ 0x80200001
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oot-6f73573-dirty Sun May 1 15:09:55 CEST 2016 booting...
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Exception handlers installed.
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sdram_size_mb: Total SDRAM (MB): 4096
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CBMEM: recovering 3/254 entries from root @ fdfff000
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Enumerating buses...
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Show all devs...Before device enumeration.
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Root Device: enabled 1
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CPU_CLUSTER: 0: enabled 1
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Compare with tree...
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Root Device: enabled 1
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CPU_CLUSTER: 0: enabled 1
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scan_static_bus for Root Device
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CPU_CLUSTER: 0 enabled
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scan_static_bus for Root Device done
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done
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Allocating resources...
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Reading resources...
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Root Device read_resources bus 0 link: 0
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Root Device read_resources bus 0 link: 0 done
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Done reading resources.
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Show resources in subtree (Root Device)...After reading.
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Root Device child on link 0 CPU_CLUSTER: 0
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CPU_CLUSTER: 0
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Setting resources...
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Root Device assign_resources, bus 0 link: 0
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Root Device assign_resources, bus 0 link: 0
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Done setting resources.
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Show resources in subtree (Root Device)...After assigning values.
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Root Device child on link 0 CPU_CLUSTER: 0
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CPU_CLUSTER: 0
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Done allocating resources.
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Enabling resources...
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done.
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Initializing devices...
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Root Device init
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USBD controller set up with UTMI+ PHY
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USB3 controller set up with UTMI+ PHY
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SF: Detected W25Q32DW with page size 1000, total 400000
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FMAP: Found "FLASH" version 1.1 at 40006000.
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FMAP: base = 0 size = 400000 #areas = 21
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FMAP: area RW_ELOG found
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FMAP: offset: 27c000
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FMAP: size: 16384 bytes
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FMAP: RW_ELOG at 0027c000 (offset 27c000)
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ELOG: FLASH @0x80217468 [SPI 0x0027c000]
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ELOG: area is 4096 bytes, full threshold 3072, shrink size 1024
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ELOG: Event(17) added with size 13
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out: cmd=0x87: 03 96 87 00 00 00 04 00 f0 74 00 78
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in-header: 03 d5 00 00 04 00 00 00
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in-data: 04 20 00 00
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out: cmd=0x17: 03 5a 17 00 01 00 14 00 00 00 00 00 00 00 00 00 55 82 20 80 f0 74 00 78 04 20 00 00
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in-header: 03 5d 00 00 10 00 00 00
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in-data: 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20
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elog_add_boot_reason: Normal mode boot, nothing interesting to log
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CPU_CLUSTER: 0 init
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Extracted contents:
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header: 00 ff ff ff ff ff ff 00
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serial number: 06 af 2c 13 00 00 00 00 00 18
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version: 01 03
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basic params: 80 1d 10 78 0a
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chroma info: bb f5 94 55 54 90 27 23 50 54
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established: 00 00 00
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standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
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descriptor 1: 26 1b 56 64 50 00 16 30 30 20 36 00 25 a4 10 00 00 18
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descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
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descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
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descriptor 4: 00 00 00 fe 00 42 31 33 33 58 54 4e 30 31 2e 33 20 0a
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extensions: 00
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checksum: 4b
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Manufacturer: AUO Model 132c Serial Number 0
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Made week 0 of 2014
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EDID version: 1.3
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Digital display
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Maximum image size: 29 cm x 16 cm
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Gamma: 220%
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Check DPMS levels
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Supported color formats: RGB 4:4:4, YCrCb 4:2:2
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First detailed timing is preferred timing
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Established timings supported:
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Standard timings supported:
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Detailed timings
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Hex of detail: 261b5664500016303020360025a410000018
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Did detailed timing
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Detailed mode (IN HEX): Clock 69500 KHz, 125 mm x a4 mm
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0556 0586 05a6 05ba hborder 0
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0300 0303 0309 0316 vborder 0
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-hsync -vsync
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Hex of detail: 0000000f0000000000000000000000000020
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Manufacturer-specified data, tag 15
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Hex of detail: 000000fe0041554f0a202020202020202020
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ASCII string: AUO
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Hex of detail: 000000fe004231333358544e30312e33200a
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ASCII string: B133XTN01.3
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Checksum
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Checksum: 0x4b (valid)
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WARNING: EDID block does NOT fully conform to EDID 1.3.
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Missing name descriptor
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Missing monitor ranges
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tegra_dp_update_config: configuration updated by EDID.
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display_startup: backlight vdd setting gpio 000e007a to 1
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Setting dcache policy: [0xfe000000:0xfe300000) [writethrough]
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LCD frame buffer at 4064MiB to 4067MiB
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clock_display: PLLD=139000000 ref=12000000, m/n/p/cpcon=3/139/2/3
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MODE:1366x768@60.008Hz pclk=69500000
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update_display_mode: PixelClock=69500000, ShiftClockDiv=1
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DP config: cfg_name cfg_value
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Lane Count 1
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SupportEnhancedFraming Y
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Bandwidth 10
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bpp 18
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EnhancedFraming Y
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Scramble_enabled N
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LinkBW 10
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lane_count 1
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activespolarity 0
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active_count 37
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tu_size 64
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active_frac 15
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watermark 18
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hblank_sym 346
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vblank_sym 5169
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DP config: cfg_name cfg_value
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Lane Count 1
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SupportEnhancedFraming Y
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Bandwidth 10
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bpp 18
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EnhancedFraming Y
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Scramble_enabled N
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LinkBW 10
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lane_count 1
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activespolarity 0
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active_count 37
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tu_size 64
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active_frac 15
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watermark 18
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hblank_sym 346
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vblank_sym 5169
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Fast link trainging succeeded, link bw 10, lane 1
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tegra_dc_sor_attach: sor is attached
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display_startup: enable panel backlight pwm
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display_startup: backlight enable setting gpio 0086003a to 1
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display_startup: display init done.
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CPU: Tegra124
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Devices initialized
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Show all devs...After init.
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Root Device: enabled 1
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CPU_CLUSTER: 0: enabled 1
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Writing coreboot table at 0xfdffb000
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rom_table_end = 0xfdffb000
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... aligned to 0xfe000000
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0. 0000000080000000-00000000fdffafff: RAM
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1. 00000000fdffb000-00000000fdffffff: CONFIGURATION TABLES
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2. 00000000fe000000-00000000ffffffff: RESERVED
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3. 0000000100000000-000000017fffffff: RAM
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out: cmd=0x87: 03 cd 87 00 00 00 04 00 80 84 21 80
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in-header: 03 d5 00 00 04 00 00 00
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in-data: 04 20 00 00
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Added 5 GPIOS size 152
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Wrote coreboot table at: fdffb000, 0x2a8 bytes, checksum 5049
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coreboot table: 704 bytes.
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CBMEM ROOT 0. fdfff000 00001000
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ROMSTAGE 1. fdffe000 00001000
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VBOOT 2. fdffd000 00001000
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COREBOOT 3. fdffb000 00002000
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Loading segment from rom address 0x40006058
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code (compression=1)
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New segment dstaddr 0x83104040 memsize 0x644070 srcaddr 0x40006090 filesize 0x104ae
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(cleaned up) New segment addr 0x83104040 size 0x644070 offset 0x40006090 filesize 0x104ae
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Loading segment from rom address 0x40006074
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Entry Point 0x83104041
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Loading Segment: addr: 0x0000000083104040 memsz: 0x0000000000644070 filesz: 0x00000000000104ae
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lb: [0x0000000080200000, 0x000000008021aa48)
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Post relocation: addr: 0x0000000083104040 memsz: 0x0000000000644070 filesz: 0x00000000000104ae
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using LZMA
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[ 0x83104040, 831219c4, 0x837480b0) <- 40006090
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Clearing Segment: addr: 0x00000000831219c4 memsz: 0x00000000006266ec
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dest 83104040, end 837480b0, bouncebuffer fdfc5b70
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Loaded segments
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Jumping to boot code at 83104041
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CPU0: stack: 4001f800 - 40020000, lowest used address 4001fb20, stack used: 1248 bytes
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entry = 83104041
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Starting depthcharge on nyan_big...
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The GBB signature is at 0x83004020 and is: 24 47 42 42
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Calling VbSelectAndLoadKernel().
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cros_ec_init: CrosEC protocol version 3 supported.
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Google ChromeOS EC driver ready, id 'big_v1.1.1807-2252740'
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Clearing the recovery request.
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TPM: TlclRead(0x1008, 13)
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1.2 TPM (chip type slb9645tt device-id 0x1A)
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TPM: command 0xcf returned 0x26
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Rollback: 00000026 returned by ReadSpaceKernel(&rsk)
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Unable to get kernel versions from TPM
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VbBootRecovery() start
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VbBootRecovery() forcing device removal
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Initializing EHCI USB controller at 0x7d008100.
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Initializing EHCI USB controller at 0x7d000100.
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VbExDisplayInit: width 1376 height 768
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VbBootRecovery() attempting to load kernel2
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VbTryLoadKernel() start, get_info_flags=0x1
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VbTryLoadKernel() found 0 disks
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VbSetRecoveryRequest(90)
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VbSetRecoveryRequest(0)
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VbExDisplayBacklight called but not implemented.
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VbBootRecovery() attempting to load kernel2
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VbTryLoadKernel() start, get_info_flags=0x1
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VbTryLoadKernel() found 0 disks
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VbSetRecoveryRequest(90)
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VbSetRecoveryRequest(0)
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