coreboot-6f73573-dirty Sun May 1 15:09:55 CEST 2016 starting... CBFS: loading stage fallback/romstage @ 0x4002c000 (76356 bytes), entry @ 0x4002c001 Ungating power partition 0. Power gate toggle request accepted. Ungated power partition 0. Ungating power partition 15. Ungated power partition 15. Ungating power partition 14. Power gate toggle request accepted. Ungated power partition 14. coreboot-6f73573-dirty Sun May 1 15:09:55 CEST 2016 starting... Exception handlers installed. get_sdram_config: RAMCODE=4 Initializing SDRAM of type 2 with 792000KHz sdram_size_mb: Total SDRAM (MB): 4096 LPAE Translation tables are @ 40000000 Setting dcache policy: [0x00000000:0x80000000) [off] Setting dcache policy: [0x40000000:0x40200000) [writeback] Setting dcache policy: [0x80000000:0x00000000) [writeback] Setting dcache policy: [0x90000000:0x90200000) [off] Disabling: [0x00000000:0x00100000) sromstage: soc is 00000000 CBMEM: root @ fdfff000 254 entries. out: cmd=0x87: 03 70 87 00 00 00 04 00 02 00 00 00 in-header: 03 d5 00 00 04 00 00 00 in-data: 04 20 00 00 FMAP: Found "FLASH" version 1.1 at 40006000. FMAP: base = 0 size = 400000 #areas = 21 FMAP: area GBB found FMAP: offset: 101000 FMAP: size: 978688 bytes FMAP: GBB at 00101000 (offset 101000) FMAP: area VBLOCK_A found FMAP: offset: 200000 FMAP: size: 8192 bytes FMAP: VBLOCK_A at 00200000 (offset 200000) FMAP: area VBLOCK_B found FMAP: offset: 280000 FMAP: size: 8192 bytes FMAP: VBLOCK_B at 00280000 (offset 280000) FMAP: area FW_MAIN_A found FMAP: offset: 202000 FMAP: size: 483072 bytes FMAP: FW_MAIN_A at 00202000 (offset 202000) FMAP: area FW_MAIN_B found FMAP: offset: 282000 FMAP: size: 483072 bytes FMAP: FW_MAIN_B at 00282000 (offset 282000) No RW firmware selected: 0x00000003 CBFS: loading stage fallback/coreboot_ram @ 0x80200000 (109128 bytes), entry @ 0x80200001 oot-6f73573-dirty Sun May 1 15:09:55 CEST 2016 booting... Exception handlers installed. sdram_size_mb: Total SDRAM (MB): 4096 CBMEM: recovering 3/254 entries from root @ fdfff000 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 scan_static_bus for Root Device CPU_CLUSTER: 0 enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 Setting resources... Root Device assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 Done allocating resources. Enabling resources... done. Initializing devices... Root Device init USBD controller set up with UTMI+ PHY USB3 controller set up with UTMI+ PHY SF: Detected W25Q32DW with page size 1000, total 400000 FMAP: Found "FLASH" version 1.1 at 40006000. FMAP: base = 0 size = 400000 #areas = 21 FMAP: area RW_ELOG found FMAP: offset: 27c000 FMAP: size: 16384 bytes FMAP: RW_ELOG at 0027c000 (offset 27c000) ELOG: FLASH @0x80217468 [SPI 0x0027c000] ELOG: area is 4096 bytes, full threshold 3072, shrink size 1024 ELOG: Event(17) added with size 13 out: cmd=0x87: 03 96 87 00 00 00 04 00 f0 74 00 78 in-header: 03 d5 00 00 04 00 00 00 in-data: 04 20 00 00 out: cmd=0x17: 03 5a 17 00 01 00 14 00 00 00 00 00 00 00 00 00 55 82 20 80 f0 74 00 78 04 20 00 00 in-header: 03 5d 00 00 10 00 00 00 in-data: 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 elog_add_boot_reason: Normal mode boot, nothing interesting to log CPU_CLUSTER: 0 init Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 06 af 2c 13 00 00 00 00 00 18 version: 01 03 basic params: 80 1d 10 78 0a chroma info: bb f5 94 55 54 90 27 23 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 26 1b 56 64 50 00 16 30 30 20 36 00 25 a4 10 00 00 18 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20 descriptor 4: 00 00 00 fe 00 42 31 33 33 58 54 4e 30 31 2e 33 20 0a extensions: 00 checksum: 4b Manufacturer: AUO Model 132c Serial Number 0 Made week 0 of 2014 EDID version: 1.3 Digital display Maximum image size: 29 cm x 16 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4, YCrCb 4:2:2 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: 261b5664500016303020360025a410000018 Did detailed timing Detailed mode (IN HEX): Clock 69500 KHz, 125 mm x a4 mm 0556 0586 05a6 05ba hborder 0 0300 0303 0309 0316 vborder 0 -hsync -vsync Hex of detail: 0000000f0000000000000000000000000020 Manufacturer-specified data, tag 15 Hex of detail: 000000fe0041554f0a202020202020202020 ASCII string: AUO Hex of detail: 000000fe004231333358544e30312e33200a ASCII string: B133XTN01.3 Checksum Checksum: 0x4b (valid) WARNING: EDID block does NOT fully conform to EDID 1.3. Missing name descriptor Missing monitor ranges tegra_dp_update_config: configuration updated by EDID. display_startup: backlight vdd setting gpio 000e007a to 1 Setting dcache policy: [0xfe000000:0xfe300000) [writethrough] LCD frame buffer at 4064MiB to 4067MiB clock_display: PLLD=139000000 ref=12000000, m/n/p/cpcon=3/139/2/3 MODE:1366x768@60.008Hz pclk=69500000 update_display_mode: PixelClock=69500000, ShiftClockDiv=1 DP config: cfg_name cfg_value Lane Count 1 SupportEnhancedFraming Y Bandwidth 10 bpp 18 EnhancedFraming Y Scramble_enabled N LinkBW 10 lane_count 1 activespolarity 0 active_count 37 tu_size 64 active_frac 15 watermark 18 hblank_sym 346 vblank_sym 5169 DP config: cfg_name cfg_value Lane Count 1 SupportEnhancedFraming Y Bandwidth 10 bpp 18 EnhancedFraming Y Scramble_enabled N LinkBW 10 lane_count 1 activespolarity 0 active_count 37 tu_size 64 active_frac 15 watermark 18 hblank_sym 346 vblank_sym 5169 Fast link trainging succeeded, link bw 10, lane 1 tegra_dc_sor_attach: sor is attached display_startup: enable panel backlight pwm display_startup: backlight enable setting gpio 0086003a to 1 display_startup: display init done. CPU: Tegra124 Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 Writing coreboot table at 0xfdffb000 rom_table_end = 0xfdffb000 ... aligned to 0xfe000000 0. 0000000080000000-00000000fdffafff: RAM 1. 00000000fdffb000-00000000fdffffff: CONFIGURATION TABLES 2. 00000000fe000000-00000000ffffffff: RESERVED 3. 0000000100000000-000000017fffffff: RAM out: cmd=0x87: 03 cd 87 00 00 00 04 00 80 84 21 80 in-header: 03 d5 00 00 04 00 00 00 in-data: 04 20 00 00 Added 5 GPIOS size 152 Wrote coreboot table at: fdffb000, 0x2a8 bytes, checksum 5049 coreboot table: 704 bytes. CBMEM ROOT 0. fdfff000 00001000 ROMSTAGE 1. fdffe000 00001000 VBOOT 2. fdffd000 00001000 COREBOOT 3. fdffb000 00002000 Loading segment from rom address 0x40006058 code (compression=1) New segment dstaddr 0x83104040 memsize 0x644070 srcaddr 0x40006090 filesize 0x104ae (cleaned up) New segment addr 0x83104040 size 0x644070 offset 0x40006090 filesize 0x104ae Loading segment from rom address 0x40006074 Entry Point 0x83104041 Loading Segment: addr: 0x0000000083104040 memsz: 0x0000000000644070 filesz: 0x00000000000104ae lb: [0x0000000080200000, 0x000000008021aa48) Post relocation: addr: 0x0000000083104040 memsz: 0x0000000000644070 filesz: 0x00000000000104ae using LZMA [ 0x83104040, 831219c4, 0x837480b0) <- 40006090 Clearing Segment: addr: 0x00000000831219c4 memsz: 0x00000000006266ec dest 83104040, end 837480b0, bouncebuffer fdfc5b70 Loaded segments Jumping to boot code at 83104041 CPU0: stack: 4001f800 - 40020000, lowest used address 4001fb20, stack used: 1248 bytes entry = 83104041 Starting depthcharge on nyan_big... The GBB signature is at 0x83004020 and is: 24 47 42 42 Calling VbSelectAndLoadKernel(). cros_ec_init: CrosEC protocol version 3 supported. Google ChromeOS EC driver ready, id 'big_v1.1.1807-2252740' Clearing the recovery request. TPM: TlclRead(0x1008, 13) 1.2 TPM (chip type slb9645tt device-id 0x1A) TPM: command 0xcf returned 0x26 Rollback: 00000026 returned by ReadSpaceKernel(&rsk) Unable to get kernel versions from TPM VbBootRecovery() start VbBootRecovery() forcing device removal Initializing EHCI USB controller at 0x7d008100. Initializing EHCI USB controller at 0x7d000100. VbExDisplayInit: width 1376 height 768 VbBootRecovery() attempting to load kernel2 VbTryLoadKernel() start, get_info_flags=0x1 VbTryLoadKernel() found 0 disks VbSetRecoveryRequest(90) VbSetRecoveryRequest(0) VbExDisplayBacklight called but not implemented. VbBootRecovery() attempting to load kernel2 VbTryLoadKernel() start, get_info_flags=0x1 VbTryLoadKernel() found 0 disks VbSetRecoveryRequest(90) VbSetRecoveryRequest(0)