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Nick: hell
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E-mail: NULL
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Board: UP Squared (bad, top down enabled)
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Contents:
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[NOTE ] coreboot-4.17-1285-g8a3f5a1d0b-dirty Mon Sep 5 19:38:12 UTC 2022 bootblock starting (log level: 7)...
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[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x300000.
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[DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 15
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[INFO ] CBFS: mcache @0xfef04e00 built for 14 files, used 0x2ec of 0x4000 bytes
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[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xd158 in mcache @0xfef04e2c
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[DEBUG] BS: bootblock times (exec / console): total (unknown) / 56 ms
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[NOTE ] coreboot-4.17-1285-g8a3f5a1d0b-dirty Mon Sep 5 19:38:12 UTC 2022 romstage starting (log level: 7)...
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[INFO ] CPU: Intel(R) Celeron(R) CPU N3350 @ 1.10GHz
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[INFO ] CPU: ID 506c9, Apollolake B0, ucode: 00000028
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[INFO ] CPU: AES Supported, TXT Not Supported, VT Supported
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[INFO ] MCH: device id 5af0 (rev 0b) is Apollolake
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[INFO ] PCH: device id 5ae8 (rev 0b) is Apollolake
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[INFO ] IGD: device id 5a85 (rev 0b) is Apollolake HD 500
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[WARN ] HECI: CSE device 0f.1 is disabled
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[WARN ] HECI: CSE device 0f.2 is disabled
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[INFO ] POST: 0x00
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[DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00
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[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 0000c000
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[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
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[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
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[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
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[DEBUG] prsts: 00000000
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[DEBUG] tco_sts: 0000 0000
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[DEBUG] gen_pmcon1: 08004000 gen_pmcon2: 00003a00 gen_pmcon3: 00000000
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[DEBUG] prev_sleep_state 5
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[INFO ] CBFS: Found 'fspm.bin' @0x36740 size 0x59000 in mcache @0xfef04fc4
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[INFO ] POST: 0x34
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[DEBUG] FMAP: area RW_MRC_CACHE found @ 311000 (65536 bytes)
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[NOTE ] MRC: no data in 'RW_MRC_CACHE'
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[DEBUG] MAINBOARD: src/mainboard/up/squared/romstage.c/mainboard_memory_init_params called
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[DEBUG] MAINBOARD: Found memory SKU ID: 0x01
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[INFO ] MAINBOARD: Found supported memory: 4GB
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[DEBUG] FMAP: area RW_VAR_MRC_CACHE found @ 321000 (4096 bytes)
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[NOTE ] MRC: no data in 'RW_VAR_MRC_CACHE'
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[INFO ] POST: 0x36
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[INFO ] POST: 0x92
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[INFO ] POST: 0x98
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[DEBUG] CBMEM:
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[DEBUG] IMD: root @ 0x7afff000 254 entries.
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[DEBUG] IMD: root @ 0x7affec00 62 entries.
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[DEBUG] External stage cache:
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[DEBUG] IMD: root @ 0x7b7ff000 254 entries.
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[DEBUG] IMD: root @ 0x7b7fec00 62 entries.
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[DEBUG] FMAP: area RW_MRC_CACHE found @ 311000 (65536 bytes)
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[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
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[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
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[NOTE ] MRC: no data in 'RW_MRC_CACHE'
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[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
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[DEBUG] MRC: updated 'RW_MRC_CACHE'.
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[DEBUG] CPU: frequency set to 2400 MHz
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[DEBUG] FMAP: area RW_VAR_MRC_CACHE found @ 321000 (4096 bytes)
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[DEBUG] MRC: Checking cached data update for 'RW_VAR_MRC_CACHE'.
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[NOTE ] MRC: no data in 'RW_VAR_MRC_CACHE'
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[DEBUG] MRC: cache data 'RW_VAR_MRC_CACHE' needs update.
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[DEBUG] MRC: updated 'RW_VAR_MRC_CACHE'.
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[DEBUG] 4 DIMMs found
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[DEBUG] SMM Memory Map
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[DEBUG] SMRAM : 0x7b000000 0x800000
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[DEBUG] Subregion 0: 0x7b000000 0x700000
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[DEBUG] Subregion 1: 0x7b700000 0x100000
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[DEBUG] Subregion 2: 0x7b800000 0x0
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[DEBUG] top_of_ram = 0x7b000000
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[DEBUG] Normal boot
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[INFO ] CBFS: Found 'fallback/postcar' @0xbad40 size 0x55e0 in mcache @0xfef0503c
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[DEBUG] Loading module at 0x7abcf000 with entry 0x7abcf031. filesize: 0x51e0 memsize: 0xb550
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[DEBUG] Processing 240 relocs. Offset value of 0x78bcf000
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[DEBUG] BS: romstage times (exec / console): total (unknown) / 347 ms
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[NOTE ] coreboot-4.17-1285-g8a3f5a1d0b-dirty Mon Sep 5 19:38:12 UTC 2022 postcar starting (log level: 7)...
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[DEBUG] Normal boot
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[INFO ] CBFS: Found 'fallback/ramstage' @0x192c0 size 0x1b558 in mcache @0x7affe9bc
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[DEBUG] Loading module at 0x7ab7c000 with entry 0x7ab7c000. filesize: 0x37d38 memsize: 0x51650
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[DEBUG] Processing 3899 relocs. Offset value of 0x76b7c000
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[DEBUG] BS: postcar times (exec / console): total (unknown) / 55 ms
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[NOTE ] coreboot-4.17-1285-g8a3f5a1d0b-dirty Mon Sep 5 19:38:12 UTC 2022 ramstage starting (log level: 7)...
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[INFO ] POST: 0x39
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[INFO ] POST: 0x6f
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[DEBUG] Normal boot
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[INFO ] POST: 0x70
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[DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 3 ms
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[INFO ] POST: 0x71
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[DEBUG] FMAP: area COREBOOT found @ 342000 (12046336 bytes)
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[INFO ] CBFS: Found 'fsps.bin' @0x8f780 size 0x2b000 in mcache @0x7affeac8
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[WARN ] PCI:00.1: Could not disable the device
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[WARN ] PCI:0d.0: Could not disable the device
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[WARN ] PCI:0d.1: Could not disable the device
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[WARN ] PCI:0d.2: Could not disable the device
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[WARN ] PCI:0d.3: Could not disable the device
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[WARN ] PCI:0f.1: Could not disable the device
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[WARN ] PCI:0f.2: Could not disable the device
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[DEBUG] MAINBOARD: src/mainboard/up/squared/ramstage.c/mainboard_silicon_init_params called
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[INFO ] POST: 0x93
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[INFO ] FSPS returned 0
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[INFO ] POST: 0x99
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[INFO ] ITSS IRQ Polarities Before:
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[INFO ] IPC0: 0xffffeef8
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[INFO ] IPC1: 0xffffffff
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[INFO ] IPC2: 0xffffffff
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[INFO ] IPC3: 0x00ffffff
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[INFO ] ITSS IRQ Polarities After:
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[INFO ] IPC0: 0xffffeef8
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[INFO ] IPC1: 0x0003ffff
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[INFO ] IPC2: 0x00000000
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[INFO ] IPC3: 0x00000000
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[INFO ] CPU TDP = 6 Watts
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[INFO ] CPU PL1 = 6 Watts
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[INFO ] CPU PL2 = 7 Watts
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[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 181 / 130 ms
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[INFO ] POST: 0x72
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[INFO ] Enumerating buses...
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[DEBUG] Root Device scanning...
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[DEBUG] DOMAIN: 0000 enabled
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[DEBUG] CPU_CLUSTER: 0 enabled
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[DEBUG] MMIO: fed40000 enabled
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[DEBUG] DOMAIN: 0000 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 00
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[INFO ] POST: 0x24
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[DEBUG] PCI: 00:00.0 [8086/5af0] enabled
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[DEBUG] PCI: 00:02.0 [8086/5a85] enabled
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[DEBUG] PCI: 00:0d.0 [8086/5a92] disabled
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[DEBUG] PCI: 00:0d.1 [8086/5a94] disabled
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[DEBUG] PCI: 00:0d.2 [8086/5a96] disabled
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[DEBUG] PCI: 00:0d.3 [8086/5aec] disabled
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[DEBUG] PCI: 00:0e.0 [8086/5a98] enabled
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[DEBUG] PCI: 00:0f.0 [8086/5a9a] enabled
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[DEBUG] PCI: 00:0f.1 [8086/5a9c] disabled
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[DEBUG] PCI: 00:0f.2 [8086/5a9e] disabled
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[DEBUG] PCI: 00:12.0 [8086/5ae3] enabled
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[DEBUG] PCI: 00:13.0 subordinate bus PCI Express
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[DEBUG] PCI: 00:13.0 [8086/5ad8] enabled
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[DEBUG] PCI: 00:13.1 subordinate bus PCI Express
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[DEBUG] PCI: 00:13.1 [8086/5ad9] enabled
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[DEBUG] PCI: 00:13.2 subordinate bus PCI Express
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[DEBUG] PCI: 00:13.2 [8086/5ada] enabled
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[DEBUG] PCI: 00:13.3 subordinate bus PCI Express
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[DEBUG] PCI: 00:13.3 [8086/5adb] enabled
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[DEBUG] PCI: 00:14.0 subordinate bus PCI Express
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[DEBUG] PCI: 00:14.0 [8086/5ad6] enabled
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[DEBUG] PCI: 00:14.1 subordinate bus PCI Express
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[DEBUG] PCI: 00:14.1 [8086/5ad7] enabled
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[DEBUG] PCI: 00:15.0 [8086/5aa8] enabled
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[DEBUG] PCI: 00:15.1 [8086/5aaa] enabled
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[DEBUG] PCI: 00:16.0 [8086/5aac] enabled
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[DEBUG] PCI: 00:16.1 [8086/5aae] enabled
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[DEBUG] PCI: 00:16.2 [8086/5ab0] enabled
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[DEBUG] PCI: 00:16.3 [8086/5ab2] enabled
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[DEBUG] PCI: 00:17.0 [8086/5ab4] enabled
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[DEBUG] PCI: 00:17.1 [8086/5ab6] enabled
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[DEBUG] PCI: 00:17.2 [8086/5ab8] enabled
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[DEBUG] PCI: 00:17.3 [8086/5aba] enabled
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[DEBUG] PCI: 00:18.0 [8086/5abc] enabled
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[DEBUG] PCI: 00:18.1 [8086/5abe] enabled
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[DEBUG] PCI: 00:19.0 [8086/5ac2] enabled
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[DEBUG] PCI: 00:19.1 [8086/5ac4] enabled
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[DEBUG] PCI: 00:19.2 [8086/5ac6] enabled
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[INFO ] PCI: Static device PCI: 00:1a.0 not found, disabling it.
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[DEBUG] PCI: 00:1c.0 [8086/5acc] enabled
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[DEBUG] PCI: 00:1e.0 [8086/5ad0] enabled
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[DEBUG] PCI: 00:1f.0 [8086/5ae8] enabled
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[DEBUG] PCI: 00:1f.1 [8086/5ad4] enabled
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[INFO ] POST: 0x25
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[WARN ] PCI: Leftover static devices:
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[WARN ] PCI: 00:00.1
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[WARN ] PCI: 00:00.2
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[WARN ] PCI: 00:03.0
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[WARN ] PCI: 00:11.0
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[WARN ] PCI: 00:18.2
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[WARN ] PCI: 00:18.3
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[WARN ] PCI: 00:1a.0
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[WARN ] PCI: 00:1b.0
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[WARN ] PCI: Check your devicetree.cb.
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[DEBUG] PCI: 00:02.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:02.0 finished in 0 msecs
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[DEBUG] PCI: 00:0e.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:0e.0 finished in 0 msecs
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[DEBUG] PCI: 00:13.0 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 01
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[INFO ] POST: 0x24
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[INFO ] POST: 0x25
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[INFO ] POST: 0x55
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[DEBUG] scan_bus: bus PCI: 00:13.0 finished in 13 msecs
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[DEBUG] PCI: 00:13.1 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 02
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[INFO ] POST: 0x24
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[DEBUG] PCI: 02:00.0 [10ec/8168] enabled
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[INFO ] POST: 0x25
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[INFO ] POST: 0x55
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[INFO ] Enabling Common Clock Configuration
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[INFO ] ASPM: Enabled L1
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[INFO ] PCIe: Max_Payload_Size adjusted to 128
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[INFO ] PCI: 02:00.0: Enabled LTR
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[DEBUG] scan_bus: bus PCI: 00:13.1 finished in 36 msecs
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[DEBUG] PCI: 00:13.2 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 03
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[INFO ] POST: 0x24
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[DEBUG] PCI: 03:00.0 [10ec/8168] enabled
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[INFO ] POST: 0x25
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[INFO ] POST: 0x55
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[INFO ] Enabling Common Clock Configuration
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[INFO ] ASPM: Enabled L1
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[INFO ] PCIe: Max_Payload_Size adjusted to 128
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[INFO ] PCI: 03:00.0: Enabled LTR
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[DEBUG] scan_bus: bus PCI: 00:13.2 finished in 36 msecs
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[DEBUG] PCI: 00:13.3 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 04
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[INFO ] POST: 0x24
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[INFO ] POST: 0x25
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[INFO ] POST: 0x55
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[DEBUG] scan_bus: bus PCI: 00:13.3 finished in 13 msecs
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[DEBUG] PCI: 00:14.0 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 05
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[INFO ] POST: 0x24
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[INFO ] POST: 0x25
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[INFO ] POST: 0x55
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[DEBUG] scan_bus: bus PCI: 00:14.0 finished in 13 msecs
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[DEBUG] PCI: 00:14.1 scanning...
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[DEBUG] PCI: pci_scan_bus for bus 06
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[INFO ] POST: 0x24
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[INFO ] POST: 0x25
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[INFO ] POST: 0x55
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[DEBUG] scan_bus: bus PCI: 00:14.1 finished in 13 msecs
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[DEBUG] PCI: 00:15.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:15.0 finished in 0 msecs
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[DEBUG] PCI: 00:16.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:16.0 finished in 0 msecs
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[DEBUG] PCI: 00:16.1 scanning...
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[DEBUG] scan_bus: bus PCI: 00:16.1 finished in 0 msecs
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[DEBUG] PCI: 00:16.2 scanning...
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[DEBUG] scan_bus: bus PCI: 00:16.2 finished in 0 msecs
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[DEBUG] PCI: 00:16.3 scanning...
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[DEBUG] scan_bus: bus PCI: 00:16.3 finished in 0 msecs
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[DEBUG] PCI: 00:17.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:17.0 finished in 0 msecs
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[DEBUG] PCI: 00:17.1 scanning...
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[DEBUG] scan_bus: bus PCI: 00:17.1 finished in 0 msecs
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[DEBUG] PCI: 00:17.2 scanning...
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[DEBUG] scan_bus: bus PCI: 00:17.2 finished in 0 msecs
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[DEBUG] PCI: 00:17.3 scanning...
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[DEBUG] scan_bus: bus PCI: 00:17.3 finished in 0 msecs
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[DEBUG] PCI: 00:19.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:19.0 finished in 0 msecs
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[DEBUG] PCI: 00:19.1 scanning...
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[DEBUG] scan_bus: bus PCI: 00:19.1 finished in 0 msecs
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[DEBUG] PCI: 00:19.2 scanning...
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[DEBUG] scan_bus: bus PCI: 00:19.2 finished in 0 msecs
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[DEBUG] PCI: 00:1f.0 scanning...
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[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
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[DEBUG] PCI: 00:1f.1 scanning...
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[DEBUG] scan_bus: bus PCI: 00:1f.1 finished in 0 msecs
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[INFO ] POST: 0x55
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[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 628 msecs
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[DEBUG] scan_bus: bus Root Device finished in 650 msecs
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[INFO ] done
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[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 668 ms
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[DEBUG] FMAP: area UNIFIED_MRC_CACHE found @ 301000 (135168 bytes)
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[INFO ] MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
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[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms
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[INFO ] POST: 0x73
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[DEBUG] found VGA at PCI: 00:02.0
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[DEBUG] Setting up VGA for PCI: 00:02.0
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[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
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[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
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[INFO ] Allocating resources...
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[INFO ] Reading resources...
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[DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000
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[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000
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[INFO ] Available memory above 4GB: 2048M
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[INFO ] Done reading resources.
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[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
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[DEBUG] PCI: 00:13.1 io: size: 0 align: 12 gran: 12 limit: ffff
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[DEBUG] PCI: 02:00.0 10 * [0x0 - 0xff] io
|
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[DEBUG] PCI: 00:13.1 io: size: 1000 align: 12 gran: 12 limit: ffff done
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[DEBUG] PCI: 00:13.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
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[DEBUG] PCI: 02:00.0 18 * [0x0 - 0xfff] mem
|
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[DEBUG] PCI: 00:13.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
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[DEBUG] PCI: 00:13.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
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[DEBUG] PCI: 02:00.0 20 * [0x0 - 0x3fff] prefmem
|
|
[DEBUG] PCI: 00:13.1 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
|
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[DEBUG] PCI: 00:13.2 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 03:00.0 10 * [0x0 - 0xff] io
|
|
[DEBUG] PCI: 00:13.2 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:13.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 03:00.0 18 * [0x0 - 0xfff] mem
|
|
[DEBUG] PCI: 00:13.2 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:13.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
|
|
[DEBUG] PCI: 00:13.2 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 84 base 00000080 limit 0000008f io (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.1 20 base 0000efa0 limit 0000efbf io (fixed)
|
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[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: dfa0, Tag: 100
|
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[INFO ] * Base: efc0, Size: 1040, Tag: 100
|
|
[DEBUG] PCI: 00:13.1 1c * [0xf000 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:13.2 1c * [0xd000 - 0xdfff] limit: dfff io
|
|
[DEBUG] PCI: 00:02.0 20 * [0xefc0 - 0xefff] limit: efff io
|
|
[DEBUG] PCI: 00:12.0 20 * [0xef80 - 0xef9f] limit: ef9f io
|
|
[DEBUG] PCI: 00:12.0 18 * [0xef78 - 0xef7f] limit: ef7f io
|
|
[DEBUG] PCI: 00:12.0 1c * [0xef74 - 0xef77] limit: ef77 io
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
|
|
[DEBUG] update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 02 base fed64000 limit fed64fff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 03 base fed65000 limit fed65fff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 04 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 05 base 000c0000 limit 7affffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 06 base 7b000000 limit 7fffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 07 base 100000000 limit 17fffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 08 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 09 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0a base 11800000 limit 11bfffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0b base 11000000 limit 117fffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0c base 12000000 limit 120fffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0d base 12150000 limit 12150fff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0e base 12140000 limit 1214ffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 0f base 10000000 limit 10ffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 10 base 11c00000 limit 11ffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:00.0 11 base 12100000 limit 1213ffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:18.0 10 base ddffc000 limit ddffcfff mem (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 80000000, Size: 5dffc000, Tag: 200
|
|
[INFO ] * Base: ddffd000, Size: 2003000, Tag: 200
|
|
[INFO ] * Base: f0000000, Size: ed10000, Tag: 200
|
|
[INFO ] * Base: fed18000, Size: 4c000, Tag: 200
|
|
[INFO ] * Base: fed66000, Size: 129a000, Tag: 200
|
|
[INFO ] * Base: 180000000, Size: 7e80000000, Tag: 100200
|
|
[DEBUG] PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] limit: cfffffff prefmem
|
|
[DEBUG] PCI: 00:02.0 10 * [0xff000000 - 0xffffffff] limit: ffffffff mem
|
|
[DEBUG] PCI: 00:15.1 10 * [0xfee00000 - 0xfeffffff] limit: feffffff mem
|
|
[DEBUG] PCI: 00:0e.0 20 * [0xfec00000 - 0xfecfffff] limit: fecfffff mem
|
|
[DEBUG] PCI: 00:13.1 24 * [0xfeb00000 - 0xfebfffff] limit: febfffff prefmem
|
|
[DEBUG] PCI: 00:13.1 20 * [0xfea00000 - 0xfeafffff] limit: feafffff mem
|
|
[DEBUG] PCI: 00:13.2 24 * [0xfe900000 - 0xfe9fffff] limit: fe9fffff prefmem
|
|
[DEBUG] PCI: 00:13.2 20 * [0xfe800000 - 0xfe8fffff] limit: fe8fffff mem
|
|
[DEBUG] PCI: 00:15.0 10 * [0xfedf0000 - 0xfedfffff] limit: fedfffff mem
|
|
[DEBUG] PCI: 00:0e.0 10 * [0xfedec000 - 0xfedeffff] limit: fedeffff mem
|
|
[DEBUG] PCI: 00:12.0 10 * [0xfedea000 - 0xfedebfff] limit: fedebfff mem
|
|
[DEBUG] PCI: 00:0f.0 10 * [0xfede9000 - 0xfede9fff] limit: fede9fff mem
|
|
[DEBUG] PCI: 00:15.1 18 * [0xfede8000 - 0xfede8fff] limit: fede8fff mem
|
|
[DEBUG] PCI: 00:16.0 10 * [0xfede7000 - 0xfede7fff] limit: fede7fff mem
|
|
[DEBUG] PCI: 00:16.0 18 * [0xfede6000 - 0xfede6fff] limit: fede6fff mem
|
|
[DEBUG] PCI: 00:16.1 10 * [0xfede5000 - 0xfede5fff] limit: fede5fff mem
|
|
[DEBUG] PCI: 00:16.1 18 * [0xfede4000 - 0xfede4fff] limit: fede4fff mem
|
|
[DEBUG] PCI: 00:16.2 10 * [0xfede3000 - 0xfede3fff] limit: fede3fff mem
|
|
[DEBUG] PCI: 00:16.2 18 * [0xfede2000 - 0xfede2fff] limit: fede2fff mem
|
|
[DEBUG] PCI: 00:16.3 10 * [0xfede1000 - 0xfede1fff] limit: fede1fff mem
|
|
[DEBUG] PCI: 00:16.3 18 * [0xfede0000 - 0xfede0fff] limit: fede0fff mem
|
|
[DEBUG] PCI: 00:17.0 10 * [0xfeddf000 - 0xfeddffff] limit: feddffff mem
|
|
[DEBUG] PCI: 00:17.0 18 * [0xfedde000 - 0xfeddefff] limit: feddefff mem
|
|
[DEBUG] PCI: 00:17.1 10 * [0xfeddd000 - 0xfedddfff] limit: fedddfff mem
|
|
[DEBUG] PCI: 00:17.1 18 * [0xfeddc000 - 0xfeddcfff] limit: feddcfff mem
|
|
[DEBUG] PCI: 00:17.2 10 * [0xfeddb000 - 0xfeddbfff] limit: feddbfff mem
|
|
[DEBUG] PCI: 00:17.2 18 * [0xfedda000 - 0xfeddafff] limit: feddafff mem
|
|
[DEBUG] PCI: 00:17.3 10 * [0xfedd9000 - 0xfedd9fff] limit: fedd9fff mem
|
|
[DEBUG] PCI: 00:17.3 18 * [0xfedd8000 - 0xfedd8fff] limit: fedd8fff mem
|
|
[DEBUG] PCI: 00:18.0 18 * [0xfedd7000 - 0xfedd7fff] limit: fedd7fff mem
|
|
[DEBUG] PCI: 00:18.1 10 * [0xfedd6000 - 0xfedd6fff] limit: fedd6fff mem
|
|
[DEBUG] PCI: 00:18.1 18 * [0xfedd5000 - 0xfedd5fff] limit: fedd5fff mem
|
|
[DEBUG] PCI: 00:19.0 10 * [0xfedd4000 - 0xfedd4fff] limit: fedd4fff mem
|
|
[DEBUG] PCI: 00:19.0 18 * [0xfedd3000 - 0xfedd3fff] limit: fedd3fff mem
|
|
[DEBUG] PCI: 00:19.1 10 * [0xfedd2000 - 0xfedd2fff] limit: fedd2fff mem
|
|
[DEBUG] PCI: 00:19.1 18 * [0xfedd1000 - 0xfedd1fff] limit: fedd1fff mem
|
|
[DEBUG] PCI: 00:19.2 10 * [0xfedd0000 - 0xfedd0fff] limit: fedd0fff mem
|
|
[DEBUG] PCI: 00:19.2 18 * [0xfedcf000 - 0xfedcffff] limit: fedcffff mem
|
|
[DEBUG] PCI: 00:1c.0 10 * [0xfedce000 - 0xfedcefff] limit: fedcefff mem
|
|
[DEBUG] PCI: 00:1c.0 18 * [0xfedcd000 - 0xfedcdfff] limit: fedcdfff mem
|
|
[DEBUG] PCI: 00:1e.0 10 * [0xfedcc000 - 0xfedccfff] limit: fedccfff mem
|
|
[DEBUG] PCI: 00:1e.0 18 * [0xfedcb000 - 0xfedcbfff] limit: fedcbfff mem
|
|
[DEBUG] PCI: 00:12.0 24 * [0xfedca000 - 0xfedca7ff] limit: fedca7ff mem
|
|
[DEBUG] PCI: 00:12.0 14 * [0xfedc9000 - 0xfedc90ff] limit: fedc90ff mem
|
|
[DEBUG] PCI: 00:1f.1 10 * [0xfedc8000 - 0xfedc80ff] limit: fedc80ff mem
|
|
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
|
|
[DEBUG] PCI: 00:13.1 io: base: f000 size: 1000 align: 12 gran: 12 limit: ffff
|
|
[INFO ] PCI: 00:13.1: Resource ranges:
|
|
[INFO ] * Base: f000, Size: 1000, Tag: 100
|
|
[DEBUG] PCI: 02:00.0 10 * [0xf000 - 0xf0ff] limit: f0ff io
|
|
[DEBUG] PCI: 00:13.1 io: base: f000 size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:13.1 prefmem: base: feb00000 size: 100000 align: 20 gran: 20 limit: febfffff
|
|
[INFO ] PCI: 00:13.1: Resource ranges:
|
|
[INFO ] * Base: feb00000, Size: 100000, Tag: 1200
|
|
[DEBUG] PCI: 02:00.0 20 * [0xfeb00000 - 0xfeb03fff] limit: feb03fff prefmem
|
|
[DEBUG] PCI: 00:13.1 prefmem: base: feb00000 size: 100000 align: 20 gran: 20 limit: febfffff done
|
|
[DEBUG] PCI: 00:13.1 mem: base: fea00000 size: 100000 align: 20 gran: 20 limit: feafffff
|
|
[INFO ] PCI: 00:13.1: Resource ranges:
|
|
[INFO ] * Base: fea00000, Size: 100000, Tag: 200
|
|
[DEBUG] PCI: 02:00.0 18 * [0xfea00000 - 0xfea00fff] limit: fea00fff mem
|
|
[DEBUG] PCI: 00:13.1 mem: base: fea00000 size: 100000 align: 20 gran: 20 limit: feafffff done
|
|
[DEBUG] PCI: 00:13.2 io: base: d000 size: 1000 align: 12 gran: 12 limit: dfff
|
|
[INFO ] PCI: 00:13.2: Resource ranges:
|
|
[INFO ] * Base: d000, Size: 1000, Tag: 100
|
|
[DEBUG] PCI: 03:00.0 10 * [0xd000 - 0xd0ff] limit: d0ff io
|
|
[DEBUG] PCI: 00:13.2 io: base: d000 size: 1000 align: 12 gran: 12 limit: dfff done
|
|
[DEBUG] PCI: 00:13.2 prefmem: base: fe900000 size: 100000 align: 20 gran: 20 limit: fe9fffff
|
|
[INFO ] PCI: 00:13.2: Resource ranges:
|
|
[INFO ] * Base: fe900000, Size: 100000, Tag: 1200
|
|
[DEBUG] PCI: 03:00.0 20 * [0xfe900000 - 0xfe903fff] limit: fe903fff prefmem
|
|
[DEBUG] PCI: 00:13.2 prefmem: base: fe900000 size: 100000 align: 20 gran: 20 limit: fe9fffff done
|
|
[DEBUG] PCI: 00:13.2 mem: base: fe800000 size: 100000 align: 20 gran: 20 limit: fe8fffff
|
|
[INFO ] PCI: 00:13.2: Resource ranges:
|
|
[INFO ] * Base: fe800000, Size: 100000, Tag: 200
|
|
[DEBUG] PCI: 03:00.0 18 * [0xfe800000 - 0xfe800fff] limit: fe800fff mem
|
|
[DEBUG] PCI: 00:13.2 mem: base: fe800000 size: 100000 align: 20 gran: 20 limit: fe8fffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:02.0 10 <- [0x00000000ff000000 - 0x00000000ffffffff] size 0x01000000 gran 0x18 mem64
|
|
[DEBUG] PCI: 00:02.0 18 <- [0x00000000c0000000 - 0x00000000cfffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:02.0 20 <- [0x000000000000efc0 - 0x000000000000efff] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:0e.0 10 <- [0x00000000fedec000 - 0x00000000fedeffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:0e.0 20 <- [0x00000000fec00000 - 0x00000000fecfffff] size 0x00100000 gran 0x14 mem64
|
|
[DEBUG] PCI: 00:0f.0 10 <- [0x00000000fede9000 - 0x00000000fede9fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:12.0 10 <- [0x00000000fedea000 - 0x00000000fedebfff] size 0x00002000 gran 0x0d mem
|
|
[DEBUG] PCI: 00:12.0 14 <- [0x00000000fedc9000 - 0x00000000fedc90ff] size 0x00000100 gran 0x08 mem
|
|
[DEBUG] PCI: 00:12.0 18 <- [0x000000000000ef78 - 0x000000000000ef7f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:12.0 1c <- [0x000000000000ef74 - 0x000000000000ef77] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:12.0 20 <- [0x000000000000ef80 - 0x000000000000ef9f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:12.0 24 <- [0x00000000fedca000 - 0x00000000fedca7ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:13.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
|
[DEBUG] PCI: 00:13.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
[DEBUG] PCI: 00:13.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 01 mem
|
|
[DEBUG] PCI: 00:13.1 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c bus 02 io
|
|
[DEBUG] PCI: 00:13.1 24 <- [0x00000000feb00000 - 0x00000000febfffff] size 0x00100000 gran 0x14 bus 02 prefmem
|
|
[DEBUG] PCI: 00:13.1 20 <- [0x00000000fea00000 - 0x00000000feafffff] size 0x00100000 gran 0x14 bus 02 mem
|
|
[DEBUG] PCI: 02:00.0 10 <- [0x000000000000f000 - 0x000000000000f0ff] size 0x00000100 gran 0x08 io
|
|
[DEBUG] PCI: 02:00.0 18 <- [0x00000000fea00000 - 0x00000000fea00fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 02:00.0 20 <- [0x00000000feb00000 - 0x00000000feb03fff] size 0x00004000 gran 0x0e prefmem64
|
|
[DEBUG] PCI: 00:13.2 1c <- [0x000000000000d000 - 0x000000000000dfff] size 0x00001000 gran 0x0c bus 03 io
|
|
[DEBUG] PCI: 00:13.2 24 <- [0x00000000fe900000 - 0x00000000fe9fffff] size 0x00100000 gran 0x14 bus 03 prefmem
|
|
[DEBUG] PCI: 00:13.2 20 <- [0x00000000fe800000 - 0x00000000fe8fffff] size 0x00100000 gran 0x14 bus 03 mem
|
|
[DEBUG] PCI: 03:00.0 10 <- [0x000000000000d000 - 0x000000000000d0ff] size 0x00000100 gran 0x08 io
|
|
[DEBUG] PCI: 03:00.0 18 <- [0x00000000fe800000 - 0x00000000fe800fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 03:00.0 20 <- [0x00000000fe900000 - 0x00000000fe903fff] size 0x00004000 gran 0x0e prefmem64
|
|
[DEBUG] PCI: 00:13.3 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 04 io
|
|
[DEBUG] PCI: 00:13.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
|
|
[DEBUG] PCI: 00:13.3 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 04 mem
|
|
[DEBUG] PCI: 00:14.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 05 io
|
|
[DEBUG] PCI: 00:14.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
|
|
[DEBUG] PCI: 00:14.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 05 mem
|
|
[DEBUG] PCI: 00:14.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 06 io
|
|
[DEBUG] PCI: 00:14.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 06 prefmem
|
|
[DEBUG] PCI: 00:14.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 06 mem
|
|
[DEBUG] PCI: 00:15.0 10 <- [0x00000000fedf0000 - 0x00000000fedfffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:15.1 10 <- [0x00000000fee00000 - 0x00000000feffffff] size 0x00200000 gran 0x15 mem64
|
|
[DEBUG] PCI: 00:15.1 18 <- [0x00000000fede8000 - 0x00000000fede8fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.0 10 <- [0x00000000fede7000 - 0x00000000fede7fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.0 18 <- [0x00000000fede6000 - 0x00000000fede6fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.1 10 <- [0x00000000fede5000 - 0x00000000fede5fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.1 18 <- [0x00000000fede4000 - 0x00000000fede4fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.2 10 <- [0x00000000fede3000 - 0x00000000fede3fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.2 18 <- [0x00000000fede2000 - 0x00000000fede2fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.3 10 <- [0x00000000fede1000 - 0x00000000fede1fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:16.3 18 <- [0x00000000fede0000 - 0x00000000fede0fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.0 10 <- [0x00000000feddf000 - 0x00000000feddffff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.0 18 <- [0x00000000fedde000 - 0x00000000feddefff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.1 10 <- [0x00000000feddd000 - 0x00000000fedddfff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.1 18 <- [0x00000000feddc000 - 0x00000000feddcfff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.2 10 <- [0x00000000feddb000 - 0x00000000feddbfff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.2 18 <- [0x00000000fedda000 - 0x00000000feddafff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.3 10 <- [0x00000000fedd9000 - 0x00000000fedd9fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:17.3 18 <- [0x00000000fedd8000 - 0x00000000fedd8fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:18.0 18 <- [0x00000000fedd7000 - 0x00000000fedd7fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:18.1 10 <- [0x00000000fedd6000 - 0x00000000fedd6fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:18.1 18 <- [0x00000000fedd5000 - 0x00000000fedd5fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:19.0 10 <- [0x00000000fedd4000 - 0x00000000fedd4fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:19.0 18 <- [0x00000000fedd3000 - 0x00000000fedd3fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:19.1 10 <- [0x00000000fedd2000 - 0x00000000fedd2fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:19.1 18 <- [0x00000000fedd1000 - 0x00000000fedd1fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:19.2 10 <- [0x00000000fedd0000 - 0x00000000fedd0fff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:19.2 18 <- [0x00000000fedcf000 - 0x00000000fedcffff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:1c.0 10 <- [0x00000000fedce000 - 0x00000000fedcefff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:1c.0 18 <- [0x00000000fedcd000 - 0x00000000fedcdfff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:1e.0 10 <- [0x00000000fedcc000 - 0x00000000fedccfff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:1e.0 18 <- [0x00000000fedcb000 - 0x00000000fedcbfff] size 0x00001000 gran 0x0c mem64
|
|
[DEBUG] PCI: 00:1f.1 10 <- [0x00000000fedc8000 - 0x00000000fedc80ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1924 ms
|
|
[INFO ] POST: 0x94
|
|
[INFO ] POST: 0xa2
|
|
[DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 0 / 6 ms
|
|
[INFO ] POST: 0x74
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:00.0 cmd <- 07
|
|
[DEBUG] PCI: 00:02.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:0e.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:0e.0 cmd <- 02
|
|
[DEBUG] PCI: 00:0f.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:0f.0 cmd <- 06
|
|
[DEBUG] PCI: 00:12.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:12.0 cmd <- 03
|
|
[DEBUG] PCI: 00:13.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:13.0 cmd <- 00
|
|
[DEBUG] PCI: 00:13.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:13.1 cmd <- 07
|
|
[DEBUG] PCI: 00:13.2 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:13.2 cmd <- 07
|
|
[DEBUG] PCI: 00:13.3 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:13.3 cmd <- 00
|
|
[DEBUG] PCI: 00:14.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:14.0 cmd <- 00
|
|
[DEBUG] PCI: 00:14.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:14.1 cmd <- 00
|
|
[DEBUG] PCI: 00:15.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:15.0 cmd <- 02
|
|
[DEBUG] PCI: 00:15.1 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:15.1 cmd <- 02
|
|
[DEBUG] PCI: 00:16.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:16.1 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:16.1 cmd <- 02
|
|
[DEBUG] PCI: 00:16.2 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:16.2 cmd <- 02
|
|
[DEBUG] PCI: 00:16.3 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:16.3 cmd <- 02
|
|
[DEBUG] PCI: 00:17.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:17.0 cmd <- 02
|
|
[DEBUG] PCI: 00:17.1 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:17.1 cmd <- 02
|
|
[DEBUG] PCI: 00:17.2 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:17.2 cmd <- 02
|
|
[DEBUG] PCI: 00:17.3 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:17.3 cmd <- 02
|
|
[DEBUG] PCI: 00:18.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:18.0 cmd <- 06
|
|
[DEBUG] PCI: 00:18.1 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:18.1 cmd <- 02
|
|
[DEBUG] PCI: 00:19.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:19.0 cmd <- 02
|
|
[DEBUG] PCI: 00:19.1 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:19.1 cmd <- 02
|
|
[DEBUG] PCI: 00:19.2 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:19.2 cmd <- 02
|
|
[DEBUG] PCI: 00:1c.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:1c.0 cmd <- 06
|
|
[DEBUG] PCI: 00:1e.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:1e.0 cmd <- 06
|
|
[DEBUG] PCI: 00:1f.0 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:1f.0 cmd <- 07
|
|
[DEBUG] PCI: 00:1f.1 subsystem <- 8086/7270
|
|
[DEBUG] PCI: 00:1f.1 cmd <- 03
|
|
[DEBUG] PCI: 02:00.0 cmd <- 03
|
|
[DEBUG] PCI: 03:00.0 cmd <- 03
|
|
[INFO ] done.
|
|
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 293 ms
|
|
[DEBUG] BS: BS_DEV_INIT entry times (exec / console): 11 / 0 ms
|
|
[INFO ] POST: 0x75
|
|
[INFO ] Initializing devices...
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
|
|
[DEBUG] 0x000000007b000000 - 0x00000000bfffffff size 0x45000000 type 0
|
|
[DEBUG] 0x00000000c0000000 - 0x00000000cfffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000d0000000 - 0x00000000ffffffff size 0x30000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
|
|
[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] CPU physical address size: 39 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 6/5.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
|
|
[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
|
|
[DEBUG] MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
|
|
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[INFO ] POST: 0x93
|
|
[DEBUG] Detected 2 core, 2 thread CPU.
|
|
[INFO ] Will perform SMM setup.
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xd280 size 0xc000 in mcache @0x7affe98c
|
|
[DEBUG] microcode: sig=0x506c9 pf=0x1 revision=0x28
|
|
[INFO ] microcode: load microcode patch
|
|
[INFO ] microcode: updated to revision 0x48 date=2021-11-16
|
|
[INFO ] CPU: Intel(R) Celeron(R) CPU N3350 @ 1.10GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 18 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 1 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[INFO ] LAPIC 0x4 in XAPIC mode.
|
|
[INFO ] AP: slot 1 apic_id 4, MCU rev: 0x00000028
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
|
|
[DEBUG] Processing 11 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
|
|
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ab97f8a
|
|
[DEBUG] Installing permanent SMM handler to 0x7b000000
|
|
[DEBUG] FX_SAVE [0x7b6ffc00-0x7b700000]
|
|
[DEBUG] HANDLER [0x7b6fe000-0x7b6fee08]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x7b6fdc00-0x7b6fe000]
|
|
[DEBUG] stub0 [0x7b6f6000-0x7b6f61e0]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x7b6fd800-0x7b6fdc00]
|
|
[DEBUG] stub1 [0x7b6f5c00-0x7b6f5de0]
|
|
|
|
[DEBUG] stacks [0x7b000000-0x7b001000]
|
|
[DEBUG] Loading module at 0x7b6fe000 with entry 0x7b6fe053. filesize: 0xdf8 memsize: 0xe08
|
|
[DEBUG] Processing 87 relocs. Offset value of 0x7b6fe000
|
|
[DEBUG] Loading module at 0x7b6f6000 with entry 0x7b6f6000. filesize: 0x1e0 memsize: 0x1e0
|
|
[DEBUG] Processing 11 relocs. Offset value of 0x7b6f6000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
|
|
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x700000
|
|
[DEBUG] SMM Module: placing smm entry code at 7b6f5c00, cpu # 0x1
|
|
[DEBUG] SMM Module: stub loaded at 7b6f6000. Will call 0x7b6fe053
|
|
[DEBUG] Clearing SMI status registers
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6edc00, cpu = 1
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6ee000, cpu = 0
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 506c9
|
|
[DEBUG] CPU: family 06, model 5c, stepping 09
|
|
[DEBUG] Clearing out pending MCEs
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[DEBUG] CPU: vendor Intel device 506c9
|
|
[DEBUG] CPU: family 06, model 5c, stepping 09
|
|
[DEBUG] Clearing out pending MCEs
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 257 msecs.
|
|
[DEBUG] Enabling SMIs.
|
|
[DEBUG] MTRR: TEMPORARY Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
|
|
[DEBUG] 0x000000007b000000 - 0x00000000feffffff size 0x84000000 type 0
|
|
[DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
|
|
[DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 10/5.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
|
|
[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
|
|
[DEBUG] MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
|
|
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f80000000 type 6
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 679 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:00.0 init
|
|
[DEBUG] PCI: 00:00.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:02.0 init
|
|
[INFO ] CBFS: Found 'vbt.bin' @0xba7c0 size 0x513 in mcache @0x7affeaec
|
|
[INFO ] Found a VBT of 6154 bytes after decompression
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] PCI: 00:02.0 init finished in 71 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:0f.0 init
|
|
[DEBUG] PCI: 00:0f.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:12.0 init
|
|
[DEBUG] PCI: 00:12.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:15.0 init
|
|
[DEBUG] PCI: 00:15.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:15.1 init
|
|
[INFO ] Putting port 0 into host mode.
|
|
[INFO ] Timed out waiting for host mode.
|
|
[INFO ] XDCI port 0 host switch over took 10 ms
|
|
[DEBUG] PCI: 00:15.1 init finished in 25 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:16.0 init
|
|
[DEBUG] I2C bus 0 version 0x3132312a
|
|
[INFO ] DW I2C bus 0 at 0xfede7000 (400 KHz)
|
|
[DEBUG] PCI: 00:16.0 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:16.1 init
|
|
[DEBUG] I2C bus 1 version 0x3132312a
|
|
[INFO ] DW I2C bus 1 at 0xfede5000 (400 KHz)
|
|
[DEBUG] PCI: 00:16.1 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:16.2 init
|
|
[DEBUG] I2C bus 2 version 0x3132312a
|
|
[INFO ] DW I2C bus 2 at 0xfede3000 (400 KHz)
|
|
[DEBUG] PCI: 00:16.2 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:16.3 init
|
|
[DEBUG] I2C bus 3 version 0x3132312a
|
|
[INFO ] DW I2C bus 3 at 0xfede1000 (400 KHz)
|
|
[DEBUG] PCI: 00:16.3 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:17.0 init
|
|
[DEBUG] I2C bus 4 version 0x3132312a
|
|
[INFO ] DW I2C bus 4 at 0xfeddf000 (400 KHz)
|
|
[DEBUG] PCI: 00:17.0 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:17.1 init
|
|
[DEBUG] I2C bus 5 version 0x3132312a
|
|
[INFO ] DW I2C bus 5 at 0xfeddd000 (400 KHz)
|
|
[DEBUG] PCI: 00:17.1 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:17.2 init
|
|
[DEBUG] I2C bus 6 version 0x3132312a
|
|
[INFO ] DW I2C bus 6 at 0xfeddb000 (400 KHz)
|
|
[DEBUG] PCI: 00:17.2 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:17.3 init
|
|
[DEBUG] I2C bus 7 version 0x3132312a
|
|
[INFO ] DW I2C bus 7 at 0xfedd9000 (400 KHz)
|
|
[DEBUG] PCI: 00:17.3 init finished in 9 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:1c.0 init
|
|
[DEBUG] PCI: 00:1c.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:1e.0 init
|
|
[DEBUG] PCI: 00:1e.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:1f.0 init
|
|
[DEBUG] RTC Init
|
|
[DEBUG] PCI: 00:1f.0 init finished in 2 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 00:1f.1 init
|
|
[DEBUG] PCI: 00:1f.1 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 02:00.0 init
|
|
[DEBUG] PCI: 02:00.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[DEBUG] PCI: 03:00.0 init
|
|
[DEBUG] PCI: 03:00.0 init finished in 0 msecs
|
|
[INFO ] POST: 0x75
|
|
[INFO ] POST: 0x75
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 134 / 1046 ms
|
|
[INFO ] POST: 0x00
|
|
[DEBUG] ME: Version: 3.0.13.1144
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 7 / 7 ms
|
|
[INFO ] POST: 0x76
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:02.0 final
|
|
[DEBUG] PCI: 00:0f.0 final
|
|
[DEBUG] PCI: 00:1f.1 final
|
|
[INFO ] Devices finalized
|
|
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 21 ms
|
|
[INFO ] POST: 0x77
|
|
[DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 3 ms
|
|
[INFO ] POST: 0x79
|
|
[INFO ] POST: 0x9c
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x34e80 size 0x188e in mcache @0x7affea78
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7ab10000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * DSDT
|
|
[DEBUG] ACPI: * FADT
|
|
[DEBUG] SCI is IRQ9
|
|
[DEBUG] ACPI: added table 1/32, length now 40
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x180000000, len = 0x7e80000000
|
|
[DEBUG] Found 1 CPU(s) with 2/2 physical/logical core(s) each.
|
|
[INFO ] Turbo is available and visible
|
|
[DEBUG] PSS: 1101MHz power 6000 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 1100MHz power 6000 control 0xb00 status 0xb00
|
|
[DEBUG] PSS: 1000MHz power 5388 control 0xa00 status 0xa00
|
|
[DEBUG] PSS: 800MHz power 4213 control 0x800 status 0x800
|
|
[DEBUG] PSS: 1101MHz power 6000 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 1100MHz power 6000 control 0xb00 status 0xb00
|
|
[DEBUG] PSS: 1000MHz power 5388 control 0xa00 status 0xa00
|
|
[DEBUG] PSS: 800MHz power 4213 control 0x800 status 0x800
|
|
[DEBUG] ACPI: added table 2/32, length now 44
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 48
|
|
[DEBUG] ACPI: * MADT
|
|
[DEBUG] SCI is IRQ9
|
|
[DEBUG] ACPI: added table 4/32, length now 52
|
|
[DEBUG] current = 7ab12290
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 5/32, length now 56
|
|
[DEBUG] ACPI: added table 6/32, length now 60
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 7/32, length now 64
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 9168 bytes.
|
|
[DEBUG] smbios_write_tables: 7ab08000
|
|
[DEBUG] SMBIOS firmware version is set to coreboot_version: '4.17-1285-g8a3f5a1d0b-dirty'
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[DEBUG] SMBIOS tables: 1280 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 452b
|
|
[DEBUG] Writing coreboot table at 0x7ab34000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
|
|
[DEBUG] 3. 0000000000100000-000000000fffffff: RAM
|
|
[DEBUG] 4. 0000000010000000-0000000012150fff: RESERVED
|
|
[DEBUG] 5. 0000000012151000-000000007ab07fff: RAM
|
|
[DEBUG] 6. 000000007ab08000-000000007ab7bfff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007ab7c000-000000007abcdfff: RAMSTAGE
|
|
[DEBUG] 8. 000000007abce000-000000007affffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 000000007b000000-000000007fffffff: RESERVED
|
|
[DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
|
|
[DEBUG] 11. 00000000fed10000-00000000fed17fff: RESERVED
|
|
[DEBUG] 12. 00000000fed64000-00000000fed65fff: RESERVED
|
|
[DEBUG] 13. 0000000100000000-000000017fffffff: RAM
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
|
|
[DEBUG] Wrote coreboot table at: 0x7ab34000, 0x464 bytes, checksum eaf9
|
|
[DEBUG] coreboot table: 1148 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
|
|
[DEBUG] FSP MEMORY 2. 0x7abfe000 0x00400000
|
|
[DEBUG] CONSOLE 3. 0x7abde000 0x00020000
|
|
[DEBUG] FMAP 4. 0x7abdd000 0x000002ae
|
|
[DEBUG] TIME STAMP 5. 0x7abdc000 0x00000910
|
|
[DEBUG] MEM INFO 6. 0x7abdb000 0x00000768
|
|
[DEBUG] AFTER CAR 7. 0x7abce000 0x0000d000
|
|
[DEBUG] RAMSTAGE 8. 0x7ab7b000 0x00053000
|
|
[DEBUG] REFCODE 9. 0x7ab50000 0x0002b000
|
|
[DEBUG] SMM BACKUP 10. 0x7ab40000 0x00010000
|
|
[DEBUG] IGD OPREGION11. 0x7ab3c000 0x0000380a
|
|
[DEBUG] COREBOOT 12. 0x7ab34000 0x00008000
|
|
[DEBUG] ACPI 13. 0x7ab10000 0x00024000
|
|
[DEBUG] SMBIOS 14. 0x7ab08000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
|
|
[DEBUG] FSP RUNTIME 1. 0x7affebe0 0x00000004
|
|
[DEBUG] RO MCACHE 2. 0x7affe8e0 0x000002ec
|
|
[DEBUG] POWER STATE 3. 0x7affe8a0 0x00000040
|
|
[DEBUG] ROMSTAGE 4. 0x7affe880 0x00000004
|
|
[DEBUG] ROMSTG STCK 5. 0x7affe7c0 0x000000a8
|
|
[DEBUG] ACPI GNVS 6. 0x7affe780 0x00000030
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 5 / 464 ms
|
|
[INFO ] POST: 0x7a
|
|
[INFO ] CBFS: Found 'fallback/payload' @0xc0380 size 0x55948a in mcache @0x7affeb60
|
|
[DEBUG] Checking segment from ROM address 0xff5033ac
|
|
[DEBUG] Checking segment from ROM address 0xff5033c8
|
|
[DEBUG] Checking segment from ROM address 0xff5033e4
|
|
[DEBUG] Checking segment from ROM address 0xff503400
|
|
[DEBUG] Checking segment from ROM address 0xff50341c
|
|
[DEBUG] Checking segment from ROM address 0xff503438
|
|
[DEBUG] Loading segment from ROM address 0xff5033ac
|
|
[DEBUG] data (compression=0)
|
|
[DEBUG] New segment dstaddr 0x00090000 memsize 0x1080 srcaddr 0xff503454 filesize 0x1080
|
|
[DEBUG] Loading Segment: addr: 0x00090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080
|
|
[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff5033c8
|
|
[DEBUG] code (compression=0)
|
|
[DEBUG] New segment dstaddr 0x01000000 memsize 0x1e48e0 srcaddr 0xff5044d4 filesize 0x1e48e0
|
|
[DEBUG] Loading Segment: addr: 0x01000000 memsz: 0x00000000001e48e0 filesz: 0x00000000001e48e0
|
|
[DEBUG] it's not compressed!
|
|
[DEBUG] Loading segment from ROM address 0xff5033e4
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[DEBUG] code (compression=0)
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[DEBUG] New segment dstaddr 0x00040000 memsize 0xef srcaddr 0xff6e8db4 filesize 0xef
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[DEBUG] Loading Segment: addr: 0x00040000 memsz: 0x00000000000000ef filesz: 0x00000000000000ef
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[DEBUG] it's not compressed!
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[DEBUG] Loading segment from ROM address 0xff503400
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[DEBUG] data (compression=0)
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[DEBUG] New segment dstaddr 0x00091000 memsize 0x33 srcaddr 0xff6e8ea3 filesize 0x33
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[DEBUG] Loading Segment: addr: 0x00091000 memsz: 0x0000000000000033 filesz: 0x0000000000000033
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[DEBUG] it's not compressed!
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[DEBUG] Loading segment from ROM address 0xff50341c
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[DEBUG] data (compression=0)
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[DEBUG] New segment dstaddr 0x04000000 memsize 0x373960 srcaddr 0xff6e8ed6 filesize 0x373960
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[DEBUG] Loading Segment: addr: 0x04000000 memsz: 0x0000000000373960 filesz: 0x0000000000373960
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[DEBUG] it's not compressed!
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[DEBUG] Loading segment from ROM address 0xff503438
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[DEBUG] Entry Point 0x00040000
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[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 3429 / 228 ms
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[INFO ] POST: 0x95
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[INFO ] POST: 0xa3
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[INFO ] POST: 0x88
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[INFO ] POST: 0x89
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[DEBUG] CSE FWSTS1: 0x80000255
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[DEBUG] CSE FWSTS2: 0x30850000
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[DEBUG] CSE FWSTS3: 0x00000000
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[DEBUG] CSE FWSTS4: 0x00080000
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[DEBUG] CSE FWSTS5: 0x00000000
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[DEBUG] CSE FWSTS6: 0x00000000
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[DEBUG] CSE: Working State : 5
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[DEBUG] CSE: Manufacturing Mode : YES
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[DEBUG] CSE: Operation State : 1
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[DEBUG] CSE: FW Init Complete : YES
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[DEBUG] CSE: Error Code : 0
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[DEBUG] CSE: Operation Mode : 0
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[DEBUG] CSE: IBB Verification Result: FAIL
|
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[DEBUG] CSE: IBB Verification Done : NO
|
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[DEBUG] CSE: Actual IBB Size : 0
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|
[DEBUG] CSE: Verified Boot Valid : FAIL
|
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[DEBUG] CSE: Verified Boot Test : NO
|
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[DEBUG] CSE: FPF status : UNFUSED
|
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[DEBUG] CSE: Error Status Code : 0
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|
[INFO ] Disabling Heci using PCR
|
|
[INFO ] Putting xHCI port 0 into host mode.
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[INFO ] xHCI port 0 host switch over took 0 ms
|
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[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 13 / 115 ms
|
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[INFO ] POST: 0x7b
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[DEBUG] mp_park_aps done after 0 msecs.
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[DEBUG] Jumping to boot code at 0x00040000(0x7ab34000)
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|
[INFO ] POST: 0xf8
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