|
|
|
|
|
coreboot-e3515e3-dirty Wed Apr 27 11:27:53 UTC 2016 romstage starting...
|
|
Initial stack pointer: 000dff38
|
|
POST: 0x30
|
|
CPU APICID 00 start flag set
|
|
POST: 0x32
|
|
POST: 0x66
|
|
BSP Family_Model: 00600f12
|
|
*sysinfo range: [000c2d40,000cd04c]
|
|
bsp_apicid = 00
|
|
cpu_init_detectedx = 00000000
|
|
sb700 reset flags: 0000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'microcode_amd.bin'
|
|
CBFS: 'microcode_amd.bin' not found.
|
|
[microcode] microcode file not found. Skipping updates.
|
|
POST: 0x33
|
|
cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done
|
|
POST: 0x34
|
|
Enter amd_ht_init()
|
|
AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Forcing HT links to isochronous mode due to enabled IOMMU
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Exit amd_ht_init()
|
|
amd_ht_fixup()
|
|
amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 0)
|
|
amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 0)
|
|
POST: 0x35
|
|
cpuSetAMDPCI 00 done
|
|
cpuSetAMDPCI 01 done
|
|
Prep FID/VID Node:00
|
|
F3x80: e20be281
|
|
F3x84: 01e200e2
|
|
F3xD4: c3312f10
|
|
F3xD8: 03000016
|
|
F3xDC: 05475638
|
|
Prep FID/VID Node:01
|
|
F3x80: e20be281
|
|
F3x84: 01e200e2
|
|
F3xD4: c3312f10
|
|
F3xD8: 03000016
|
|
F3xDC: 05475638
|
|
setup_remote_node: 01 done
|
|
Start node 01 done.
|
|
POST: 0x36
|
|
core0 started: 01
|
|
sr5650_early_setup()
|
|
get_cpu_rev EAX=0x600f12.
|
|
CPU Rev is Fam 15.
|
|
NB Revision is A12.
|
|
fam10_optimization()
|
|
sr5650_por_init
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Enabling IOMMU
|
|
sb700_early_setup()
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
sb700_devices_por_init()
|
|
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
|
|
SMBus controller enabled, sb revision is A15
|
|
sb700_devices_por_init: Disabling ISA DMA support
|
|
sb700_devices_por_init(): IDE Device, BDF:0-20-1
|
|
sb700_devices_por_init(): LPC Device, BDF:0-20-3
|
|
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
|
|
sb700_devices_por_init(): SATA Device, BDF:0-17-0
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
sb700_pmio_por_init()
|
|
start_other_cores()
|
|
init node: 00 cores: 07 pass 1
|
|
Start other core - nodeid: 00 cores: 07
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
init node: 01 cores: 07 pass 1
|
|
Start other core - nodeid: 01 cores: 07
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
POST: 0x37
|
|
started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
|
|
* AP 01started
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
* AP 02started
|
|
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
|
|
* AP 03started
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
* AP 04started
|
|
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
|
|
* AP 05started
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
* AP 06started
|
|
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
|
|
* AP 07started
|
|
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
|
|
* AP 09started
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
* AP 0astarted
|
|
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
|
|
* AP 0bstarted
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
* AP 0cstarted
|
|
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
|
|
* AP 0dstarted
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
* AP 0estarted
|
|
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
|
|
* AP 0fstarted
|
|
|
|
|
|
Begin FIDVID MSR 0xc0010071 0x4aba00f6 0x4c067044
|
|
POST: 0x39
|
|
FIDVID on BSP, APIC_id: 00
|
|
BSP fid = 0
|
|
get_boot_apic_id: using 0 as APIC ID for node 0, core 0
|
|
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
|
|
get_boot_apic_id: using 8 as APIC ID for node 1, core 0
|
|
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
|
|
Wait for AP stage 1: ap_apicid = 1
|
|
readback = 1000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 2
|
|
readback = 2000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 3
|
|
readback = 3000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 4
|
|
readback = 4000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 5
|
|
readback = 5000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 6
|
|
readback = 6000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 7
|
|
readback = 7000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 8
|
|
readback = 8000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = 9
|
|
readback = 9000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = a
|
|
readback = a000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = b
|
|
readback = b000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = c
|
|
readback = c000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = d
|
|
readback = d000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = e
|
|
readback = e000014
|
|
common_fid(packed) = 0
|
|
Wait for AP stage 1: ap_apicid = f
|
|
readback = f000014
|
|
common_fid(packed) = 0
|
|
common_fid = 0
|
|
POST: 0x3a
|
|
End FIDVIDMSR 0xc0010071 0x4aba00f6 0x4c067044
|
|
POST: 0x38
|
|
sr5650_htinit: Node 0 Link 1, HT freq=e.
|
|
sr5650_htinit: HT3 mode
|
|
...WARM RESET...
|
|
|
|
|
|
|
|
|
|
coreboot-e3515e3-dirty Wed Apr 27 11:27:53 UTC 2016 romstage starting...
|
|
Initial stack pointer: 000dff38
|
|
POST: 0x30
|
|
CPU APICID 00 start flag set
|
|
POST: 0x32
|
|
POST: 0x66
|
|
BSP Family_Model: 00600f12
|
|
*sysinfo range: [000c2d40,000cd04c]
|
|
bsp_apicid = 00
|
|
cpu_init_detectedx = 00000000
|
|
sb700 reset flags: 0004
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'microcode_amd.bin'
|
|
CBFS: 'microcode_amd.bin' not found.
|
|
[microcode] microcode file not found. Skipping updates.
|
|
POST: 0x33
|
|
cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done
|
|
POST: 0x34
|
|
Enter amd_ht_init()
|
|
AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Forcing HT links to isochronous mode due to enabled IOMMU
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Exit amd_ht_init()
|
|
amd_ht_fixup()
|
|
amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 0)
|
|
amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 0)
|
|
POST: 0x35
|
|
cpuSetAMDPCI 00 done
|
|
cpuSetAMDPCI 01 done
|
|
Prep FID/VID Node:00
|
|
F3x80: e20be281
|
|
F3x84: 01e200e2
|
|
F3xD4: c3312f10
|
|
F3xD8: 03000016
|
|
F3xDC: 05475638
|
|
Prep FID/VID Node:01
|
|
F3x80: e20be281
|
|
F3x84: 01e200e2
|
|
F3xD4: c3312f10
|
|
F3xD8: 03000016
|
|
F3xDC: 05475638
|
|
setup_remote_node: 01 done
|
|
Start node 01 done.
|
|
POST: 0x36
|
|
core0 started: 01
|
|
sr5650_early_setup()
|
|
get_cpu_rev EAX=0x600f12.
|
|
CPU Rev is Fam 15.
|
|
NB Revision is A12.
|
|
fam10_optimization()
|
|
sr5650_por_init
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Enabling IOMMU
|
|
sb700_early_setup()
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
sb700_devices_por_init()
|
|
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
|
|
SMBus controller enabled, sb revision is A15
|
|
sb700_devices_por_init: Disabling ISA DMA support
|
|
sb700_devices_por_init(): IDE Device, BDF:0-20-1
|
|
sb700_devices_por_init(): LPC Device, BDF:0-20-3
|
|
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
|
|
sb700_devices_por_init(): SATA Device, BDF:0-17-0
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
sb700_pmio_por_init()
|
|
start_other_cores()
|
|
init node: 00 cores: 07 pass 1
|
|
Start other core - nodeid: 00 cores: 07
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
init node: 01 cores: 07 pass 1
|
|
Start other core - nodeid: 01 cores: 07
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
POST: 0x37
|
|
started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
|
|
* AP 01started
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
* AP 02started
|
|
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
|
|
* AP 03started
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
* AP 04started
|
|
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
|
|
* AP 05started
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
* AP 06started
|
|
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
|
|
* AP 07started
|
|
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
|
|
* AP 09started
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
* AP 0astarted
|
|
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
|
|
* AP 0bstarted
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
* AP 0cstarted
|
|
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
|
|
* AP 0dstarted
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
* AP 0estarted
|
|
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
|
|
* AP 0fstarted
|
|
|
|
|
|
Begin FIDVID MSR 0xc0010071 0x4aba00f6 0x4c026400
|
|
POST: 0x39
|
|
POST: 0x3a
|
|
End FIDVIDMSR 0xc0010071 0x4aba00f6 0x4c026400
|
|
POST: 0x38
|
|
sr5650_htinit: Node 0 Link 1, HT freq=e.
|
|
sr5650_htinit: HT3 mode
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
...WARM RESET...
|
|
|
|
|
|
|
|
|
|
coreboot-e3515e3-dirty Wed Apr 27 11:27:53 UTC 2016 romstage starting...
|
|
Initial stack pointer: 000dff38
|
|
POST: 0x30
|
|
CPU APICID 00 start flag set
|
|
POST: 0x32
|
|
POST: 0x66
|
|
BSP Family_Model: 00600f12
|
|
*sysinfo range: [000c2d40,000cd04c]
|
|
bsp_apicid = 00
|
|
cpu_init_detectedx = 00000000
|
|
sb700 reset flags: 0004
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'microcode_amd.bin'
|
|
CBFS: 'microcode_amd.bin' not found.
|
|
[microcode] microcode file not found. Skipping updates.
|
|
POST: 0x33
|
|
cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done
|
|
POST: 0x34
|
|
Enter amd_ht_init()
|
|
AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Forcing HT links to isochronous mode due to enabled IOMMU
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Exit amd_ht_init()
|
|
amd_ht_fixup()
|
|
amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 0)
|
|
amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 0)
|
|
POST: 0x35
|
|
cpuSetAMDPCI 00 done
|
|
cpuSetAMDPCI 01 done
|
|
Prep FID/VID Node:00
|
|
F3x80: e20be281
|
|
F3x84: 01e200e2
|
|
F3xD4: c3312f10
|
|
F3xD8: 03000016
|
|
F3xDC: 05475638
|
|
Prep FID/VID Node:01
|
|
F3x80: e20be281
|
|
F3x84: 01e200e2
|
|
F3xD4: c3312f10
|
|
F3xD8: 03000016
|
|
F3xDC: 05475638
|
|
setup_remote_node: 01 done
|
|
Start node 01 done.
|
|
POST: 0x36
|
|
core0 started: 01
|
|
sr5650_early_setup()
|
|
get_cpu_rev EAX=0x600f12.
|
|
CPU Rev is Fam 15.
|
|
NB Revision is A12.
|
|
fam10_optimization()
|
|
sr5650_por_init
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Enabling IOMMU
|
|
sb700_early_setup()
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
sb700_devices_por_init()
|
|
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
|
|
SMBus controller enabled, sb revision is A15
|
|
sb700_devices_por_init: Disabling ISA DMA support
|
|
sb700_devices_por_init(): IDE Device, BDF:0-20-1
|
|
sb700_devices_por_init(): LPC Device, BDF:0-20-3
|
|
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
|
|
sb700_devices_por_init(): SATA Device, BDF:0-17-0
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
sb700_pmio_por_init()
|
|
start_other_cores()
|
|
init node: 00 cores: 07 pass 1
|
|
Start other core - nodeid: 00 cores: 07
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
init node: 01 cores: 07 pass 1
|
|
Start other core - nodeid: 01 cores: 07
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
POST: 0x37
|
|
started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
|
|
* AP 01started
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
* AP 02started
|
|
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
|
|
* AP 03started
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
* AP 04started
|
|
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
|
|
* AP 05started
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
* AP 06started
|
|
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
|
|
* AP 07started
|
|
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
|
|
* AP 09started
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
* AP 0astarted
|
|
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
|
|
* AP 0bstarted
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
* AP 0cstarted
|
|
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
|
|
* AP 0dstarted
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
* AP 0estarted
|
|
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
|
|
* AP 0fstarted
|
|
|
|
|
|
Begin FIDVID MSR 0xc0010071 0x4aba00f6 0x4c026400
|
|
POST: 0x39
|
|
POST: 0x3a
|
|
End FIDVIDMSR 0xc0010071 0x4aba00f6 0x4c026400
|
|
POST: 0x38
|
|
sr5650_htinit: Node 0 Link 1, HT freq=e.
|
|
sr5650_htinit: HT3 mode
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Node 00 DIMM voltage set to index 00
|
|
Node 01 DIMM voltage set to index 00
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
POST: 0x3b
|
|
stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
|
|
* AP 01stopped
|
|
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
|
|
* AP 02stopped
|
|
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
|
|
* AP 03stopped
|
|
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
|
|
* AP 04stopped
|
|
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
|
|
* AP 05stopped
|
|
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
|
|
* AP 06stopped
|
|
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
|
|
* AP 07stopped
|
|
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
|
|
* AP 09stopped
|
|
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
|
|
* AP 0astopped
|
|
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
|
|
* AP 0bstopped
|
|
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
|
|
* AP 0cstopped
|
|
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
|
|
* AP 0dstopped
|
|
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
|
|
* AP 0estopped
|
|
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
|
|
* AP 0fstopped
|
|
|
|
fill_mem_ctrl() detected 2 nodes
|
|
POST: 0x3d
|
|
POST: 0x40
|
|
raminit_amdmct()
|
|
raminit_amdmct begin:
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
mctAutoInitMCT_D: mct_init Node 0
|
|
mctAutoInitMCT_D: mct_InitialMCT_D
|
|
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
|
|
mctAutoInitMCT_D: mctSMBhub_Init
|
|
activate_spd_rom() for node 00
|
|
enable_spd_node0()
|
|
mctAutoInitMCT_D: mct_preInitDCT
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
DIMMPresence: DIMMValid=c
|
|
DIMMPresence: DIMMPresent=c
|
|
DIMMPresence: RegDIMMPresent=c
|
|
DIMMPresence: LRDIMMPresent=0
|
|
DIMMPresence: DimmECCPresent=c
|
|
DIMMPresence: DimmPARPresent=0
|
|
DIMMPresence: Dimmx4Present=c
|
|
DIMMPresence: Dimmx8Present=0
|
|
DIMMPresence: Dimmx16Present=0
|
|
DIMMPresence: DimmPlPresent=0
|
|
DIMMPresence: DimmDRPresent=c
|
|
DIMMPresence: DimmQRPresent=0
|
|
DIMMPresence: DATAload[0]=2
|
|
DIMMPresence: MAload[0]=20
|
|
DIMMPresence: MAdimms[0]=1
|
|
DIMMPresence: DATAload[1]=2
|
|
DIMMPresence: MAload[1]=20
|
|
DIMMPresence: MAdimms[1]=1
|
|
DIMMPresence: Status 2005
|
|
DIMMPresence: ErrStatus 0
|
|
DIMMPresence: ErrCode 0
|
|
DIMMPresence: Done
|
|
|
|
DCTPreInit_D: mct_DIMMPresence Done
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 's3nv'
|
|
CBFS: Found @ offset 2fec0 size 10000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 's3nv'
|
|
CBFS: Found @ offset 2fec0 size 10000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
mctAutoInitMCT_D: mct_init Node 1
|
|
mctAutoInitMCT_D: mct_InitialMCT_D
|
|
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
|
|
mctAutoInitMCT_D: mctSMBhub_Init
|
|
activate_spd_rom() for node 01
|
|
enable_spd_node1()
|
|
mctAutoInitMCT_D: mct_preInitDCT
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
DIMMPresence: DIMMValid=0
|
|
DIMMPresence: DIMMPresent=0
|
|
DIMMPresence: RegDIMMPresent=0
|
|
DIMMPresence: LRDIMMPresent=0
|
|
DIMMPresence: DimmECCPresent=0
|
|
DIMMPresence: DimmPARPresent=0
|
|
DIMMPresence: Dimmx4Present=0
|
|
DIMMPresence: Dimmx8Present=0
|
|
DIMMPresence: Dimmx16Present=0
|
|
DIMMPresence: DimmPlPresent=0
|
|
DIMMPresence: DimmDRPresent=0
|
|
DIMMPresence: DimmQRPresent=0
|
|
DIMMPresence: DATAload[0]=0
|
|
DIMMPresence: MAload[0]=0
|
|
DIMMPresence: MAdimms[0]=0
|
|
DIMMPresence: DATAload[1]=0
|
|
DIMMPresence: MAload[1]=0
|
|
DIMMPresence: MAdimms[1]=0
|
|
DIMMPresence: Status 2000
|
|
DIMMPresence: ErrStatus 1
|
|
DIMMPresence: ErrCode 2
|
|
DIMMPresence: Done
|
|
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 's3nv'
|
|
CBFS: Found @ offset 2fec0 size 10000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 's3nv'
|
|
CBFS: Found @ offset 2fec0 size 10000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
mctAutoInitMCT_D: mct_init Node 2
|
|
mctAutoInitMCT_D: mct_init Node 3
|
|
mctAutoInitMCT_D: mct_init Node 4
|
|
mctAutoInitMCT_D: mct_init Node 5
|
|
mctAutoInitMCT_D: mct_init Node 6
|
|
mctAutoInitMCT_D: mct_init Node 7
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
mctAutoInitMCT_D: DIMMSetVoltage
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Node 00 DIMM voltage set to index 00
|
|
mctAutoInitMCT_D: mctSMBhub_Init
|
|
activate_spd_rom() for node 00
|
|
enable_spd_node0()
|
|
mctAutoInitMCT_D: mct_initDCT
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
SPDCalcWidth: Status 2005
|
|
SPDCalcWidth: ErrStatus 0
|
|
SPDCalcWidth: ErrCode 0
|
|
SPDCalcWidth: Done
|
|
DCTInit_D: mct_SPDCalcWidth Done
|
|
AutoCycTiming_D: Start
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
GetPresetmaxF_D: Start
|
|
GetPresetmaxF_D: Done
|
|
SPDGetTCL_D: Start
|
|
SPDGetTCL_D: DIMMCASL 6
|
|
SPDGetTCL_D: DIMMAutoSpeed 4
|
|
SPDGetTCL_D: Status 2005
|
|
SPDGetTCL_D: ErrStatus 0
|
|
SPDGetTCL_D: ErrCode 0
|
|
SPDGetTCL_D: Done
|
|
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
AutoCycTiming: Status 2005
|
|
AutoCycTiming: ErrStatus 0
|
|
AutoCycTiming: ErrCode 0
|
|
AutoCycTiming: Done
|
|
|
|
DCTInit_D: AutoCycTiming_D Done
|
|
SPDSetBanks: CSPresent c
|
|
SPDSetBanks: Status 2005
|
|
SPDSetBanks: ErrStatus 0
|
|
SPDSetBanks: ErrCode 0
|
|
SPDSetBanks: Done
|
|
|
|
AfterStitch pDCTstat->NodeSysBase = 0
|
|
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
|
|
StitchMemory: Status 2005
|
|
StitchMemory: ErrStatus 0
|
|
StitchMemory: ErrCode 0
|
|
StitchMemory: Done
|
|
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
InterleaveBanks_D: Status 2005
|
|
InterleaveBanks_D: ErrStatus 0
|
|
InterleaveBanks_D: ErrCode 0
|
|
InterleaveBanks_D: Done
|
|
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
AutoConfig_D: DramControl: 00002a06
|
|
AutoConfig_D: DramTimingLo: 00000000
|
|
AutoConfig_D: DramConfigMisc: 00000000
|
|
AutoConfig_D: DramConfigMisc2: 00000020
|
|
AutoConfig_D: DramConfigLo: 03082000
|
|
AutoConfig_D: DramConfigHi: 0f090084
|
|
InitDDRPhy: Start
|
|
InitDDRPhy: Done
|
|
mct_SetDramConfigHi_D: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00000000 00112222
|
|
mct_PlatformSpec: Done
|
|
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
|
|
*
|
|
mct_SetDramConfigHi_D: Done
|
|
mct_EarlyArbEn_D: Start
|
|
mct_EarlyArbEn_D: Done
|
|
AutoConfig: Status 2005
|
|
AutoConfig: ErrStatus 0
|
|
AutoConfig: ErrCode 0
|
|
AutoConfig: Done
|
|
|
|
DCTInit_D: AutoConfig_D Done
|
|
DCTInit_D: PlatformSpec_D Done
|
|
DCTFinalInit_D: StartupDCT_D Start
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
mct_DCTAccessDone: Start
|
|
mct_DCTAccessDone: Done
|
|
mct_DramControlReg_Init_D: Start
|
|
mct_DramControlReg_Init_D: F2xA8: 00000c20
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
|
|
mct_DramControlReg_Init_D: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_SendZQCmd: Start
|
|
mct_SendZQCmd: Done
|
|
mct_SendZQCmd: Start
|
|
mct_SendZQCmd: Done
|
|
mct_DCTAccessDone: Start
|
|
mct_DCTAccessDone: Done
|
|
mct_DramInit_Sw_D: Done
|
|
DCTFinalInit_D: StartupDCT_D Done
|
|
SPDCalcWidth: Status 2005
|
|
SPDCalcWidth: ErrStatus 0
|
|
SPDCalcWidth: ErrCode 0
|
|
SPDCalcWidth: Done
|
|
DCTInit_D: mct_SPDCalcWidth Done
|
|
AutoCycTiming_D: Start
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
AutoCycTiming: Status 2005
|
|
AutoCycTiming: ErrStatus 0
|
|
AutoCycTiming: ErrCode 0
|
|
AutoCycTiming: Done
|
|
|
|
DCTInit_D: AutoCycTiming_D Done
|
|
DCTInit_D: enabling intra-channel clock skew
|
|
SPDSetBanks: CSPresent c
|
|
SPDSetBanks: Status 2005
|
|
SPDSetBanks: ErrStatus 0
|
|
SPDSetBanks: ErrCode 0
|
|
SPDSetBanks: Done
|
|
|
|
AfterStitch pDCTstat->NodeSysBase = 0
|
|
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffffe
|
|
StitchMemory: Status 2005
|
|
StitchMemory: ErrStatus 0
|
|
StitchMemory: ErrCode 0
|
|
StitchMemory: Done
|
|
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
InterleaveBanks_D: Status 2005
|
|
InterleaveBanks_D: ErrStatus 0
|
|
InterleaveBanks_D: ErrCode 0
|
|
InterleaveBanks_D: Done
|
|
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
AutoConfig_D: DramControl: 00002a06
|
|
AutoConfig_D: DramTimingLo: 00000000
|
|
AutoConfig_D: DramConfigMisc: 00000000
|
|
AutoConfig_D: DramConfigMisc2: 00000020
|
|
AutoConfig_D: DramConfigLo: 03082000
|
|
AutoConfig_D: DramConfigHi: 0f090084
|
|
InitDDRPhy: Start
|
|
InitDDRPhy: Done
|
|
mct_SetDramConfigHi_D: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00000000 00112222
|
|
mct_PlatformSpec: Done
|
|
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
|
|
*
|
|
mct_SetDramConfigHi_D: Done
|
|
mct_EarlyArbEn_D: Start
|
|
mct_EarlyArbEn_D: Done
|
|
AutoConfig: Status 2005
|
|
AutoConfig: ErrStatus 0
|
|
AutoConfig: ErrCode 0
|
|
AutoConfig: Done
|
|
|
|
DCTInit_D: AutoConfig_D Done
|
|
DCTInit_D: PlatformSpec_D Done
|
|
DCTFinalInit_D: StartupDCT_D Start
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
mct_DCTAccessDone: Start
|
|
mct_DCTAccessDone: Done
|
|
mct_DramControlReg_Init_D: Start
|
|
mct_DramControlReg_Init_D: F2xA8: 00000c20
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
|
|
mct_DramControlReg_Init_D: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_SendZQCmd: Start
|
|
mct_SendZQCmd: Done
|
|
mct_SendZQCmd: Start
|
|
mct_SendZQCmd: Done
|
|
mct_DCTAccessDone: Start
|
|
mct_DCTAccessDone: Done
|
|
mct_DramInit_Sw_D: Done
|
|
DCTFinalInit_D: StartupDCT_D Done
|
|
mctAutoInitMCT_D: mctSMBhub_Init
|
|
activate_spd_rom() for node 01
|
|
enable_spd_node1()
|
|
mctAutoInitMCT_D: mct_initDCT
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
SPDCalcWidth: Status 2000
|
|
SPDCalcWidth: ErrStatus 1
|
|
SPDCalcWidth: ErrCode 2
|
|
SPDCalcWidth: Done
|
|
mctAutoInitMCT_D: SyncDCTsReady_D
|
|
mctAutoInitMCT_D: HTMemMapInit_D
|
|
Node: 00 base: 00 limit: 7ffffff BottomIO: c00000
|
|
Node: 00 base: 03 limit: 83fffff
|
|
Node: 01 base: 00 limit: 00
|
|
Node: 02 base: 00 limit: 00
|
|
Node: 03 base: 00 limit: 00
|
|
Node: 04 base: 00 limit: 00
|
|
Node: 05 base: 00 limit: 00
|
|
Node: 06 base: 00 limit: 00
|
|
Node: 07 base: 00 limit: 00
|
|
Copy dram map from Node 0 to Node 01
|
|
mctAutoInitMCT_D: mctHookAfterCPU
|
|
mctAutoInitMCT_D: DQSTiming_D
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
activate_spd_rom() for node 00
|
|
enable_spd_node0()
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 0 raw readback: 004c
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 004c
|
|
Lane 00 nibble 0 adjusted value (post nibble): 004c
|
|
Lane 01 nibble 0 raw readback: 0048
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0048
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0048
|
|
Lane 02 nibble 0 raw readback: 0045
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 03 nibble 0 raw readback: 0043
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0043
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0043
|
|
Lane 04 nibble 0 raw readback: 003a
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 003a
|
|
Lane 04 nibble 0 adjusted value (post nibble): 003a
|
|
Lane 05 nibble 0 raw readback: 003f
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 003f
|
|
Lane 05 nibble 0 adjusted value (post nibble): 003f
|
|
Lane 06 nibble 0 raw readback: 0040
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0040
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0040
|
|
Lane 07 nibble 0 raw readback: 0044
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0044
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0044
|
|
Lane 08 nibble 0 raw readback: 003c
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 003c
|
|
Lane 08 nibble 0 adjusted value (post nibble): 003c
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 1 raw readback: 004d
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 004d
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0047
|
|
Lane 01 nibble 1 raw readback: 0049
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0049
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0045
|
|
Lane 02 nibble 1 raw readback: 0045
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0043
|
|
Lane 03 nibble 1 raw readback: 0043
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0043
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0042
|
|
Lane 04 nibble 1 raw readback: 003b
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 003b
|
|
Lane 04 nibble 1 adjusted value (post nibble): 003e
|
|
Lane 05 nibble 1 raw readback: 003f
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 003f
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 06 nibble 1 raw readback: 0041
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0041
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 07 nibble 1 raw readback: 0044
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0044
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0042
|
|
Lane 08 nibble 1 raw readback: 003c
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 08 nibble 1 adjusted value (post nibble): 003e
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 0 raw readback: 0040
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0040
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0040
|
|
Lane 01 nibble 0 raw readback: 003d
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 003d
|
|
Lane 01 nibble 0 adjusted value (post nibble): 003d
|
|
Lane 02 nibble 0 raw readback: 0039
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0039
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0039
|
|
Lane 03 nibble 0 raw readback: 0036
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0036
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0036
|
|
Lane 04 nibble 0 raw readback: 002e
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 002e
|
|
Lane 04 nibble 0 adjusted value (post nibble): 002e
|
|
Lane 05 nibble 0 raw readback: 0030
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0030
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0030
|
|
Lane 06 nibble 0 raw readback: 0033
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0033
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0033
|
|
Lane 07 nibble 0 raw readback: 0036
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0036
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0036
|
|
Lane 08 nibble 0 raw readback: 002f
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 002f
|
|
Lane 08 nibble 0 adjusted value (post nibble): 002f
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 1 raw readback: 003f
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 003f
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 01 nibble 1 raw readback: 003c
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 01 nibble 1 adjusted value (post nibble): 003e
|
|
Lane 02 nibble 1 raw readback: 0039
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0039
|
|
Lane 02 nibble 1 adjusted value (post nibble): 003d
|
|
Lane 03 nibble 1 raw readback: 0036
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0036
|
|
Lane 03 nibble 1 adjusted value (post nibble): 003b
|
|
Lane 04 nibble 1 raw readback: 002d
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 002d
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0037
|
|
Lane 05 nibble 1 raw readback: 0031
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0031
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0039
|
|
Lane 06 nibble 1 raw readback: 0033
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0033
|
|
Lane 06 nibble 1 adjusted value (post nibble): 003a
|
|
Lane 07 nibble 1 raw readback: 0037
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0037
|
|
Lane 07 nibble 1 adjusted value (post nibble): 003c
|
|
Lane 08 nibble 1 raw readback: 002f
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 002f
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0038
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
activate_spd_rom() for node 01
|
|
enable_spd_node1()
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
TrainRcvrEn: Status 2205
|
|
TrainRcvrEn: ErrStatus 0
|
|
TrainRcvrEn: ErrCode 0
|
|
TrainRcvrEn: Done
|
|
|
|
activate_spd_rom() for node 00
|
|
enable_spd_node0()
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 0006
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00000000 10112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00000000 10112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0047
|
|
Lane 00 new seed: 0047
|
|
Lane 01 scaled delay: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 scaled delay: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 scaled delay: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 scaled delay: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 scaled delay: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 scaled delay: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 scaled delay: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 scaled delay: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 0 raw readback: 0050
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0050
|
|
Lane 01 nibble 0 raw readback: 004b
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 004b
|
|
Lane 01 nibble 0 adjusted value (post nibble): 004b
|
|
Lane 02 nibble 0 raw readback: 0048
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0048
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0048
|
|
Lane 03 nibble 0 raw readback: 0046
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0046
|
|
Lane 04 nibble 0 raw readback: 003b
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 04 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 05 nibble 0 raw readback: 0040
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0040
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0040
|
|
Lane 06 nibble 0 raw readback: 0041
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0041
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0041
|
|
Lane 07 nibble 0 raw readback: 0046
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0046
|
|
Lane 08 nibble 0 raw readback: 003d
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 003d
|
|
Lane 08 nibble 0 adjusted value (post nibble): 003d
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 1 raw readback: 0050
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0050
|
|
Lane 00 nibble 1 adjusted value (post nibble): 004b
|
|
Lane 01 nibble 1 raw readback: 004b
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 004b
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0049
|
|
Lane 02 nibble 1 raw readback: 0049
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0049
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0048
|
|
Lane 03 nibble 1 raw readback: 0046
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 04 nibble 1 raw readback: 003c
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 05 nibble 1 raw readback: 0040
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0043
|
|
Lane 06 nibble 1 raw readback: 0042
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0042
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 07 nibble 1 raw readback: 0046
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 08 nibble 1 raw readback: 003d
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 003d
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0042
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0047
|
|
Lane 00 new seed: 0047
|
|
Lane 01 scaled delay: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 scaled delay: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 scaled delay: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 scaled delay: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 scaled delay: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 scaled delay: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 scaled delay: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 scaled delay: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 0 raw readback: 0045
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 01 nibble 0 raw readback: 0042
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0042
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0042
|
|
Lane 02 nibble 0 raw readback: 003e
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 003e
|
|
Lane 02 nibble 0 adjusted value (post nibble): 003e
|
|
Lane 03 nibble 0 raw readback: 003b
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 03 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 04 nibble 0 raw readback: 0031
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0031
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0031
|
|
Lane 05 nibble 0 raw readback: 0035
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0035
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0035
|
|
Lane 06 nibble 0 raw readback: 0037
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0037
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0037
|
|
Lane 07 nibble 0 raw readback: 003a
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 003a
|
|
Lane 07 nibble 0 adjusted value (post nibble): 003a
|
|
Lane 08 nibble 0 raw readback: 0033
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0033
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0033
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 1 raw readback: 0045
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 01 nibble 1 raw readback: 0041
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0041
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 02 nibble 1 raw readback: 003e
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 003e
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0042
|
|
Lane 03 nibble 1 raw readback: 003c
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 04 nibble 1 raw readback: 0030
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0030
|
|
Lane 04 nibble 1 adjusted value (post nibble): 003b
|
|
Lane 05 nibble 1 raw readback: 0035
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0035
|
|
Lane 05 nibble 1 adjusted value (post nibble): 003e
|
|
Lane 06 nibble 1 raw readback: 0037
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0037
|
|
Lane 06 nibble 1 adjusted value (post nibble): 003f
|
|
Lane 07 nibble 1 raw readback: 003a
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 003a
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 08 nibble 1 raw readback: 0032
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0032
|
|
Lane 08 nibble 1 adjusted value (post nibble): 003c
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 000a
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00393c39 20112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00393c39 20112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0059
|
|
Lane 00 new seed: 0059
|
|
Lane 01 scaled delay: 0056
|
|
Lane 01 new seed: 0056
|
|
Lane 02 scaled delay: 0055
|
|
Lane 02 new seed: 0055
|
|
Lane 03 scaled delay: 0052
|
|
Lane 03 new seed: 0052
|
|
Lane 04 scaled delay: 004b
|
|
Lane 04 new seed: 004b
|
|
Lane 05 scaled delay: 004e
|
|
Lane 05 new seed: 004e
|
|
Lane 06 scaled delay: 004f
|
|
Lane 06 new seed: 004f
|
|
Lane 07 scaled delay: 0052
|
|
Lane 07 new seed: 0052
|
|
Lane 08 scaled delay: 004d
|
|
Lane 08 new seed: 004d
|
|
Lane 00 nibble 0 raw readback: 0061
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0061
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0061
|
|
Lane 01 nibble 0 raw readback: 0058
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0058
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0058
|
|
Lane 02 nibble 0 raw readback: 0055
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0055
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0055
|
|
Lane 03 nibble 0 raw readback: 0052
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0052
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0052
|
|
Lane 04 nibble 0 raw readback: 0045
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 05 nibble 0 raw readback: 004b
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 004b
|
|
Lane 05 nibble 0 adjusted value (post nibble): 004b
|
|
Lane 06 nibble 0 raw readback: 004e
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 06 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 07 nibble 0 raw readback: 0053
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0053
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0053
|
|
Lane 08 nibble 0 raw readback: 0046
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0046
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0059
|
|
Lane 01 new seed: 0056
|
|
Lane 02 new seed: 0055
|
|
Lane 03 new seed: 0052
|
|
Lane 04 new seed: 004b
|
|
Lane 05 new seed: 004e
|
|
Lane 06 new seed: 004f
|
|
Lane 07 new seed: 0052
|
|
Lane 08 new seed: 004d
|
|
Lane 00 nibble 1 raw readback: 0060
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0060
|
|
Lane 00 nibble 1 adjusted value (post nibble): 005c
|
|
Lane 01 nibble 1 raw readback: 0059
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0057
|
|
Lane 02 nibble 1 raw readback: 0055
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0055
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0055
|
|
Lane 03 nibble 1 raw readback: 0054
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0054
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0053
|
|
Lane 04 nibble 1 raw readback: 0046
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0048
|
|
Lane 05 nibble 1 raw readback: 004b
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 004b
|
|
Lane 05 nibble 1 adjusted value (post nibble): 004c
|
|
Lane 06 nibble 1 raw readback: 004e
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 004e
|
|
Lane 06 nibble 1 adjusted value (post nibble): 004e
|
|
Lane 07 nibble 1 raw readback: 0053
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0053
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0052
|
|
Lane 08 nibble 1 raw readback: 0046
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0049
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0052
|
|
Lane 00 new seed: 0052
|
|
Lane 01 scaled delay: 004f
|
|
Lane 01 new seed: 004f
|
|
Lane 02 scaled delay: 004d
|
|
Lane 02 new seed: 004d
|
|
Lane 03 scaled delay: 004b
|
|
Lane 03 new seed: 004b
|
|
Lane 04 scaled delay: 0043
|
|
Lane 04 new seed: 0043
|
|
Lane 05 scaled delay: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 scaled delay: 0049
|
|
Lane 06 new seed: 0049
|
|
Lane 07 scaled delay: 004a
|
|
Lane 07 new seed: 004a
|
|
Lane 08 scaled delay: 0045
|
|
Lane 08 new seed: 0045
|
|
Lane 00 nibble 0 raw readback: 0052
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0052
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0052
|
|
Lane 01 nibble 0 raw readback: 004e
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 01 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 02 nibble 0 raw readback: 0049
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0049
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0049
|
|
Lane 03 nibble 0 raw readback: 0046
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0046
|
|
Lane 04 nibble 0 raw readback: 0038
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0038
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0038
|
|
Lane 05 nibble 0 raw readback: 003b
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 05 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 06 nibble 0 raw readback: 003f
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 003f
|
|
Lane 06 nibble 0 adjusted value (post nibble): 003f
|
|
Lane 07 nibble 0 raw readback: 0044
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0044
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0044
|
|
Lane 08 nibble 0 raw readback: 003a
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 003a
|
|
Lane 08 nibble 0 adjusted value (post nibble): 003a
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0052
|
|
Lane 01 new seed: 004f
|
|
Lane 02 new seed: 004d
|
|
Lane 03 new seed: 004b
|
|
Lane 04 new seed: 0043
|
|
Lane 05 new seed: 0047
|
|
Lane 06 new seed: 0049
|
|
Lane 07 new seed: 004a
|
|
Lane 08 new seed: 0045
|
|
Lane 00 nibble 1 raw readback: 0053
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0053
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0052
|
|
Lane 01 nibble 1 raw readback: 004d
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 004d
|
|
Lane 01 nibble 1 adjusted value (post nibble): 004e
|
|
Lane 02 nibble 1 raw readback: 0049
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0049
|
|
Lane 02 nibble 1 adjusted value (post nibble): 004b
|
|
Lane 03 nibble 1 raw readback: 0046
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0048
|
|
Lane 04 nibble 1 raw readback: 0037
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0037
|
|
Lane 04 nibble 1 adjusted value (post nibble): 003d
|
|
Lane 05 nibble 1 raw readback: 003c
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 06 nibble 1 raw readback: 0040
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 07 nibble 1 raw readback: 0044
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0044
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0047
|
|
Lane 08 nibble 1 raw readback: 003a
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 003a
|
|
Lane 08 nibble 1 adjusted value (post nibble): 003f
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 000e
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00373a37 30112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00373a37 30112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 006b
|
|
Lane 00 new seed: 006b
|
|
Lane 01 scaled delay: 0064
|
|
Lane 01 new seed: 0064
|
|
Lane 02 scaled delay: 0062
|
|
Lane 02 new seed: 0062
|
|
Lane 03 scaled delay: 005f
|
|
Lane 03 new seed: 005f
|
|
Lane 04 scaled delay: 0052
|
|
Lane 04 new seed: 0052
|
|
Lane 05 scaled delay: 0057
|
|
Lane 05 new seed: 0057
|
|
Lane 06 scaled delay: 0059
|
|
Lane 06 new seed: 0059
|
|
Lane 07 scaled delay: 005e
|
|
Lane 07 new seed: 005e
|
|
Lane 08 scaled delay: 0053
|
|
Lane 08 new seed: 0053
|
|
Lane 00 nibble 0 raw readback: 0030
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0070
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0070
|
|
Lane 01 nibble 0 raw readback: 0027
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0067
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0067
|
|
Lane 02 nibble 0 raw readback: 0023
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0063
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0063
|
|
Lane 03 nibble 0 raw readback: 005f
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 03 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 04 nibble 0 raw readback: 004e
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 04 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 05 nibble 0 raw readback: 0056
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0056
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0056
|
|
Lane 06 nibble 0 raw readback: 0059
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0059
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0059
|
|
Lane 07 nibble 0 raw readback: 005f
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 07 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 08 nibble 0 raw readback: 004f
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 004f
|
|
Lane 08 nibble 0 adjusted value (post nibble): 004f
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 006b
|
|
Lane 01 new seed: 0064
|
|
Lane 02 new seed: 0062
|
|
Lane 03 new seed: 005f
|
|
Lane 04 new seed: 0052
|
|
Lane 05 new seed: 0057
|
|
Lane 06 new seed: 0059
|
|
Lane 07 new seed: 005e
|
|
Lane 08 new seed: 0053
|
|
Lane 00 nibble 1 raw readback: 0030
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0070
|
|
Lane 00 nibble 1 adjusted value (post nibble): 006d
|
|
Lane 01 nibble 1 raw readback: 0027
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0067
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0065
|
|
Lane 02 nibble 1 raw readback: 0023
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0063
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0062
|
|
Lane 03 nibble 1 raw readback: 005f
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 005f
|
|
Lane 03 nibble 1 adjusted value (post nibble): 005f
|
|
Lane 04 nibble 1 raw readback: 004e
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 004e
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0050
|
|
Lane 05 nibble 1 raw readback: 0054
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0054
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0055
|
|
Lane 06 nibble 1 raw readback: 0058
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0058
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0058
|
|
Lane 07 nibble 1 raw readback: 005f
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 005f
|
|
Lane 07 nibble 1 adjusted value (post nibble): 005e
|
|
Lane 08 nibble 1 raw readback: 004e
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 004e
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0050
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 005e
|
|
Lane 00 new seed: 005e
|
|
Lane 01 scaled delay: 0059
|
|
Lane 01 new seed: 0059
|
|
Lane 02 scaled delay: 0055
|
|
Lane 02 new seed: 0055
|
|
Lane 03 scaled delay: 0052
|
|
Lane 03 new seed: 0052
|
|
Lane 04 scaled delay: 0044
|
|
Lane 04 new seed: 0044
|
|
Lane 05 scaled delay: 0049
|
|
Lane 05 new seed: 0049
|
|
Lane 06 scaled delay: 004d
|
|
Lane 06 new seed: 004d
|
|
Lane 07 scaled delay: 0050
|
|
Lane 07 new seed: 0050
|
|
Lane 08 scaled delay: 0046
|
|
Lane 08 new seed: 0046
|
|
Lane 00 nibble 0 raw readback: 005f
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 00 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 01 nibble 0 raw readback: 005a
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 005a
|
|
Lane 01 nibble 0 adjusted value (post nibble): 005a
|
|
Lane 02 nibble 0 raw readback: 0055
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0055
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0055
|
|
Lane 03 nibble 0 raw readback: 0050
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0050
|
|
Lane 04 nibble 0 raw readback: 003f
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 003f
|
|
Lane 04 nibble 0 adjusted value (post nibble): 003f
|
|
Lane 05 nibble 0 raw readback: 0044
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0044
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0044
|
|
Lane 06 nibble 0 raw readback: 0049
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0049
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0049
|
|
Lane 07 nibble 0 raw readback: 004e
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 07 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 08 nibble 0 raw readback: 0042
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0042
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0042
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 005e
|
|
Lane 01 new seed: 0059
|
|
Lane 02 new seed: 0055
|
|
Lane 03 new seed: 0052
|
|
Lane 04 new seed: 0044
|
|
Lane 05 new seed: 0049
|
|
Lane 06 new seed: 004d
|
|
Lane 07 new seed: 0050
|
|
Lane 08 new seed: 0046
|
|
Lane 00 nibble 1 raw readback: 005f
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 005f
|
|
Lane 00 nibble 1 adjusted value (post nibble): 005e
|
|
Lane 01 nibble 1 raw readback: 0059
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0059
|
|
Lane 02 nibble 1 raw readback: 0053
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0053
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0054
|
|
Lane 03 nibble 1 raw readback: 004f
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 004f
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0050
|
|
Lane 04 nibble 1 raw readback: 003d
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 003d
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 05 nibble 1 raw readback: 0045
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0047
|
|
Lane 06 nibble 1 raw readback: 0048
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0048
|
|
Lane 06 nibble 1 adjusted value (post nibble): 004a
|
|
Lane 07 nibble 1 raw readback: 004e
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 004e
|
|
Lane 07 nibble 1 adjusted value (post nibble): 004f
|
|
Lane 08 nibble 1 raw readback: 0040
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0043
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 0012
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00363936 30112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00363936 30112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 007c
|
|
Lane 00 new seed: 007c
|
|
Lane 01 scaled delay: 0072
|
|
Lane 01 new seed: 0072
|
|
Lane 02 scaled delay: 006f
|
|
Lane 02 new seed: 006f
|
|
Lane 03 scaled delay: 006b
|
|
Lane 03 new seed: 006b
|
|
Lane 04 scaled delay: 0059
|
|
Lane 04 new seed: 0059
|
|
Lane 05 scaled delay: 005f
|
|
Lane 05 new seed: 005f
|
|
Lane 06 scaled delay: 0063
|
|
Lane 06 new seed: 0063
|
|
Lane 07 scaled delay: 006a
|
|
Lane 07 new seed: 006a
|
|
Lane 08 scaled delay: 0059
|
|
Lane 08 new seed: 0059
|
|
Lane 00 nibble 0 raw readback: 0043
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0083
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0083
|
|
Lane 01 nibble 0 raw readback: 0037
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0077
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0077
|
|
Lane 02 nibble 0 raw readback: 0032
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0072
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0072
|
|
Lane 03 nibble 0 raw readback: 002d
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 006d
|
|
Lane 03 nibble 0 adjusted value (post nibble): 006d
|
|
Lane 04 nibble 0 raw readback: 0059
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0059
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0059
|
|
Lane 05 nibble 0 raw readback: 0062
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0062
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0062
|
|
Lane 06 nibble 0 raw readback: 0027
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0067
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0067
|
|
Lane 07 nibble 0 raw readback: 002d
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 006d
|
|
Lane 07 nibble 0 adjusted value (post nibble): 006d
|
|
Lane 08 nibble 0 raw readback: 005b
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 005b
|
|
Lane 08 nibble 0 adjusted value (post nibble): 005b
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 007c
|
|
Lane 01 new seed: 0072
|
|
Lane 02 new seed: 006f
|
|
Lane 03 new seed: 006b
|
|
Lane 04 new seed: 0059
|
|
Lane 05 new seed: 005f
|
|
Lane 06 new seed: 0063
|
|
Lane 07 new seed: 006a
|
|
Lane 08 new seed: 0059
|
|
Lane 00 nibble 1 raw readback: 0042
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0082
|
|
Lane 00 nibble 1 adjusted value (post nibble): 007f
|
|
Lane 01 nibble 1 raw readback: 0038
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0078
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0075
|
|
Lane 02 nibble 1 raw readback: 0033
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0073
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0071
|
|
Lane 03 nibble 1 raw readback: 002e
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 006e
|
|
Lane 03 nibble 1 adjusted value (post nibble): 006c
|
|
Lane 04 nibble 1 raw readback: 005a
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 005a
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0059
|
|
Lane 05 nibble 1 raw readback: 0062
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0062
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0060
|
|
Lane 06 nibble 1 raw readback: 0027
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0067
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0065
|
|
Lane 07 nibble 1 raw readback: 002e
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 006e
|
|
Lane 07 nibble 1 adjusted value (post nibble): 006c
|
|
Lane 08 nibble 1 raw readback: 005b
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 005b
|
|
Lane 08 nibble 1 adjusted value (post nibble): 005a
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 006a
|
|
Lane 00 new seed: 006a
|
|
Lane 01 scaled delay: 0064
|
|
Lane 01 new seed: 0064
|
|
Lane 02 scaled delay: 005e
|
|
Lane 02 new seed: 005e
|
|
Lane 03 scaled delay: 0059
|
|
Lane 03 new seed: 0059
|
|
Lane 04 scaled delay: 0046
|
|
Lane 04 new seed: 0046
|
|
Lane 05 scaled delay: 004e
|
|
Lane 05 new seed: 004e
|
|
Lane 06 scaled delay: 0052
|
|
Lane 06 new seed: 0052
|
|
Lane 07 scaled delay: 0058
|
|
Lane 07 new seed: 0058
|
|
Lane 08 scaled delay: 0049
|
|
Lane 08 new seed: 0049
|
|
Lane 00 nibble 0 raw readback: 002d
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 006d
|
|
Lane 00 nibble 0 adjusted value (post nibble): 006d
|
|
Lane 01 nibble 0 raw readback: 0025
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0065
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0065
|
|
Lane 02 nibble 0 raw readback: 005f
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 02 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 03 nibble 0 raw readback: 005a
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 005a
|
|
Lane 03 nibble 0 adjusted value (post nibble): 005a
|
|
Lane 04 nibble 0 raw readback: 0046
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0046
|
|
Lane 05 nibble 0 raw readback: 004b
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 004b
|
|
Lane 05 nibble 0 adjusted value (post nibble): 004b
|
|
Lane 06 nibble 0 raw readback: 0050
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0050
|
|
Lane 07 nibble 0 raw readback: 0058
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0058
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0058
|
|
Lane 08 nibble 0 raw readback: 0048
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0048
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0048
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 006a
|
|
Lane 01 new seed: 0064
|
|
Lane 02 new seed: 005e
|
|
Lane 03 new seed: 0059
|
|
Lane 04 new seed: 0046
|
|
Lane 05 new seed: 004e
|
|
Lane 06 new seed: 0052
|
|
Lane 07 new seed: 0058
|
|
Lane 08 new seed: 0049
|
|
Lane 00 nibble 1 raw readback: 002c
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 006c
|
|
Lane 00 nibble 1 adjusted value (post nibble): 006b
|
|
Lane 01 nibble 1 raw readback: 0024
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0064
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0064
|
|
Lane 02 nibble 1 raw readback: 005d
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 005d
|
|
Lane 02 nibble 1 adjusted value (post nibble): 005d
|
|
Lane 03 nibble 1 raw readback: 0059
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0059
|
|
Lane 04 nibble 1 raw readback: 0043
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0043
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 05 nibble 1 raw readback: 004d
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 004d
|
|
Lane 05 nibble 1 adjusted value (post nibble): 004d
|
|
Lane 06 nibble 1 raw readback: 004f
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 004f
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0050
|
|
Lane 07 nibble 1 raw readback: 0058
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0058
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0058
|
|
Lane 08 nibble 1 raw readback: 0048
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0048
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0048
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
activate_spd_rom() for node 01
|
|
enable_spd_node1()
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
TrainRcvrEn: Status 2205
|
|
TrainRcvrEn: ErrStatus 0
|
|
TrainRcvrEn: ErrCode 0
|
|
TrainRcvrEn: Done
|
|
|
|
TrainDQSReceiverEnCyc: Status 2205
|
|
TrainDQSReceiverEnCyc: TrainErrors 24000
|
|
TrainDQSReceiverEnCyc: ErrStatus 24000
|
|
TrainDQSReceiverEnCyc: ErrCode 0
|
|
TrainDQSReceiverEnCyc: Done
|
|
|
|
DQSTiming_D: Restarting training on algorithm request
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 0004
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00000000 00112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00000000 00112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 1: New frequency code: 0004
|
|
ChangeMemClk: Start
|
|
ChangeMemClk: Done
|
|
SetTargetFreq: Done
|
|
AutoCycTiming_D: Start
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
AutoCycTiming: Status 2205
|
|
AutoCycTiming: ErrStatus 0
|
|
AutoCycTiming: ErrCode 0
|
|
AutoCycTiming: Done
|
|
|
|
AutoCycTiming_D: Start
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
AutoCycTiming: Status 2205
|
|
AutoCycTiming: ErrStatus 0
|
|
AutoCycTiming: ErrCode 0
|
|
AutoCycTiming: Done
|
|
|
|
AutoCycTiming_D: Start
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
AutoCycTiming: Status 2000
|
|
AutoCycTiming: ErrStatus 1
|
|
AutoCycTiming: ErrCode 2
|
|
AutoCycTiming: Done
|
|
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
activate_spd_rom() for node 00
|
|
enable_spd_node0()
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 0 raw readback: 004d
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 004d
|
|
Lane 00 nibble 0 adjusted value (post nibble): 004d
|
|
Lane 01 nibble 0 raw readback: 0047
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0047
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0047
|
|
Lane 02 nibble 0 raw readback: 0045
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 03 nibble 0 raw readback: 0043
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0043
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0043
|
|
Lane 04 nibble 0 raw readback: 003b
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 04 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 05 nibble 0 raw readback: 003e
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 003e
|
|
Lane 05 nibble 0 adjusted value (post nibble): 003e
|
|
Lane 06 nibble 0 raw readback: 0040
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0040
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0040
|
|
Lane 07 nibble 0 raw readback: 0044
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0044
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0044
|
|
Lane 08 nibble 0 raw readback: 003c
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 003c
|
|
Lane 08 nibble 0 adjusted value (post nibble): 003c
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 1 raw readback: 004c
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 004c
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 01 nibble 1 raw readback: 0049
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0049
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0045
|
|
Lane 02 nibble 1 raw readback: 0045
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0043
|
|
Lane 03 nibble 1 raw readback: 0044
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0044
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0042
|
|
Lane 04 nibble 1 raw readback: 003b
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 003b
|
|
Lane 04 nibble 1 adjusted value (post nibble): 003e
|
|
Lane 05 nibble 1 raw readback: 003e
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 003e
|
|
Lane 05 nibble 1 adjusted value (post nibble): 003f
|
|
Lane 06 nibble 1 raw readback: 0040
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 07 nibble 1 raw readback: 0043
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0043
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0042
|
|
Lane 08 nibble 1 raw readback: 003c
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 08 nibble 1 adjusted value (post nibble): 003e
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 0 raw readback: 003f
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 003f
|
|
Lane 00 nibble 0 adjusted value (post nibble): 003f
|
|
Lane 01 nibble 0 raw readback: 003c
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 003c
|
|
Lane 01 nibble 0 adjusted value (post nibble): 003c
|
|
Lane 02 nibble 0 raw readback: 0039
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0039
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0039
|
|
Lane 03 nibble 0 raw readback: 0037
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0037
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0037
|
|
Lane 04 nibble 0 raw readback: 002f
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 002f
|
|
Lane 04 nibble 0 adjusted value (post nibble): 002f
|
|
Lane 05 nibble 0 raw readback: 0031
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0031
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0031
|
|
Lane 06 nibble 0 raw readback: 0033
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0033
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0033
|
|
Lane 07 nibble 0 raw readback: 0036
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0036
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0036
|
|
Lane 08 nibble 0 raw readback: 0030
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0030
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0030
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 initial seed: 0041
|
|
Lane 01 initial seed: 0041
|
|
Lane 02 initial seed: 0041
|
|
Lane 03 initial seed: 0041
|
|
Lane 04 initial seed: 0041
|
|
Lane 05 initial seed: 0041
|
|
Lane 06 initial seed: 0041
|
|
Lane 07 initial seed: 0041
|
|
Lane 08 initial seed: 0041
|
|
Lane 00 nibble 1 raw readback: 003f
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 003f
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 01 nibble 1 raw readback: 003b
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 003b
|
|
Lane 01 nibble 1 adjusted value (post nibble): 003e
|
|
Lane 02 nibble 1 raw readback: 0039
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0039
|
|
Lane 02 nibble 1 adjusted value (post nibble): 003d
|
|
Lane 03 nibble 1 raw readback: 0036
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0036
|
|
Lane 03 nibble 1 adjusted value (post nibble): 003b
|
|
Lane 04 nibble 1 raw readback: 002d
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 002d
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0037
|
|
Lane 05 nibble 1 raw readback: 0031
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0031
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0039
|
|
Lane 06 nibble 1 raw readback: 0033
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0033
|
|
Lane 06 nibble 1 adjusted value (post nibble): 003a
|
|
Lane 07 nibble 1 raw readback: 0037
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0037
|
|
Lane 07 nibble 1 adjusted value (post nibble): 003c
|
|
Lane 08 nibble 1 raw readback: 002f
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 002f
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0038
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
activate_spd_rom() for node 01
|
|
enable_spd_node1()
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
TrainRcvrEn: Status 2205
|
|
TrainRcvrEn: ErrStatus 0
|
|
TrainRcvrEn: ErrCode 0
|
|
TrainRcvrEn: Done
|
|
|
|
activate_spd_rom() for node 00
|
|
enable_spd_node0()
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 0006
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00000000 10112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00000000 10112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0047
|
|
Lane 00 new seed: 0047
|
|
Lane 01 scaled delay: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 scaled delay: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 scaled delay: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 scaled delay: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 scaled delay: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 scaled delay: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 scaled delay: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 scaled delay: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 0 raw readback: 0050
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0050
|
|
Lane 01 nibble 0 raw readback: 004a
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 004a
|
|
Lane 01 nibble 0 adjusted value (post nibble): 004a
|
|
Lane 02 nibble 0 raw readback: 0048
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0048
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0048
|
|
Lane 03 nibble 0 raw readback: 0045
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 04 nibble 0 raw readback: 003b
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 04 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 05 nibble 0 raw readback: 0040
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0040
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0040
|
|
Lane 06 nibble 0 raw readback: 0041
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0041
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0041
|
|
Lane 07 nibble 0 raw readback: 0045
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 08 nibble 0 raw readback: 003d
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 003d
|
|
Lane 08 nibble 0 adjusted value (post nibble): 003d
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 1 raw readback: 0050
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0050
|
|
Lane 00 nibble 1 adjusted value (post nibble): 004b
|
|
Lane 01 nibble 1 raw readback: 004b
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 004b
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0049
|
|
Lane 02 nibble 1 raw readback: 0048
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0048
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0047
|
|
Lane 03 nibble 1 raw readback: 0047
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0047
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0047
|
|
Lane 04 nibble 1 raw readback: 003c
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 003c
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 05 nibble 1 raw readback: 0040
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0043
|
|
Lane 06 nibble 1 raw readback: 0042
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0042
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 07 nibble 1 raw readback: 0046
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 08 nibble 1 raw readback: 003d
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 003d
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0042
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0047
|
|
Lane 00 new seed: 0047
|
|
Lane 01 scaled delay: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 scaled delay: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 scaled delay: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 scaled delay: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 scaled delay: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 scaled delay: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 scaled delay: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 scaled delay: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 0 raw readback: 0045
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 01 nibble 0 raw readback: 0041
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0041
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0041
|
|
Lane 02 nibble 0 raw readback: 003e
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 003e
|
|
Lane 02 nibble 0 adjusted value (post nibble): 003e
|
|
Lane 03 nibble 0 raw readback: 003b
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 03 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 04 nibble 0 raw readback: 0032
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0032
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0032
|
|
Lane 05 nibble 0 raw readback: 0034
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0034
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0034
|
|
Lane 06 nibble 0 raw readback: 0037
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0037
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0037
|
|
Lane 07 nibble 0 raw readback: 003a
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 003a
|
|
Lane 07 nibble 0 adjusted value (post nibble): 003a
|
|
Lane 08 nibble 0 raw readback: 0032
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0032
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0032
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0047
|
|
Lane 01 new seed: 0047
|
|
Lane 02 new seed: 0047
|
|
Lane 03 new seed: 0047
|
|
Lane 04 new seed: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 new seed: 0047
|
|
Lane 07 new seed: 0047
|
|
Lane 08 new seed: 0047
|
|
Lane 00 nibble 1 raw readback: 0045
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 01 nibble 1 raw readback: 0040
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0043
|
|
Lane 02 nibble 1 raw readback: 003e
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 003e
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0042
|
|
Lane 03 nibble 1 raw readback: 003b
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 003b
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 04 nibble 1 raw readback: 0030
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0030
|
|
Lane 04 nibble 1 adjusted value (post nibble): 003b
|
|
Lane 05 nibble 1 raw readback: 0035
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0035
|
|
Lane 05 nibble 1 adjusted value (post nibble): 003e
|
|
Lane 06 nibble 1 raw readback: 0037
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0037
|
|
Lane 06 nibble 1 adjusted value (post nibble): 003f
|
|
Lane 07 nibble 1 raw readback: 003a
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 003a
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 08 nibble 1 raw readback: 0033
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0033
|
|
Lane 08 nibble 1 adjusted value (post nibble): 003d
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
|
|
DIMM 1 RttNom: 2
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
|
|
DIMM 1 RttWr: 0
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 000a
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00393c39 20112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00393c39 20112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0059
|
|
Lane 00 new seed: 0059
|
|
Lane 01 scaled delay: 0056
|
|
Lane 01 new seed: 0056
|
|
Lane 02 scaled delay: 0053
|
|
Lane 02 new seed: 0053
|
|
Lane 03 scaled delay: 0053
|
|
Lane 03 new seed: 0053
|
|
Lane 04 scaled delay: 004b
|
|
Lane 04 new seed: 004b
|
|
Lane 05 scaled delay: 004e
|
|
Lane 05 new seed: 004e
|
|
Lane 06 scaled delay: 004f
|
|
Lane 06 new seed: 004f
|
|
Lane 07 scaled delay: 0052
|
|
Lane 07 new seed: 0052
|
|
Lane 08 scaled delay: 004d
|
|
Lane 08 new seed: 004d
|
|
Lane 00 nibble 0 raw readback: 0061
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0061
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0061
|
|
Lane 01 nibble 0 raw readback: 0059
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0059
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0059
|
|
Lane 02 nibble 0 raw readback: 0056
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0056
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0056
|
|
Lane 03 nibble 0 raw readback: 0053
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0053
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0053
|
|
Lane 04 nibble 0 raw readback: 0046
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0046
|
|
Lane 05 nibble 0 raw readback: 004c
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 004c
|
|
Lane 05 nibble 0 adjusted value (post nibble): 004c
|
|
Lane 06 nibble 0 raw readback: 004e
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 06 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 07 nibble 0 raw readback: 0053
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0053
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0053
|
|
Lane 08 nibble 0 raw readback: 0048
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0048
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0048
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0059
|
|
Lane 01 new seed: 0056
|
|
Lane 02 new seed: 0053
|
|
Lane 03 new seed: 0053
|
|
Lane 04 new seed: 004b
|
|
Lane 05 new seed: 004e
|
|
Lane 06 new seed: 004f
|
|
Lane 07 new seed: 0052
|
|
Lane 08 new seed: 004d
|
|
Lane 00 nibble 1 raw readback: 0060
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0060
|
|
Lane 00 nibble 1 adjusted value (post nibble): 005c
|
|
Lane 01 nibble 1 raw readback: 0059
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0057
|
|
Lane 02 nibble 1 raw readback: 0055
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0055
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0054
|
|
Lane 03 nibble 1 raw readback: 0053
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0053
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0053
|
|
Lane 04 nibble 1 raw readback: 0045
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0048
|
|
Lane 05 nibble 1 raw readback: 004a
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 004a
|
|
Lane 05 nibble 1 adjusted value (post nibble): 004c
|
|
Lane 06 nibble 1 raw readback: 004d
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 004d
|
|
Lane 06 nibble 1 adjusted value (post nibble): 004e
|
|
Lane 07 nibble 1 raw readback: 0053
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0053
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0052
|
|
Lane 08 nibble 1 raw readback: 0046
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0049
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 0052
|
|
Lane 00 new seed: 0052
|
|
Lane 01 scaled delay: 004e
|
|
Lane 01 new seed: 004e
|
|
Lane 02 scaled delay: 004d
|
|
Lane 02 new seed: 004d
|
|
Lane 03 scaled delay: 004b
|
|
Lane 03 new seed: 004b
|
|
Lane 04 scaled delay: 0043
|
|
Lane 04 new seed: 0043
|
|
Lane 05 scaled delay: 0047
|
|
Lane 05 new seed: 0047
|
|
Lane 06 scaled delay: 0049
|
|
Lane 06 new seed: 0049
|
|
Lane 07 scaled delay: 004a
|
|
Lane 07 new seed: 004a
|
|
Lane 08 scaled delay: 0046
|
|
Lane 08 new seed: 0046
|
|
Lane 00 nibble 0 raw readback: 0052
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0052
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0052
|
|
Lane 01 nibble 0 raw readback: 004e
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 01 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 02 nibble 0 raw readback: 004a
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 004a
|
|
Lane 02 nibble 0 adjusted value (post nibble): 004a
|
|
Lane 03 nibble 0 raw readback: 0046
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0046
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0046
|
|
Lane 04 nibble 0 raw readback: 0038
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0038
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0038
|
|
Lane 05 nibble 0 raw readback: 003b
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 05 nibble 0 adjusted value (post nibble): 003b
|
|
Lane 06 nibble 0 raw readback: 0040
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0040
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0040
|
|
Lane 07 nibble 0 raw readback: 0044
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0044
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0044
|
|
Lane 08 nibble 0 raw readback: 003b
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 003b
|
|
Lane 08 nibble 0 adjusted value (post nibble): 003b
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 0052
|
|
Lane 01 new seed: 004e
|
|
Lane 02 new seed: 004d
|
|
Lane 03 new seed: 004b
|
|
Lane 04 new seed: 0043
|
|
Lane 05 new seed: 0047
|
|
Lane 06 new seed: 0049
|
|
Lane 07 new seed: 004a
|
|
Lane 08 new seed: 0046
|
|
Lane 00 nibble 1 raw readback: 0052
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0052
|
|
Lane 00 nibble 1 adjusted value (post nibble): 0052
|
|
Lane 01 nibble 1 raw readback: 004d
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 004d
|
|
Lane 01 nibble 1 adjusted value (post nibble): 004d
|
|
Lane 02 nibble 1 raw readback: 0049
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0049
|
|
Lane 02 nibble 1 adjusted value (post nibble): 004b
|
|
Lane 03 nibble 1 raw readback: 0046
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0046
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0048
|
|
Lane 04 nibble 1 raw readback: 0036
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0036
|
|
Lane 04 nibble 1 adjusted value (post nibble): 003c
|
|
Lane 05 nibble 1 raw readback: 003b
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 003b
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0041
|
|
Lane 06 nibble 1 raw readback: 0040
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 07 nibble 1 raw readback: 0045
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0045
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0047
|
|
Lane 08 nibble 1 raw readback: 003a
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 003a
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0040
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
|
|
DIMM 1 RttWr: 0
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 000e
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00373a37 30112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00373a37 30112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 006b
|
|
Lane 00 new seed: 006b
|
|
Lane 01 scaled delay: 0064
|
|
Lane 01 new seed: 0064
|
|
Lane 02 scaled delay: 0061
|
|
Lane 02 new seed: 0061
|
|
Lane 03 scaled delay: 005f
|
|
Lane 03 new seed: 005f
|
|
Lane 04 scaled delay: 0052
|
|
Lane 04 new seed: 0052
|
|
Lane 05 scaled delay: 0057
|
|
Lane 05 new seed: 0057
|
|
Lane 06 scaled delay: 0059
|
|
Lane 06 new seed: 0059
|
|
Lane 07 scaled delay: 005e
|
|
Lane 07 new seed: 005e
|
|
Lane 08 scaled delay: 0053
|
|
Lane 08 new seed: 0053
|
|
Lane 00 nibble 0 raw readback: 0030
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0070
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0070
|
|
Lane 01 nibble 0 raw readback: 0026
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0066
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0066
|
|
Lane 02 nibble 0 raw readback: 0023
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0063
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0063
|
|
Lane 03 nibble 0 raw readback: 005f
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 03 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 04 nibble 0 raw readback: 004e
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 04 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 05 nibble 0 raw readback: 0056
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0056
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0056
|
|
Lane 06 nibble 0 raw readback: 0059
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0059
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0059
|
|
Lane 07 nibble 0 raw readback: 005f
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 07 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 08 nibble 0 raw readback: 0050
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0050
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 006b
|
|
Lane 01 new seed: 0064
|
|
Lane 02 new seed: 0061
|
|
Lane 03 new seed: 005f
|
|
Lane 04 new seed: 0052
|
|
Lane 05 new seed: 0057
|
|
Lane 06 new seed: 0059
|
|
Lane 07 new seed: 005e
|
|
Lane 08 new seed: 0053
|
|
Lane 00 nibble 1 raw readback: 0030
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0070
|
|
Lane 00 nibble 1 adjusted value (post nibble): 006d
|
|
Lane 01 nibble 1 raw readback: 0028
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0068
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0066
|
|
Lane 02 nibble 1 raw readback: 0023
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0063
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0062
|
|
Lane 03 nibble 1 raw readback: 005f
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 005f
|
|
Lane 03 nibble 1 adjusted value (post nibble): 005f
|
|
Lane 04 nibble 1 raw readback: 004e
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 004e
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0050
|
|
Lane 05 nibble 1 raw readback: 0055
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0055
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0056
|
|
Lane 06 nibble 1 raw readback: 0059
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0059
|
|
Lane 07 nibble 1 raw readback: 005f
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 005f
|
|
Lane 07 nibble 1 adjusted value (post nibble): 005e
|
|
Lane 08 nibble 1 raw readback: 004f
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 004f
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0051
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 005e
|
|
Lane 00 new seed: 005e
|
|
Lane 01 scaled delay: 0058
|
|
Lane 01 new seed: 0058
|
|
Lane 02 scaled delay: 0055
|
|
Lane 02 new seed: 0055
|
|
Lane 03 scaled delay: 0052
|
|
Lane 03 new seed: 0052
|
|
Lane 04 scaled delay: 0043
|
|
Lane 04 new seed: 0043
|
|
Lane 05 scaled delay: 0049
|
|
Lane 05 new seed: 0049
|
|
Lane 06 scaled delay: 004d
|
|
Lane 06 new seed: 004d
|
|
Lane 07 scaled delay: 0050
|
|
Lane 07 new seed: 0050
|
|
Lane 08 scaled delay: 0048
|
|
Lane 08 new seed: 0048
|
|
Lane 00 nibble 0 raw readback: 0060
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0060
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0060
|
|
Lane 01 nibble 0 raw readback: 005a
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 005a
|
|
Lane 01 nibble 0 adjusted value (post nibble): 005a
|
|
Lane 02 nibble 0 raw readback: 0055
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0055
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0055
|
|
Lane 03 nibble 0 raw readback: 0050
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 03 nibble 0 adjusted value (post nibble): 0050
|
|
Lane 04 nibble 0 raw readback: 003f
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 003f
|
|
Lane 04 nibble 0 adjusted value (post nibble): 003f
|
|
Lane 05 nibble 0 raw readback: 0044
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0044
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0044
|
|
Lane 06 nibble 0 raw readback: 0049
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0049
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0049
|
|
Lane 07 nibble 0 raw readback: 004e
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 004e
|
|
Lane 07 nibble 0 adjusted value (post nibble): 004e
|
|
Lane 08 nibble 0 raw readback: 0041
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0041
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0041
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 005e
|
|
Lane 01 new seed: 0058
|
|
Lane 02 new seed: 0055
|
|
Lane 03 new seed: 0052
|
|
Lane 04 new seed: 0043
|
|
Lane 05 new seed: 0049
|
|
Lane 06 new seed: 004d
|
|
Lane 07 new seed: 0050
|
|
Lane 08 new seed: 0048
|
|
Lane 00 nibble 1 raw readback: 005f
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 005f
|
|
Lane 00 nibble 1 adjusted value (post nibble): 005e
|
|
Lane 01 nibble 1 raw readback: 0059
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0058
|
|
Lane 02 nibble 1 raw readback: 0053
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0053
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0054
|
|
Lane 03 nibble 1 raw readback: 0050
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0050
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0051
|
|
Lane 04 nibble 1 raw readback: 003d
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 003d
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0040
|
|
Lane 05 nibble 1 raw readback: 0044
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0044
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0046
|
|
Lane 06 nibble 1 raw readback: 0048
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0048
|
|
Lane 06 nibble 1 adjusted value (post nibble): 004a
|
|
Lane 07 nibble 1 raw readback: 004e
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 004e
|
|
Lane 07 nibble 1 adjusted value (post nibble): 004f
|
|
Lane 08 nibble 1 raw readback: 0040
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0040
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0044
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
|
|
DIMM 1 RttWr: 2
|
|
DIMM 1 RttNom: 1
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
|
|
DIMM 1 RttNom: 1
|
|
DIMM 1 RttWr: 2
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
|
|
DIMM 1 RttWr: 2
|
|
SetTargetFreq: Start
|
|
SetTargetFreq: Node 0: New frequency code: 0012
|
|
ChangeMemClk: Start
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 0 timing/termination pattern 00363936 30112222
|
|
mct_PlatformSpec: Done
|
|
set_2t_configuration: Start
|
|
set_2t_configuration: Done
|
|
mct_BeforePlatformSpec: Start
|
|
mct_BeforePlatformSpec: Done
|
|
mct_PlatformSpec: Start
|
|
Programmed DCT 1 timing/termination pattern 00363936 30112222
|
|
mct_PlatformSpec: Done
|
|
ChangeMemClk: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 0: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 0: Done
|
|
phyAssistedMemFnceTraining: Start
|
|
phyAssistedMemFnceTraining: training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 0
|
|
phyAssistedMemFnceTraining: training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: done training node 0 DCT 1
|
|
phyAssistedMemFnceTraining: Done
|
|
InitPhyCompensation: DCT 1: Start
|
|
Waiting for predriver calibration to be applied...done!
|
|
InitPhyCompensation: DCT 1: Done
|
|
Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
|
|
Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c20)
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
|
|
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
|
|
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
|
|
SetTargetFreq: Done
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 007c
|
|
Lane 00 new seed: 007c
|
|
Lane 01 scaled delay: 0073
|
|
Lane 01 new seed: 0073
|
|
Lane 02 scaled delay: 006f
|
|
Lane 02 new seed: 006f
|
|
Lane 03 scaled delay: 006b
|
|
Lane 03 new seed: 006b
|
|
Lane 04 scaled delay: 0059
|
|
Lane 04 new seed: 0059
|
|
Lane 05 scaled delay: 0060
|
|
Lane 05 new seed: 0060
|
|
Lane 06 scaled delay: 0064
|
|
Lane 06 new seed: 0064
|
|
Lane 07 scaled delay: 006a
|
|
Lane 07 new seed: 006a
|
|
Lane 08 scaled delay: 005a
|
|
Lane 08 new seed: 005a
|
|
Lane 00 nibble 0 raw readback: 0043
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 0083
|
|
Lane 00 nibble 0 adjusted value (post nibble): 0083
|
|
Lane 01 nibble 0 raw readback: 0037
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0077
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0077
|
|
Lane 02 nibble 0 raw readback: 0032
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 0072
|
|
Lane 02 nibble 0 adjusted value (post nibble): 0072
|
|
Lane 03 nibble 0 raw readback: 002d
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 006d
|
|
Lane 03 nibble 0 adjusted value (post nibble): 006d
|
|
Lane 04 nibble 0 raw readback: 0059
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0059
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0059
|
|
Lane 05 nibble 0 raw readback: 0022
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 0062
|
|
Lane 05 nibble 0 adjusted value (post nibble): 0062
|
|
Lane 06 nibble 0 raw readback: 0027
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0067
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0067
|
|
Lane 07 nibble 0 raw readback: 002d
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 006d
|
|
Lane 07 nibble 0 adjusted value (post nibble): 006d
|
|
Lane 08 nibble 0 raw readback: 005b
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 005b
|
|
Lane 08 nibble 0 adjusted value (post nibble): 005b
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 007c
|
|
Lane 01 new seed: 0073
|
|
Lane 02 new seed: 006f
|
|
Lane 03 new seed: 006b
|
|
Lane 04 new seed: 0059
|
|
Lane 05 new seed: 0060
|
|
Lane 06 new seed: 0064
|
|
Lane 07 new seed: 006a
|
|
Lane 08 new seed: 005a
|
|
Lane 00 nibble 1 raw readback: 0042
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 0082
|
|
Lane 00 nibble 1 adjusted value (post nibble): 007f
|
|
Lane 01 nibble 1 raw readback: 0038
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0078
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0075
|
|
Lane 02 nibble 1 raw readback: 0032
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 0072
|
|
Lane 02 nibble 1 adjusted value (post nibble): 0070
|
|
Lane 03 nibble 1 raw readback: 002d
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 006d
|
|
Lane 03 nibble 1 adjusted value (post nibble): 006c
|
|
Lane 04 nibble 1 raw readback: 005a
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 005a
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0059
|
|
Lane 05 nibble 1 raw readback: 0021
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 0061
|
|
Lane 05 nibble 1 adjusted value (post nibble): 0060
|
|
Lane 06 nibble 1 raw readback: 0026
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 0066
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0065
|
|
Lane 07 nibble 1 raw readback: 002e
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 006e
|
|
Lane 07 nibble 1 adjusted value (post nibble): 006c
|
|
Lane 08 nibble 1 raw readback: 005a
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 005a
|
|
Lane 08 nibble 1 adjusted value (post nibble): 005a
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
SPD2ndTiming: Start
|
|
SPD2ndTiming: Done
|
|
mct_BeforeDramInit_Prod_D: Start
|
|
mct_ProgramODT_D: Start
|
|
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
|
|
mct_ProgramODT_D: Done
|
|
mct_BeforeDramInit_Prod_D: Done
|
|
mct_DramInit_Sw_D: Start
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
|
|
mct_SendMrsCmd: Start
|
|
mct_SendMrsCmd: Done
|
|
mct_DramInit_Sw_D: Done
|
|
AgesaHwWlPhase1: training nibble 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 scaled delay: 006a
|
|
Lane 00 new seed: 006a
|
|
Lane 01 scaled delay: 0063
|
|
Lane 01 new seed: 0063
|
|
Lane 02 scaled delay: 005e
|
|
Lane 02 new seed: 005e
|
|
Lane 03 scaled delay: 005a
|
|
Lane 03 new seed: 005a
|
|
Lane 04 scaled delay: 0046
|
|
Lane 04 new seed: 0046
|
|
Lane 05 scaled delay: 004d
|
|
Lane 05 new seed: 004d
|
|
Lane 06 scaled delay: 0052
|
|
Lane 06 new seed: 0052
|
|
Lane 07 scaled delay: 0058
|
|
Lane 07 new seed: 0058
|
|
Lane 08 scaled delay: 004b
|
|
Lane 08 new seed: 004b
|
|
Lane 00 nibble 0 raw readback: 002c
|
|
Lane 00 nibble 0 adjusted value (pre nibble): 006c
|
|
Lane 00 nibble 0 adjusted value (post nibble): 006c
|
|
Lane 01 nibble 0 raw readback: 0025
|
|
Lane 01 nibble 0 adjusted value (pre nibble): 0065
|
|
Lane 01 nibble 0 adjusted value (post nibble): 0065
|
|
Lane 02 nibble 0 raw readback: 005f
|
|
Lane 02 nibble 0 adjusted value (pre nibble): 005f
|
|
Lane 02 nibble 0 adjusted value (post nibble): 005f
|
|
Lane 03 nibble 0 raw readback: 005a
|
|
Lane 03 nibble 0 adjusted value (pre nibble): 005a
|
|
Lane 03 nibble 0 adjusted value (post nibble): 005a
|
|
Lane 04 nibble 0 raw readback: 0045
|
|
Lane 04 nibble 0 adjusted value (pre nibble): 0045
|
|
Lane 04 nibble 0 adjusted value (post nibble): 0045
|
|
Lane 05 nibble 0 raw readback: 004b
|
|
Lane 05 nibble 0 adjusted value (pre nibble): 004b
|
|
Lane 05 nibble 0 adjusted value (post nibble): 004b
|
|
Lane 06 nibble 0 raw readback: 0050
|
|
Lane 06 nibble 0 adjusted value (pre nibble): 0050
|
|
Lane 06 nibble 0 adjusted value (post nibble): 0050
|
|
Lane 07 nibble 0 raw readback: 0057
|
|
Lane 07 nibble 0 adjusted value (pre nibble): 0057
|
|
Lane 07 nibble 0 adjusted value (post nibble): 0057
|
|
Lane 08 nibble 0 raw readback: 0048
|
|
Lane 08 nibble 0 adjusted value (pre nibble): 0048
|
|
Lane 08 nibble 0 adjusted value (post nibble): 0048
|
|
AgesaHwWlPhase1: training nibble 1
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
|
|
Lane 00 new seed: 006a
|
|
Lane 01 new seed: 0063
|
|
Lane 02 new seed: 005e
|
|
Lane 03 new seed: 005a
|
|
Lane 04 new seed: 0046
|
|
Lane 05 new seed: 004d
|
|
Lane 06 new seed: 0052
|
|
Lane 07 new seed: 0058
|
|
Lane 08 new seed: 004b
|
|
Lane 00 nibble 1 raw readback: 002c
|
|
Lane 00 nibble 1 adjusted value (pre nibble): 006c
|
|
Lane 00 nibble 1 adjusted value (post nibble): 006b
|
|
Lane 01 nibble 1 raw readback: 0024
|
|
Lane 01 nibble 1 adjusted value (pre nibble): 0064
|
|
Lane 01 nibble 1 adjusted value (post nibble): 0063
|
|
Lane 02 nibble 1 raw readback: 005d
|
|
Lane 02 nibble 1 adjusted value (pre nibble): 005d
|
|
Lane 02 nibble 1 adjusted value (post nibble): 005d
|
|
Lane 03 nibble 1 raw readback: 0059
|
|
Lane 03 nibble 1 adjusted value (pre nibble): 0059
|
|
Lane 03 nibble 1 adjusted value (post nibble): 0059
|
|
Lane 04 nibble 1 raw readback: 0043
|
|
Lane 04 nibble 1 adjusted value (pre nibble): 0043
|
|
Lane 04 nibble 1 adjusted value (post nibble): 0044
|
|
Lane 05 nibble 1 raw readback: 004c
|
|
Lane 05 nibble 1 adjusted value (pre nibble): 004c
|
|
Lane 05 nibble 1 adjusted value (post nibble): 004c
|
|
Lane 06 nibble 1 raw readback: 004f
|
|
Lane 06 nibble 1 adjusted value (pre nibble): 004f
|
|
Lane 06 nibble 1 adjusted value (post nibble): 0050
|
|
Lane 07 nibble 1 raw readback: 0058
|
|
Lane 07 nibble 1 adjusted value (pre nibble): 0058
|
|
Lane 07 nibble 1 adjusted value (post nibble): 0058
|
|
Lane 08 nibble 1 raw readback: 0048
|
|
Lane 08 nibble 1 adjusted value (pre nibble): 0048
|
|
Lane 08 nibble 1 adjusted value (post nibble): 0049
|
|
original critical gross delay: 0
|
|
new critical gross delay: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
|
|
DIMM 1 RttWr: 0
|
|
DIMM 1 RttNom: 3
|
|
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
|
|
DIMM 1 RttNom: 3
|
|
DIMM 1 RttWr: 0
|
|
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
|
|
DIMM 1 RttWr: 0
|
|
activate_spd_rom() for node 01
|
|
enable_spd_node1()
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 0054
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
fam15_receiver_enable_training_seed: using seed: 004d
|
|
TrainRcvrEn: Status 2205
|
|
TrainRcvrEn: ErrStatus 0
|
|
TrainRcvrEn: ErrCode 0
|
|
TrainRcvrEn: Done
|
|
|
|
TrainDQSReceiverEnCyc: Status 2205
|
|
TrainDQSReceiverEnCyc: TrainErrors 4000
|
|
TrainDQSReceiverEnCyc: ErrStatus 4000
|
|
TrainDQSReceiverEnCyc: ErrCode 0
|
|
TrainDQSReceiverEnCyc: Done
|
|
|
|
TrainMaxRdLatency: Status 2205
|
|
TrainMaxRdLatency: ErrStatus 4000
|
|
TrainMaxRdLatency: ErrCode 0
|
|
TrainMaxRdLatency: Done
|
|
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
mctAutoInitMCT_D: :OtherTiming
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
InterleaveNodes_D: Status 2205
|
|
InterleaveNodes_D: ErrStatus 4000
|
|
InterleaveNodes_D: ErrCode 0
|
|
InterleaveNodes_D: Done
|
|
|
|
InterleaveChannels_D: Node 0
|
|
InterleaveChannels_D: Status 2205
|
|
InterleaveChannels_D: ErrStatus 4000
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Node 1
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 1
|
|
InterleaveChannels_D: ErrCode 2
|
|
InterleaveChannels_D: Node 2
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 0
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Node 3
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 0
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Node 4
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 0
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Node 5
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 0
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Node 6
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 0
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Node 7
|
|
InterleaveChannels_D: Status 2000
|
|
InterleaveChannels_D: ErrStatus 0
|
|
InterleaveChannels_D: ErrCode 0
|
|
InterleaveChannels_D: Done
|
|
|
|
mctAutoInitMCT_D: ECCInit_D
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
DCTMemClr_Sync_D: Start
|
|
DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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...................................................................................................................................................................................................................................................................................................................
|
|
.
|
|
DCTMemClr_Sync_D: Done
|
|
DCTMemClr_Sync_D: Start
|
|
DCTMemClr_Sync_D: Done
|
|
ECC enabled on node: 00
|
|
DCTMemClr_Sync_D: Start
|
|
DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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.............................................................................................................................................................................................................................................................................................
|
|
.
|
|
DCTMemClr_Sync_D: Done
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
ECCInit: Node 00
|
|
ECCInit: Status 2205
|
|
ECCInit: ErrStatus 4000
|
|
ECCInit: ErrCode 0
|
|
ECCInit: Done
|
|
ECCInit: Node 01
|
|
ECCInit: Status 2000
|
|
ECCInit: ErrStatus 1
|
|
ECCInit: ErrCode 2
|
|
ECCInit: Done
|
|
mctAutoInitMCT_D: CPUMemTyping_D
|
|
CPUMemTyping: Cache32bTOP:c00000
|
|
CPUMemTyping: Bottom32bIO:c00000
|
|
CPUMemTyping: Bottom40bIO:8400000
|
|
mctAutoInitMCT_D: UMAMemTyping_D
|
|
mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 0 (interleaved: 0)
|
|
set_up_cc6_storage_fam15: original (node 0) max_range_limit: 83fffffff DRAM limit: 83fffffff
|
|
set_up_cc6_storage_fam15: new max_range_limit: 83effffff
|
|
set_up_cc6_storage_fam15: Target node: 0
|
|
set_up_cc6_storage_fam15: Done
|
|
set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 1 (interleaved: 0)
|
|
set_up_cc6_storage_fam15: original (node 0) max_range_limit: 83fffffff DRAM limit: 7ffffff
|
|
set_up_cc6_storage_fam15: new max_range_limit: 83effffff
|
|
set_up_cc6_storage_fam15: Target node: 0
|
|
set_up_cc6_storage_fam15: Done
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
mctAutoInitMCT_D Done: Global Status: 12
|
|
raminit_amdmct end:
|
|
CBMEM:
|
|
IMD: root @ b7fff000 254 entries.
|
|
IMD: root @ b7ffec00 62 entries.
|
|
POST: 0x41
|
|
amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
disable_spd()
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'fallback/ramstage'
|
|
CBFS: Found @ offset 3ff00 size 14f67
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
|
|
|
|
coreboot-e3515e3-dirty Wed Apr 27 11:27:53 UTC 2016 ramstage starting...
|
|
POST: 0x39
|
|
Moving GDT to b7ffe9e0...ok
|
|
POST: 0x80
|
|
Normal boot.
|
|
POST: 0x70
|
|
BS: BS_PRE_DEVICE times (us): entry 0 run 582 exit 0
|
|
POST: 0x71
|
|
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 584 exit 0
|
|
POST: 0x72
|
|
Enumerating buses...
|
|
Show all devs... Before device enumeration.
|
|
Root Device: enabled 1
|
|
CPU_CLUSTER: 0: enabled 1
|
|
APIC: 00: enabled 1
|
|
DOMAIN: 0000: enabled 1
|
|
PCI: 00:18.0: enabled 1
|
|
PCI: 00:00.0: enabled 1
|
|
PCI: 00:00.1: enabled 1
|
|
PCI: 00:00.2: enabled 1
|
|
PCI: 00:02.0: enabled 1
|
|
PCI: 00:03.0: enabled 0
|
|
PCI: 00:04.0: enabled 1
|
|
PCI: 00:05.0: enabled 0
|
|
PCI: 00:06.0: enabled 0
|
|
PCI: 00:07.0: enabled 0
|
|
PCI: 00:08.0: enabled 0
|
|
PCI: 00:09.0: enabled 1
|
|
PCI: 00:0a.0: enabled 1
|
|
PCI: 00:0b.0: enabled 1
|
|
PCI: 00:0c.0: enabled 1
|
|
PCI: 00:0d.0: enabled 1
|
|
PCI: 00:11.0: enabled 1
|
|
PCI: 00:12.0: enabled 1
|
|
PCI: 00:12.1: enabled 1
|
|
PCI: 00:12.2: enabled 1
|
|
PCI: 00:13.0: enabled 1
|
|
PCI: 00:13.1: enabled 1
|
|
PCI: 00:13.2: enabled 1
|
|
PCI: 00:14.0: enabled 1
|
|
I2C: 00:50: enabled 1
|
|
I2C: 00:51: enabled 1
|
|
I2C: 00:52: enabled 1
|
|
I2C: 00:53: enabled 1
|
|
I2C: 00:54: enabled 1
|
|
I2C: 00:55: enabled 1
|
|
I2C: 00:56: enabled 1
|
|
I2C: 00:57: enabled 1
|
|
I2C: 00:2f: enabled 1
|
|
PCI: 00:14.1: enabled 1
|
|
PCI: 00:14.2: enabled 1
|
|
PCI: 00:14.3: enabled 1
|
|
PNP: 002e.0: enabled 0
|
|
PNP: 002e.1: enabled 0
|
|
PNP: 002e.2: enabled 1
|
|
PNP: 002e.3: enabled 1
|
|
PNP: 002e.5: enabled 1
|
|
PNP: 002e.106: enabled 0
|
|
PNP: 002e.107: enabled 0
|
|
PNP: 002e.207: enabled 0
|
|
PNP: 002e.307: enabled 0
|
|
PNP: 002e.407: enabled 0
|
|
PNP: 002e.8: enabled 0
|
|
PNP: 002e.108: enabled 0
|
|
PNP: 002e.9: enabled 0
|
|
PNP: 002e.109: enabled 0
|
|
PNP: 002e.209: enabled 0
|
|
PNP: 002e.309: enabled 0
|
|
PNP: 002e.a: enabled 1
|
|
PNP: 002e.b: enabled 1
|
|
PNP: 002e.c: enabled 0
|
|
PNP: 002e.d: enabled 0
|
|
PNP: 002e.f: enabled 0
|
|
PCI: 00:14.4: enabled 1
|
|
PCI: 00:01.0: enabled 1
|
|
PCI: 00:02.0: enabled 1
|
|
PCI: 00:03.0: enabled 1
|
|
PCI: 00:14.5: enabled 1
|
|
PCI: 00:18.1: enabled 1
|
|
PCI: 00:18.2: enabled 1
|
|
PCI: 00:18.3: enabled 1
|
|
PCI: 00:18.4: enabled 1
|
|
PCI: 00:18.5: enabled 1
|
|
PCI: 00:19.0: enabled 1
|
|
PCI: 00:19.1: enabled 1
|
|
PCI: 00:19.2: enabled 1
|
|
PCI: 00:19.3: enabled 1
|
|
PCI: 00:19.4: enabled 1
|
|
PCI: 00:19.5: enabled 1
|
|
PCI: 00:1a.0: enabled 1
|
|
PCI: 00:1a.1: enabled 1
|
|
PCI: 00:1a.2: enabled 1
|
|
PCI: 00:1a.3: enabled 1
|
|
PCI: 00:1a.4: enabled 1
|
|
PCI: 00:1a.5: enabled 1
|
|
PCI: 00:1b.0: enabled 1
|
|
PCI: 00:1b.1: enabled 1
|
|
PCI: 00:1b.2: enabled 1
|
|
PCI: 00:1b.3: enabled 1
|
|
PCI: 00:1b.4: enabled 1
|
|
PCI: 00:1b.5: enabled 1
|
|
Compare with tree...
|
|
Root Device: enabled 1
|
|
CPU_CLUSTER: 0: enabled 1
|
|
APIC: 00: enabled 1
|
|
DOMAIN: 0000: enabled 1
|
|
PCI: 00:18.0: enabled 1
|
|
PCI: 00:00.0: enabled 1
|
|
PCI: 00:00.1: enabled 1
|
|
PCI: 00:00.2: enabled 1
|
|
PCI: 00:02.0: enabled 1
|
|
PCI: 00:03.0: enabled 0
|
|
PCI: 00:04.0: enabled 1
|
|
PCI: 00:05.0: enabled 0
|
|
PCI: 00:06.0: enabled 0
|
|
PCI: 00:07.0: enabled 0
|
|
PCI: 00:08.0: enabled 0
|
|
PCI: 00:09.0: enabled 1
|
|
PCI: 00:0a.0: enabled 1
|
|
PCI: 00:0b.0: enabled 1
|
|
PCI: 00:0c.0: enabled 1
|
|
PCI: 00:0d.0: enabled 1
|
|
PCI: 00:11.0: enabled 1
|
|
PCI: 00:12.0: enabled 1
|
|
PCI: 00:12.1: enabled 1
|
|
PCI: 00:12.2: enabled 1
|
|
PCI: 00:13.0: enabled 1
|
|
PCI: 00:13.1: enabled 1
|
|
PCI: 00:13.2: enabled 1
|
|
PCI: 00:14.0: enabled 1
|
|
I2C: 00:50: enabled 1
|
|
I2C: 00:51: enabled 1
|
|
I2C: 00:52: enabled 1
|
|
I2C: 00:53: enabled 1
|
|
I2C: 00:54: enabled 1
|
|
I2C: 00:55: enabled 1
|
|
I2C: 00:56: enabled 1
|
|
I2C: 00:57: enabled 1
|
|
I2C: 00:2f: enabled 1
|
|
PCI: 00:14.1: enabled 1
|
|
PCI: 00:14.2: enabled 1
|
|
PCI: 00:14.3: enabled 1
|
|
PNP: 002e.0: enabled 0
|
|
PNP: 002e.1: enabled 0
|
|
PNP: 002e.2: enabled 1
|
|
PNP: 002e.3: enabled 1
|
|
PNP: 002e.5: enabled 1
|
|
PNP: 002e.106: enabled 0
|
|
PNP: 002e.107: enabled 0
|
|
PNP: 002e.207: enabled 0
|
|
PNP: 002e.307: enabled 0
|
|
PNP: 002e.407: enabled 0
|
|
PNP: 002e.8: enabled 0
|
|
PNP: 002e.108: enabled 0
|
|
PNP: 002e.9: enabled 0
|
|
PNP: 002e.109: enabled 0
|
|
PNP: 002e.209: enabled 0
|
|
PNP: 002e.309: enabled 0
|
|
PNP: 002e.a: enabled 1
|
|
PNP: 002e.b: enabled 1
|
|
PNP: 002e.c: enabled 0
|
|
PNP: 002e.d: enabled 0
|
|
PNP: 002e.f: enabled 0
|
|
PCI: 00:14.4: enabled 1
|
|
PCI: 00:01.0: enabled 1
|
|
PCI: 00:02.0: enabled 1
|
|
PCI: 00:03.0: enabled 1
|
|
PCI: 00:14.5: enabled 1
|
|
PCI: 00:18.1: enabled 1
|
|
PCI: 00:18.2: enabled 1
|
|
PCI: 00:18.3: enabled 1
|
|
PCI: 00:18.4: enabled 1
|
|
PCI: 00:18.5: enabled 1
|
|
PCI: 00:19.0: enabled 1
|
|
PCI: 00:19.1: enabled 1
|
|
PCI: 00:19.2: enabled 1
|
|
PCI: 00:19.3: enabled 1
|
|
PCI: 00:19.4: enabled 1
|
|
PCI: 00:19.5: enabled 1
|
|
PCI: 00:1a.0: enabled 1
|
|
PCI: 00:1a.1: enabled 1
|
|
PCI: 00:1a.2: enabled 1
|
|
PCI: 00:1a.3: enabled 1
|
|
PCI: 00:1a.4: enabled 1
|
|
PCI: 00:1a.5: enabled 1
|
|
PCI: 00:1b.0: enabled 1
|
|
PCI: 00:1b.1: enabled 1
|
|
PCI: 00:1b.2: enabled 1
|
|
PCI: 00:1b.3: enabled 1
|
|
PCI: 00:1b.4: enabled 1
|
|
PCI: 00:1b.5: enabled 1
|
|
Mainboard KGPE-D16 Enable. dev=0x0012c480
|
|
mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
|
|
mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000008
|
|
Root Device scanning...
|
|
root_dev_scan_bus for Root Device
|
|
setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
|
|
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000008
|
|
CPU_CLUSTER: 0 enabled
|
|
DOMAIN: 0000 enabled
|
|
CPU_CLUSTER: 0 scanning...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
PCI: 00:18.5 siblings=7
|
|
CPU: APIC: 00 enabled
|
|
CPU: APIC: 01 enabled
|
|
CPU: APIC: 02 enabled
|
|
CPU: APIC: 03 enabled
|
|
CPU: APIC: 04 enabled
|
|
CPU: APIC: 05 enabled
|
|
CPU: APIC: 06 enabled
|
|
CPU: APIC: 07 enabled
|
|
PCI: 00:19.5 siblings=7
|
|
CPU: APIC: 08 enabled
|
|
CPU: APIC: 09 enabled
|
|
CPU: APIC: 0a enabled
|
|
CPU: APIC: 0b enabled
|
|
CPU: APIC: 0c enabled
|
|
CPU: APIC: 0d enabled
|
|
CPU: APIC: 0e enabled
|
|
CPU: APIC: 0f enabled
|
|
scan_bus: scanning of bus CPU_CLUSTER: 0 took 35020 usecs
|
|
DOMAIN: 0000 scanning...
|
|
PCI: pci_scan_bus for bus 00
|
|
POST: 0x24
|
|
PCI: 00:18.0 [1022/1600] bus ops
|
|
PCI: 00:18.0 [1022/1600] enabled
|
|
PCI: 00:18.1 [1022/1601] enabled
|
|
PCI: 00:18.2 [1022/1602] enabled
|
|
PCI: 00:18.3 [1022/1603] ops
|
|
PCI: 00:18.3 [1022/1603] enabled
|
|
PCI: 00:18.4 [1022/1604] ops
|
|
PCI: 00:18.4 [1022/1604] enabled
|
|
PCI: 00:18.5 [1022/1605] ops
|
|
PCI: 00:18.5 [1022/1605] enabled
|
|
PCI: 00:19.0 [1022/1600] bus ops
|
|
PCI: 00:19.0 [1022/1600] enabled
|
|
PCI: 00:19.1 [1022/1601] enabled
|
|
PCI: 00:19.2 [1022/1602] enabled
|
|
PCI: 00:19.3 [1022/1603] ops
|
|
PCI: 00:19.3 [1022/1603] enabled
|
|
PCI: 00:19.4 [1022/1604] ops
|
|
PCI: 00:19.4 [1022/1604] enabled
|
|
PCI: 00:19.5 [1022/1605] ops
|
|
PCI: 00:19.5 [1022/1605] enabled
|
|
PCI: Static device PCI: 00:1a.0 not found, disabling it.
|
|
PCI: Static device PCI: 00:1a.1 not found, disabling it.
|
|
PCI: Static device PCI: 00:1a.2 not found, disabling it.
|
|
PCI: Static device PCI: 00:1a.3 not found, disabling it.
|
|
PCI: Static device PCI: 00:1a.4 not found, disabling it.
|
|
PCI: Static device PCI: 00:1a.5 not found, disabling it.
|
|
PCI: Static device PCI: 00:1b.0 not found, disabling it.
|
|
PCI: Static device PCI: 00:1b.1 not found, disabling it.
|
|
PCI: Static device PCI: 00:1b.2 not found, disabling it.
|
|
PCI: Static device PCI: 00:1b.3 not found, disabling it.
|
|
PCI: Static device PCI: 00:1b.4 not found, disabling it.
|
|
PCI: Static device PCI: 00:1b.5 not found, disabling it.
|
|
POST: 0x25
|
|
PCI: 00:18.0 scanning...
|
|
do_hypertransport_scan_chain for bus 00
|
|
sr5650_enable: dev=0012ed00, VID_DID=0x5a101002
|
|
Bus-0, Dev-0, Fun-0.
|
|
enable_pcie_bar3
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e760, port=0x8
|
|
PciePowerOffGppPorts() port 8
|
|
NB_PCI_REG04 = 2.
|
|
NB_PCI_REG84 = 3000010.
|
|
NB_PCI_REG4C = 52042.
|
|
Sysmem TOM = 0_c0000000
|
|
Sysmem TOM2 = 8_40000000
|
|
PCI: 00:00.0 [1002/5a10] ops
|
|
PCI: 00:00.0 [1002/5a10] enabled
|
|
Capability: type 0x08 @ 0xf0
|
|
flags: 0xa803
|
|
Capability: type 0x08 @ 0xf0
|
|
Capability: type 0x08 @ 0xc4
|
|
flags: 0x0280
|
|
PCI: 00:00.0 count: 0014 static_count: 0015
|
|
PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015
|
|
PCI: pci_scan_bus for bus 00
|
|
POST: 0x24
|
|
sr5650_enable: dev=0012ed00, VID_DID=0x5a101002
|
|
Bus-0, Dev-0, Fun-0.
|
|
enable_pcie_bar3
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e760, port=0x8
|
|
PciePowerOffGppPorts() port 8
|
|
NB_PCI_REG04 = 2.
|
|
NB_PCI_REG84 = 3000010.
|
|
NB_PCI_REG4C = 52042.
|
|
Sysmem TOM = 0_c0000000
|
|
Sysmem TOM2 = 8_40000000
|
|
PCI: 00:00.0 [1002/5a10] enabled
|
|
sr5650_enable: dev=0012ec60, VID_DID=0xffffffff
|
|
Bus-0, Dev-0, Fun-1.
|
|
PCI: Static device PCI: 00:00.1 not found, disabling it.
|
|
sr5650_enable: dev=0012ebc0, VID_DID=0x5a231002
|
|
Bus-0, Dev-0, Fun-2.
|
|
PCI: 00:00.2 [1002/5a23] ops
|
|
PCI: 00:00.2 [1002/5a23] enabled
|
|
sr5650_enable: dev=0012eb20, VID_DID=0xffffffff
|
|
Bus-0, Dev-2,3, Fun-0. enable=1
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012eb20, port=0x2
|
|
PcieLinkTraining port=2:lc current state=2030400
|
|
sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0
|
|
PciePowerOffGppPorts() port 2
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:02.0 subordinate bus PCI Express
|
|
PCI: 00:02.0 [1002/5a16] enabled
|
|
sr5650_enable: dev=0012ea80, VID_DID=0xffffffff
|
|
Bus-0, Dev-2,3, Fun-0. enable=0
|
|
sr5650_enable: dev=0012e9e0, VID_DID=0xffffffff
|
|
enable_pcie_bar3
|
|
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e9e0, port=0x4
|
|
PcieLinkTraining port=4:lc current state=2030400
|
|
sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
|
|
PciePowerOffGppPorts() port 4
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:04.0 subordinate bus PCI Express
|
|
PCI: 00:04.0 [1002/5a18] enabled
|
|
sr5650_enable: dev=0012e940, VID_DID=0xffffffff
|
|
enable_pcie_bar3
|
|
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
|
|
sr5650_enable: dev=0012e8a0, VID_DID=0xffffffff
|
|
enable_pcie_bar3
|
|
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
|
|
sr5650_enable: dev=0012e800, VID_DID=0xffffffff
|
|
enable_pcie_bar3
|
|
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
|
|
sr5650_enable: dev=0012e760, VID_DID=0xffffffff
|
|
Bus-0, Dev-8, Fun-0. enable=0
|
|
disable_pcie_bar3
|
|
sr5650_enable: dev=0012e6c0, VID_DID=0xffffffff
|
|
Bus-0, Dev-9, 10, Fun-0. enable=1
|
|
enable_pcie_bar3
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e6c0, port=0x9
|
|
PcieLinkTraining port=5:lc current state=a0b0f10
|
|
addr=c0000000,bus=0,devfn=48
|
|
PcieTrainPort reg=0x10000
|
|
sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:09.0 subordinate bus PCI Express
|
|
PCI: 00:09.0 [1002/5a1c] enabled
|
|
sr5650_enable: dev=0012e620, VID_DID=0xffffffff
|
|
Bus-0, Dev-9, 10, Fun-0. enable=1
|
|
enable_pcie_bar3
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e620, port=0xa
|
|
PcieLinkTraining port=6:lc current state=a0b0f10
|
|
addr=c0000000,bus=0,devfn=50
|
|
PcieTrainPort reg=0x10000
|
|
sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:0a.0 subordinate bus PCI Express
|
|
PCI: 00:0a.0 [1002/5a1d] enabled
|
|
sr5650_enable: dev=0012e580, VID_DID=0xffffffff
|
|
Bus-0, Dev-11,12, Fun-0. enable=1
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e580, port=0xb
|
|
PcieLinkTraining port=b:lc current state=2030400
|
|
sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0
|
|
PciePowerOffGppPorts() port 11
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:0b.0 subordinate bus PCI Express
|
|
PCI: 00:0b.0 [1002/5a1f] enabled
|
|
sr5650_enable: dev=0012e4e0, VID_DID=0xffffffff
|
|
Bus-0, Dev-11,12, Fun-0. enable=1
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e4e0, port=0xc
|
|
PcieLinkTraining port=c:lc current state=2030400
|
|
sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0
|
|
PciePowerOffGppPorts() port 12
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:0c.0 subordinate bus PCI Express
|
|
PCI: 00:0c.0 [1002/5a20] enabled
|
|
sr5650_enable: dev=0012e440, VID_DID=0xffffffff
|
|
sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e440, port=0xd
|
|
PcieLinkTraining port=d:lc current state=2030400
|
|
sr5650_gpp_sb_init: port=0xd hw_port=0xd result=0
|
|
PciePowerOffGppPorts() port 13
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Capability: type 0x05 @ 0xa0
|
|
Capability: type 0x0d @ 0xb0
|
|
Capability: type 0x08 @ 0xb8
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
PCI: 00:0d.0 subordinate bus PCI Express
|
|
PCI: 00:0d.0 [1002/5a1e] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:11.0 [1002/4394] ops
|
|
PCI: 00:11.0 [1002/4394] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:12.0 [1002/4397] ops
|
|
PCI: 00:12.0 [1002/4397] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:12.1 [1002/4398] ops
|
|
PCI: 00:12.1 [1002/4398] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:12.2 [1002/4396] ops
|
|
PCI: 00:12.2 [1002/4396] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:13.0 [1002/4397] ops
|
|
PCI: 00:13.0 [1002/4397] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:13.1 [1002/4398] ops
|
|
PCI: 00:13.1 [1002/4398] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:13.2 [1002/4396] ops
|
|
PCI: 00:13.2 [1002/4396] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:14.0 [1002/4385] bus ops
|
|
PCI: 00:14.0 [1002/4385] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:14.1 [1002/439c] ops
|
|
PCI: 00:14.1 [1002/439c] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:14.2 [1002/4383] ops
|
|
PCI: 00:14.2 [1002/4383] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:14.3 [1002/439d] bus ops
|
|
PCI: 00:14.3 [1002/439d] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:14.4 [1002/4384] bus ops
|
|
PCI: 00:14.4 [1002/4384] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 00:14.5 [1002/4399] ops
|
|
PCI: 00:14.5 [1002/4399] enabled
|
|
POST: 0x25
|
|
PCI: 00:02.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:02.0
|
|
PCI: pci_scan_bus for bus 01
|
|
POST: 0x24
|
|
POST: 0x25
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:02.0 took 6239 usecs
|
|
PCI: 00:04.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:04.0
|
|
PCI: pci_scan_bus for bus 02
|
|
POST: 0x24
|
|
POST: 0x25
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:04.0 took 6240 usecs
|
|
PCI: 00:09.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:09.0
|
|
PCI: pci_scan_bus for bus 03
|
|
POST: 0x24
|
|
PCI: 03:00.0 [8086/10d3] enabled
|
|
POST: 0x25
|
|
POST: 0x55
|
|
Capability: type 0x01 @ 0xc8
|
|
Capability: type 0x05 @ 0xd0
|
|
Capability: type 0x10 @ 0xe0
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Enabling Common Clock Configuration
|
|
PCIE CLK PM is not supported by endpointASPM: Enabled None
|
|
scan_bus: scanning of bus PCI: 00:09.0 took 19820 usecs
|
|
PCI: 00:0a.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:0a.0
|
|
PCI: pci_scan_bus for bus 04
|
|
POST: 0x24
|
|
PCI: 04:00.0 [8086/10d3] enabled
|
|
POST: 0x25
|
|
POST: 0x55
|
|
Capability: type 0x01 @ 0xc8
|
|
Capability: type 0x05 @ 0xd0
|
|
Capability: type 0x10 @ 0xe0
|
|
Capability: type 0x01 @ 0x50
|
|
Capability: type 0x10 @ 0x58
|
|
Enabling Common Clock Configuration
|
|
PCIE CLK PM is not supported by endpointASPM: Enabled None
|
|
scan_bus: scanning of bus PCI: 00:0a.0 took 19819 usecs
|
|
PCI: 00:0b.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:0b.0
|
|
PCI: pci_scan_bus for bus 05
|
|
POST: 0x24
|
|
POST: 0x25
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:0b.0 took 6239 usecs
|
|
PCI: 00:0c.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:0c.0
|
|
PCI: pci_scan_bus for bus 06
|
|
POST: 0x24
|
|
POST: 0x25
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:0c.0 took 6240 usecs
|
|
PCI: 00:0d.0 scanning...
|
|
do_pci_scan_bridge for PCI: 00:0d.0
|
|
PCI: pci_scan_bus for bus 07
|
|
POST: 0x24
|
|
POST: 0x25
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:0d.0 took 6240 usecs
|
|
PCI: 00:14.0 scanning...
|
|
scan_smbus for PCI: 00:14.0
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:54 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:55 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:56 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:57 enabled
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:2f enabled
|
|
scan_smbus for PCI: 00:14.0 done
|
|
scan_bus: scanning of bus PCI: 00:14.0 took 23583 usecs
|
|
PCI: 00:14.3 scanning...
|
|
scan_lpc_bus for PCI: 00:14.3
|
|
PNP: 002e.0 disabled
|
|
PNP: 002e.1 disabled
|
|
PNP: 002e.2 enabled
|
|
PNP: 002e.3 enabled
|
|
PNP: 002e.5 enabled
|
|
PNP: 002e.106 disabled
|
|
PNP: 002e.107 disabled
|
|
PNP: 002e.207 disabled
|
|
PNP: 002e.307 disabled
|
|
PNP: 002e.407 disabled
|
|
PNP: 002e.8 disabled
|
|
PNP: 002e.108 disabled
|
|
PNP: 002e.9 disabled
|
|
PNP: 002e.109 disabled
|
|
PNP: 002e.209 disabled
|
|
PNP: 002e.309 disabled
|
|
PNP: 002e.a enabled
|
|
PNP: 002e.b enabled
|
|
PNP: 002e.c disabled
|
|
PNP: 002e.d disabled
|
|
PNP: 002e.f disabled
|
|
scan_lpc_bus for PCI: 00:14.3 done
|
|
scan_bus: scanning of bus PCI: 00:14.3 took 27666 usecs
|
|
PCI: 00:14.4 scanning...
|
|
do_pci_scan_bridge for PCI: 00:14.4
|
|
PCI: pci_scan_bus for bus 08
|
|
POST: 0x24
|
|
sb7xx_51xx_enable()
|
|
PCI: 08:01.0 [1a03/2000] ops
|
|
PCI: 08:01.0 [1a03/2000] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: 08:02.0 [11c1/5811] enabled
|
|
sb7xx_51xx_enable()
|
|
PCI: Static device PCI: 08:03.0 not found, disabling it.
|
|
POST: 0x25
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:14.4 took 16788 usecs
|
|
POST: 0x55
|
|
scan_bus: scanning of bus PCI: 00:18.0 took 1315787 usecs
|
|
PCI: 00:19.0 scanning...
|
|
scan_bus: scanning of bus PCI: 00:19.0 took 1253 usecs
|
|
POST: 0x55
|
|
DOMAIN: 0000 passpw: enabled
|
|
DOMAIN: 0000 passpw: enabled
|
|
scan_bus: scanning of bus DOMAIN: 0000 took 1394940 usecs
|
|
root_dev_scan_bus for Root Device done
|
|
scan_bus: scanning of bus Root Device took 1449353 usecs
|
|
done
|
|
BS: BS_DEV_ENUMERATE times (us): entry 0 run 1691382 exit 0
|
|
POST: 0x73
|
|
found VGA at PCI: 08:01.0
|
|
Setting up VGA for PCI: 08:01.0
|
|
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4
|
|
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
|
|
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
|
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
Allocating resources...
|
|
Reading resources...
|
|
Root Device read_resources bus 0 link: 0
|
|
CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
|
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Reserving CC6 save segment base: 838000000 size: 08000000
|
|
DOMAIN: 0000 read_resources bus 0 link: 0
|
|
PCI: 00:18.0 read_resources bus 0 link: 2
|
|
PCI: 00:18.0 read_resources bus 0 link: 2 done
|
|
PCI: 00:18.0 read_resources bus 0 link: 3
|
|
PCI: 00:18.0 read_resources bus 0 link: 3 done
|
|
PCI: 00:18.0 read_resources bus 0 link: 0
|
|
PCI: 00:18.0 read_resources bus 0 link: 0 done
|
|
PCI: 00:18.0 read_resources bus 0 link: 1
|
|
sr5690_read_resource: PCI: 00:00.0
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
PCI: 00:02.0 read_resources bus 1 link: 0
|
|
PCI: 00:02.0 read_resources bus 1 link: 0 done
|
|
PCI: 00:04.0 read_resources bus 2 link: 0
|
|
PCI: 00:04.0 read_resources bus 2 link: 0 done
|
|
PCI: 00:09.0 read_resources bus 3 link: 0
|
|
PCI: 00:09.0 read_resources bus 3 link: 0 done
|
|
PCI: 00:0a.0 read_resources bus 4 link: 0
|
|
PCI: 00:0a.0 read_resources bus 4 link: 0 done
|
|
PCI: 00:0b.0 read_resources bus 5 link: 0
|
|
PCI: 00:0b.0 read_resources bus 5 link: 0 done
|
|
PCI: 00:0c.0 read_resources bus 6 link: 0
|
|
PCI: 00:0c.0 read_resources bus 6 link: 0 done
|
|
PCI: 00:0d.0 read_resources bus 7 link: 0
|
|
PCI: 00:0d.0 read_resources bus 7 link: 0 done
|
|
PCI: 00:14.0 read_resources bus 1 link: 0
|
|
I2C: 01:50 missing read_resources
|
|
I2C: 01:51 missing read_resources
|
|
I2C: 01:52 missing read_resources
|
|
I2C: 01:53 missing read_resources
|
|
I2C: 01:54 missing read_resources
|
|
I2C: 01:55 missing read_resources
|
|
I2C: 01:56 missing read_resources
|
|
I2C: 01:57 missing read_resources
|
|
PCI: 00:14.0 read_resources bus 1 link: 0 done
|
|
PCI: 00:14.3 read_resources bus 0 link: 0
|
|
PCI: 00:14.3 read_resources bus 0 link: 0 done
|
|
PCI: 00:14.4 read_resources bus 8 link: 0
|
|
PCI: 00:14.4 read_resources bus 8 link: 0 done
|
|
PCI: 00:18.0 read_resources bus 0 link: 1 done
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
PCI: 00:18.4 read_resources bus 0 link: 0
|
|
PCI: 00:18.4 read_resources bus 0 link: 0 done
|
|
PCI: 00:18.4 read_resources bus 0 link: 1
|
|
PCI: 00:18.4 read_resources bus 0 link: 1 done
|
|
PCI: 00:18.4 read_resources bus 0 link: 2
|
|
PCI: 00:18.4 read_resources bus 0 link: 2 done
|
|
PCI: 00:18.4 read_resources bus 0 link: 3
|
|
PCI: 00:18.4 read_resources bus 0 link: 3 done
|
|
PCI: 00:19.0 read_resources bus 0 link: 3
|
|
PCI: 00:19.0 read_resources bus 0 link: 3 done
|
|
PCI: 00:19.0 read_resources bus 0 link: 2
|
|
PCI: 00:19.0 read_resources bus 0 link: 2 done
|
|
PCI: 00:19.0 read_resources bus 0 link: 0
|
|
PCI: 00:19.0 read_resources bus 0 link: 0 done
|
|
PCI: 00:19.0 read_resources bus 0 link: 1
|
|
PCI: 00:19.0 read_resources bus 0 link: 1 done
|
|
PCI: 00:19.4 read_resources bus 0 link: 0
|
|
PCI: 00:19.4 read_resources bus 0 link: 0 done
|
|
PCI: 00:19.4 read_resources bus 0 link: 1
|
|
PCI: 00:19.4 read_resources bus 0 link: 1 done
|
|
PCI: 00:19.4 read_resources bus 0 link: 2
|
|
PCI: 00:19.4 read_resources bus 0 link: 2 done
|
|
PCI: 00:19.4 read_resources bus 0 link: 3
|
|
PCI: 00:19.4 read_resources bus 0 link: 3 done
|
|
DOMAIN: 0000 read_resources bus 0 link: 0 done
|
|
Root Device read_resources bus 0 link: 0 done
|
|
Done reading resources.
|
|
Show resources in subtree (Root Device)...After reading.
|
|
Root Device child on link 0 CPU_CLUSTER: 0
|
|
CPU_CLUSTER: 0 child on link 0 APIC: 00
|
|
APIC: 00
|
|
APIC: 01
|
|
APIC: 02
|
|
APIC: 03
|
|
APIC: 04
|
|
APIC: 05
|
|
APIC: 06
|
|
APIC: 07
|
|
APIC: 08
|
|
APIC: 09
|
|
APIC: 0a
|
|
APIC: 0b
|
|
APIC: 0c
|
|
APIC: 0d
|
|
APIC: 0e
|
|
APIC: 0f
|
|
DOMAIN: 0000 child on link 0 PCI: 00:18.0
|
|
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
|
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
|
DOMAIN: 0000 resource base c0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags f0000200 index c0010058
|
|
DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
|
|
DOMAIN: 0000 resource base 838000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
|
|
PCI: 00:18.0
|
|
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0
|
|
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8
|
|
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8
|
|
PCI: 00:00.0
|
|
PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
|
|
PCI: 00:00.1
|
|
PCI: 00:00.2
|
|
PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
|
|
PCI: 00:02.0
|
|
PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 00:03.0
|
|
PCI: 00:04.0
|
|
PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 00:05.0
|
|
PCI: 00:06.0
|
|
PCI: 00:07.0
|
|
PCI: 00:08.0
|
|
PCI: 00:09.0 child on link 0 PCI: 03:00.0
|
|
PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 03:00.0
|
|
PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
|
PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
|
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
|
|
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
|
|
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 04:00.0
|
|
PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
|
PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
|
PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
|
|
PCI: 00:0b.0
|
|
PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 00:0c.0
|
|
PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 00:0d.0
|
|
PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
|
PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
|
PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 00:11.0
|
|
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
|
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
|
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
|
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
|
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
|
|
PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
|
|
PCI: 00:12.0
|
|
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
|
|
PCI: 00:12.1
|
|
PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
|
|
PCI: 00:12.2
|
|
PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
|
|
PCI: 00:13.0
|
|
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
|
|
PCI: 00:13.1
|
|
PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
|
|
PCI: 00:13.2
|
|
PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
|
|
PCI: 00:14.0 child on link 0 I2C: 01:50
|
|
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
|
|
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
|
|
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
|
|
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
|
|
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
|
|
I2C: 01:50
|
|
I2C: 01:51
|
|
I2C: 01:52
|
|
I2C: 01:53
|
|
I2C: 01:54
|
|
I2C: 01:55
|
|
I2C: 01:56
|
|
I2C: 01:57
|
|
I2C: 01:2f
|
|
PCI: 00:14.1
|
|
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
|
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
|
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
|
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
|
PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
|
|
PCI: 00:14.2
|
|
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
|
PCI: 00:14.3 child on link 0 PNP: 002e.0
|
|
PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
|
|
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
|
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
|
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
|
PNP: 002e.0
|
|
PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
|
|
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
|
|
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
|
|
PNP: 002e.1
|
|
PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
|
|
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
|
|
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
|
|
PNP: 002e.2
|
|
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
|
|
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
|
|
PNP: 002e.3
|
|
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
|
|
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
|
|
PNP: 002e.5
|
|
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
|
|
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
|
|
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
|
|
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
|
|
PNP: 002e.106
|
|
PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
|
|
PNP: 002e.107
|
|
PNP: 002e.207
|
|
PNP: 002e.307
|
|
PNP: 002e.407
|
|
PNP: 002e.8
|
|
PNP: 002e.108
|
|
PNP: 002e.9
|
|
PNP: 002e.109
|
|
PNP: 002e.209
|
|
PNP: 002e.309
|
|
PNP: 002e.a
|
|
PNP: 002e.b
|
|
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
|
|
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
|
|
PNP: 002e.c
|
|
PNP: 002e.d
|
|
PNP: 002e.f
|
|
PCI: 00:14.4 child on link 0 PCI: 08:01.0
|
|
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
|
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
|
|
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
|
PCI: 08:01.0
|
|
PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
|
|
PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
|
|
PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
|
|
PCI: 08:02.0
|
|
PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
|
|
PCI: 08:03.0
|
|
PCI: 00:14.5
|
|
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
|
|
PCI: 00:18.1
|
|
PCI: 00:18.2
|
|
PCI: 00:18.3
|
|
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
|
|
PCI: 00:18.4
|
|
PCI: 00:18.5
|
|
PCI: 00:19.0
|
|
PCI: 00:19.1
|
|
PCI: 00:19.2
|
|
PCI: 00:19.3
|
|
PCI: 00:19.4
|
|
PCI: 00:19.5
|
|
PCI: 00:1a.0
|
|
PCI: 00:1a.1
|
|
PCI: 00:1a.2
|
|
PCI: 00:1a.3
|
|
PCI: 00:1a.4
|
|
PCI: 00:1a.5
|
|
PCI: 00:1b.0
|
|
PCI: 00:1b.1
|
|
PCI: 00:1b.2
|
|
PCI: 00:1b.3
|
|
PCI: 00:1b.4
|
|
PCI: 00:1b.5
|
|
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
|
PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 03:00.0 18 * [0x0 - 0x1f] io
|
|
PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
|
|
PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 04:00.0 18 * [0x0 - 0x1f] io
|
|
PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
|
|
PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
|
PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
|
|
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
|
PCI: 08:01.0 18 * [0x0 - 0x7f] io
|
|
PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
|
|
PCI: 00:09.0 1c * [0x0 - 0xfff] io
|
|
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
|
|
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
|
|
PCI: 00:11.0 20 * [0x3000 - 0x300f] io
|
|
PCI: 00:14.1 20 * [0x3010 - 0x301f] io
|
|
PCI: 00:11.0 10 * [0x3020 - 0x3027] io
|
|
PCI: 00:11.0 18 * [0x3028 - 0x302f] io
|
|
PCI: 00:14.1 10 * [0x3030 - 0x3037] io
|
|
PCI: 00:14.1 18 * [0x3038 - 0x303f] io
|
|
PCI: 00:11.0 14 * [0x3040 - 0x3043] io
|
|
PCI: 00:11.0 1c * [0x3044 - 0x3047] io
|
|
PCI: 00:14.1 14 * [0x3048 - 0x304b] io
|
|
PCI: 00:14.1 1c * [0x304c - 0x304f] io
|
|
PCI: 00:18.0 io: base: 3050 size: 4000 align: 12 gran: 12 limit: ffff done
|
|
PCI: 00:18.0 110d8 * [0x0 - 0x3fff] io
|
|
DOMAIN: 0000 io: base: 4000 size: 4000 align: 12 gran: 0 limit: ffff done
|
|
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
|
PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
|
|
PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:00.0 fc * [0x0 - 0xff] prefmem
|
|
PCI: 00:18.0 prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
|
|
PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem
|
|
PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem
|
|
PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem
|
|
PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem
|
|
PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem
|
|
PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem
|
|
PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem
|
|
PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done
|
|
PCI: 00:14.4 20 * [0x0 - 0x8fffff] mem
|
|
PCI: 00:09.0 20 * [0x900000 - 0x9fffff] mem
|
|
PCI: 00:0a.0 20 * [0xa00000 - 0xafffff] mem
|
|
PCI: 00:00.2 44 * [0xb00000 - 0xb03fff] mem
|
|
PCI: 00:14.2 10 * [0xb04000 - 0xb07fff] mem
|
|
PCI: 00:12.0 10 * [0xb08000 - 0xb08fff] mem
|
|
PCI: 00:12.1 10 * [0xb09000 - 0xb09fff] mem
|
|
PCI: 00:13.0 10 * [0xb0a000 - 0xb0afff] mem
|
|
PCI: 00:13.1 10 * [0xb0b000 - 0xb0bfff] mem
|
|
PCI: 00:14.5 10 * [0xb0c000 - 0xb0cfff] mem
|
|
PCI: 00:11.0 24 * [0xb0d000 - 0xb0d3ff] mem
|
|
PCI: 00:12.2 10 * [0xb0e000 - 0xb0e0ff] mem
|
|
PCI: 00:13.2 10 * [0xb0f000 - 0xb0f0ff] mem
|
|
PCI: 00:14.3 a0 * [0xb10000 - 0xb10000] mem
|
|
PCI: 00:18.0 mem: base: b10001 size: c00000 align: 23 gran: 20 limit: ffffffff done
|
|
PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem
|
|
PCI: 00:18.0 110b8 * [0x4000000 - 0x4bfffff] mem
|
|
PCI: 00:18.0 110b0 * [0x4c00000 - 0x4cfffff] prefmem
|
|
DOMAIN: 0000 mem: base: 4d00000 size: 4d00000 align: 26 gran: 0 limit: ffffffff done
|
|
avoid_fixed_resources: DOMAIN: 0000
|
|
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
|
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
|
constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
|
|
constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
|
|
constrain_resources: DOMAIN: 0000 08 base 838000000 limit 83fffffff mem (fixed)
|
|
constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
|
|
constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed)
|
|
constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
|
|
constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
|
|
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
|
|
constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
|
|
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
|
|
avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff
|
|
Setting resources...
|
|
DOMAIN: 0000 io: base:1000 size:4000 align:12 gran:0 limit:ffff
|
|
PCI: 00:18.0 110d8 * [0x1000 - 0x4fff] io
|
|
DOMAIN: 0000 io: next_base: 5000 size: 4000 align: 12 gran: 0 done
|
|
PCI: 00:18.0 io: base:1000 size:4000 align:12 gran:12 limit:4fff
|
|
PCI: 00:09.0 1c * [0x1000 - 0x1fff] io
|
|
PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
|
|
PCI: 00:14.4 1c * [0x3000 - 0x3fff] io
|
|
PCI: 00:11.0 20 * [0x4000 - 0x400f] io
|
|
PCI: 00:14.1 20 * [0x4010 - 0x401f] io
|
|
PCI: 00:11.0 10 * [0x4020 - 0x4027] io
|
|
PCI: 00:11.0 18 * [0x4028 - 0x402f] io
|
|
PCI: 00:14.1 10 * [0x4030 - 0x4037] io
|
|
PCI: 00:14.1 18 * [0x4038 - 0x403f] io
|
|
PCI: 00:11.0 14 * [0x4040 - 0x4043] io
|
|
PCI: 00:11.0 1c * [0x4044 - 0x4047] io
|
|
PCI: 00:14.1 14 * [0x4048 - 0x404b] io
|
|
PCI: 00:14.1 1c * [0x404c - 0x404f] io
|
|
PCI: 00:18.0 io: next_base: 4050 size: 4000 align: 12 gran: 12 done
|
|
PCI: 00:02.0 io: base:4fff size:0 align:12 gran:12 limit:4fff
|
|
PCI: 00:02.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done
|
|
PCI: 00:04.0 io: base:4fff size:0 align:12 gran:12 limit:4fff
|
|
PCI: 00:04.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done
|
|
PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
|
|
PCI: 03:00.0 18 * [0x1000 - 0x101f] io
|
|
PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
|
|
PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
|
|
PCI: 04:00.0 18 * [0x2000 - 0x201f] io
|
|
PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
|
|
PCI: 00:0b.0 io: base:4fff size:0 align:12 gran:12 limit:4fff
|
|
PCI: 00:0b.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done
|
|
PCI: 00:0c.0 io: base:4fff size:0 align:12 gran:12 limit:4fff
|
|
PCI: 00:0c.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done
|
|
PCI: 00:0d.0 io: base:4fff size:0 align:12 gran:12 limit:4fff
|
|
PCI: 00:0d.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done
|
|
PCI: 00:14.4 io: base:3000 size:1000 align:12 gran:12 limit:3fff
|
|
PCI: 08:01.0 18 * [0x3000 - 0x307f] io
|
|
PCI: 00:14.4 io: next_base: 3080 size: 1000 align: 12 gran: 12 done
|
|
DOMAIN: 0000 mem: base:f8000000 size:4d00000 align:26 gran:0 limit:ffffffff
|
|
PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem
|
|
PCI: 00:18.0 110b8 * [0xfc000000 - 0xfcbfffff] mem
|
|
PCI: 00:18.0 110b0 * [0xfcc00000 - 0xfccfffff] prefmem
|
|
DOMAIN: 0000 mem: next_base: fcd00000 size: 4d00000 align: 26 gran: 0 done
|
|
PCI: 00:18.0 prefmem: base:fcc00000 size:100000 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:00.0 fc * [0xfcc00000 - 0xfcc000ff] prefmem
|
|
PCI: 00:18.0 prefmem: next_base: fcc00100 size: 100000 align: 20 gran: 20 done
|
|
PCI: 00:02.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:02.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:04.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:04.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:09.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:09.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:0a.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:0a.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:0b.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:0b.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:0c.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:0c.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:0d.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:0d.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:14.4 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff
|
|
PCI: 00:14.4 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:18.0 mem: base:fc000000 size:c00000 align:23 gran:20 limit:fcbfffff
|
|
PCI: 00:14.4 20 * [0xfc000000 - 0xfc8fffff] mem
|
|
PCI: 00:09.0 20 * [0xfc900000 - 0xfc9fffff] mem
|
|
PCI: 00:0a.0 20 * [0xfca00000 - 0xfcafffff] mem
|
|
PCI: 00:00.2 44 * [0xfcb00000 - 0xfcb03fff] mem
|
|
PCI: 00:14.2 10 * [0xfcb04000 - 0xfcb07fff] mem
|
|
PCI: 00:12.0 10 * [0xfcb08000 - 0xfcb08fff] mem
|
|
PCI: 00:12.1 10 * [0xfcb09000 - 0xfcb09fff] mem
|
|
PCI: 00:13.0 10 * [0xfcb0a000 - 0xfcb0afff] mem
|
|
PCI: 00:13.1 10 * [0xfcb0b000 - 0xfcb0bfff] mem
|
|
PCI: 00:14.5 10 * [0xfcb0c000 - 0xfcb0cfff] mem
|
|
PCI: 00:11.0 24 * [0xfcb0d000 - 0xfcb0d3ff] mem
|
|
PCI: 00:12.2 10 * [0xfcb0e000 - 0xfcb0e0ff] mem
|
|
PCI: 00:13.2 10 * [0xfcb0f000 - 0xfcb0f0ff] mem
|
|
PCI: 00:14.3 a0 * [0xfcb10000 - 0xfcb10000] mem
|
|
PCI: 00:18.0 mem: next_base: fcb10001 size: c00000 align: 23 gran: 20 done
|
|
PCI: 00:02.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
|
|
PCI: 00:02.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:04.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
|
|
PCI: 00:04.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:09.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff
|
|
PCI: 03:00.0 10 * [0xfc900000 - 0xfc91ffff] mem
|
|
PCI: 03:00.0 1c * [0xfc920000 - 0xfc923fff] mem
|
|
PCI: 00:09.0 mem: next_base: fc924000 size: 100000 align: 20 gran: 20 done
|
|
PCI: 00:0a.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff
|
|
PCI: 04:00.0 10 * [0xfca00000 - 0xfca1ffff] mem
|
|
PCI: 04:00.0 1c * [0xfca20000 - 0xfca23fff] mem
|
|
PCI: 00:0a.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done
|
|
PCI: 00:0b.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
|
|
PCI: 00:0b.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:0c.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
|
|
PCI: 00:0c.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:0d.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
|
|
PCI: 00:0d.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
|
|
PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff
|
|
PCI: 08:01.0 10 * [0xfc000000 - 0xfc7fffff] mem
|
|
PCI: 08:01.0 14 * [0xfc800000 - 0xfc81ffff] mem
|
|
PCI: 08:02.0 10 * [0xfc820000 - 0xfc820fff] mem
|
|
PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done
|
|
Root Device assign_resources, bus 0 link: 0
|
|
0: mmio_basek=00300000, basek=00400000, limitk=02100000
|
|
DOMAIN: 0000 assign_resources, bus 0 link: 0
|
|
VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
|
|
PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
|
|
PCI: 00:18.0 110b0 <- [0x00fcc00000 - 0x00fccfffff] size 0x00100000 gran 0x14 prefmem <node 0 link 1>
|
|
PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fcbfffff] size 0x00c00000 gran 0x14 mem <node 0 link 1>
|
|
PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io <node 0 link 1>
|
|
PCI: 00:18.0 assign_resources, bus 0 link: 1
|
|
PCI: 00:00.0 sr5690_set_resources
|
|
sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
|
|
PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem <mmconfig>
|
|
sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90
|
|
PCI: 00:00.0 fc <- [0x00fcc00000 - 0x00fcc000ff] size 0x00000100 gran 0x08 prefmem
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
PCI: 00:00.2 44 <- [0x00fcb00000 - 0x00fcb03fff] size 0x00004000 gran 0x0e mem
|
|
PCI: 00:02.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 01 io
|
|
PCI: 00:02.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
PCI: 00:02.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 01 mem
|
|
PCI: 00:04.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 02 io
|
|
PCI: 00:04.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
|
PCI: 00:04.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 02 mem
|
|
PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
|
|
PCI: 00:09.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
|
PCI: 00:09.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 03 mem
|
|
PCI: 00:09.0 assign_resources, bus 3 link: 0
|
|
PCI: 03:00.0 10 <- [0x00fc900000 - 0x00fc91ffff] size 0x00020000 gran 0x11 mem
|
|
PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
|
|
PCI: 03:00.0 1c <- [0x00fc920000 - 0x00fc923fff] size 0x00004000 gran 0x0e mem
|
|
PCI: 00:09.0 assign_resources, bus 3 link: 0
|
|
PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
|
|
PCI: 00:0a.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 04 prefmem
|
|
PCI: 00:0a.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 04 mem
|
|
PCI: 00:0a.0 assign_resources, bus 4 link: 0
|
|
PCI: 04:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem
|
|
PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
|
|
PCI: 04:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem
|
|
PCI: 00:0a.0 assign_resources, bus 4 link: 0
|
|
PCI: 00:0b.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 05 io
|
|
PCI: 00:0b.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 05 prefmem
|
|
PCI: 00:0b.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 05 mem
|
|
PCI: 00:0c.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 06 io
|
|
PCI: 00:0c.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 06 prefmem
|
|
PCI: 00:0c.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 06 mem
|
|
PCI: 00:0d.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 07 io
|
|
PCI: 00:0d.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 07 prefmem
|
|
PCI: 00:0d.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 07 mem
|
|
PCI: 00:11.0 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io
|
|
PCI: 00:11.0 14 <- [0x0000004040 - 0x0000004043] size 0x00000004 gran 0x02 io
|
|
PCI: 00:11.0 18 <- [0x0000004028 - 0x000000402f] size 0x00000008 gran 0x03 io
|
|
PCI: 00:11.0 1c <- [0x0000004044 - 0x0000004047] size 0x00000004 gran 0x02 io
|
|
PCI: 00:11.0 20 <- [0x0000004000 - 0x000000400f] size 0x00000010 gran 0x04 io
|
|
PCI: 00:11.0 24 <- [0x00fcb0d000 - 0x00fcb0d3ff] size 0x00000400 gran 0x0a mem
|
|
PCI: 00:12.0 10 <- [0x00fcb08000 - 0x00fcb08fff] size 0x00001000 gran 0x0c mem
|
|
PCI: 00:12.1 10 <- [0x00fcb09000 - 0x00fcb09fff] size 0x00001000 gran 0x0c mem
|
|
PCI: 00:12.2 10 <- [0x00fcb0e000 - 0x00fcb0e0ff] size 0x00000100 gran 0x08 mem
|
|
PCI: 00:13.0 10 <- [0x00fcb0a000 - 0x00fcb0afff] size 0x00001000 gran 0x0c mem
|
|
PCI: 00:13.1 10 <- [0x00fcb0b000 - 0x00fcb0bfff] size 0x00001000 gran 0x0c mem
|
|
PCI: 00:13.2 10 <- [0x00fcb0f000 - 0x00fcb0f0ff] size 0x00000100 gran 0x08 mem
|
|
PCI: 00:14.0 assign_resources, bus 1 link: 0
|
|
PCI: 00:14.0 assign_resources, bus 1 link: 0
|
|
PCI: 00:14.1 10 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io
|
|
PCI: 00:14.1 14 <- [0x0000004048 - 0x000000404b] size 0x00000004 gran 0x02 io
|
|
PCI: 00:14.1 18 <- [0x0000004038 - 0x000000403f] size 0x00000008 gran 0x03 io
|
|
PCI: 00:14.1 1c <- [0x000000404c - 0x000000404f] size 0x00000004 gran 0x02 io
|
|
PCI: 00:14.1 20 <- [0x0000004010 - 0x000000401f] size 0x00000010 gran 0x04 io
|
|
PCI: 00:14.2 10 <- [0x00fcb04000 - 0x00fcb07fff] size 0x00004000 gran 0x0e mem64
|
|
PCI: 00:14.3 a0 <- [0x00fcb10000 - 0x00fcb10000] size 0x00000001 gran 0x00 mem
|
|
PCI: 00:14.3 assign_resources, bus 0 link: 0
|
|
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
|
|
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
|
|
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
|
|
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
|
|
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
|
|
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
|
|
PCI: 00:14.3 assign_resources, bus 0 link: 0
|
|
PCI: 00:14.4 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 08 io
|
|
PCI: 00:14.4 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 08 prefmem
|
|
PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem
|
|
PCI: 00:14.4 assign_resources, bus 8 link: 0
|
|
PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem
|
|
PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem
|
|
PCI: 08:01.0 18 <- [0x0000003000 - 0x000000307f] size 0x00000080 gran 0x07 io
|
|
PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem
|
|
PCI: 00:14.4 assign_resources, bus 8 link: 0
|
|
PCI: 00:14.5 10 <- [0x00fcb0c000 - 0x00fcb0cfff] size 0x00001000 gran 0x0c mem
|
|
PCI: 00:18.0 assign_resources, bus 0 link: 1
|
|
PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
|
|
PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
|
|
DOMAIN: 0000 assign_resources, bus 0 link: 0
|
|
Root Device assign_resources, bus 0 link: 0
|
|
Done setting resources.
|
|
Show resources in subtree (Root Device)...After assigning values.
|
|
Root Device child on link 0 CPU_CLUSTER: 0
|
|
CPU_CLUSTER: 0 child on link 0 APIC: 00
|
|
APIC: 00
|
|
APIC: 01
|
|
APIC: 02
|
|
APIC: 03
|
|
APIC: 04
|
|
APIC: 05
|
|
APIC: 06
|
|
APIC: 07
|
|
APIC: 08
|
|
APIC: 09
|
|
APIC: 0a
|
|
APIC: 0b
|
|
APIC: 0c
|
|
APIC: 0d
|
|
APIC: 0e
|
|
APIC: 0f
|
|
DOMAIN: 0000 child on link 0 PCI: 00:18.0
|
|
DOMAIN: 0000 resource base 1000 size 4000 align 12 gran 0 limit ffff flags 40040100 index 10000000
|
|
DOMAIN: 0000 resource base f8000000 size 4d00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100
|
|
DOMAIN: 0000 resource base c0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags f0000200 index c0010058
|
|
DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
|
|
DOMAIN: 0000 resource base 838000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
|
|
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
|
|
DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
|
|
DOMAIN: 0000 resource base 100000000 size 740000000 align 0 gran 0 limit 0 flags e0004200 index 30
|
|
PCI: 00:18.0
|
|
PCI: 00:18.0 resource base fcc00000 size 100000 align 20 gran 20 limit fccfffff flags 60081200 index 110b0
|
|
PCI: 00:18.0 resource base fc000000 size c00000 align 23 gran 20 limit fcbfffff flags 60080200 index 110b8
|
|
PCI: 00:18.0 resource base 1000 size 4000 align 12 gran 12 limit 4fff flags 60080100 index 110d8
|
|
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8
|
|
PCI: 00:00.0
|
|
PCI: 00:00.0 resource base fcc00000 size 100 align 12 gran 8 limit fcc000ff flags 60001200 index fc
|
|
PCI: 00:00.1
|
|
PCI: 00:00.2
|
|
PCI: 00:00.2 resource base fcb00000 size 4000 align 14 gran 14 limit fcb03fff flags 70000200 index 44
|
|
PCI: 00:02.0
|
|
PCI: 00:02.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c
|
|
PCI: 00:02.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:02.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
|
|
PCI: 00:03.0
|
|
PCI: 00:04.0
|
|
PCI: 00:04.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c
|
|
PCI: 00:04.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:04.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
|
|
PCI: 00:05.0
|
|
PCI: 00:06.0
|
|
PCI: 00:07.0
|
|
PCI: 00:08.0
|
|
PCI: 00:09.0 child on link 0 PCI: 03:00.0
|
|
PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
|
|
PCI: 00:09.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:09.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20
|
|
PCI: 03:00.0
|
|
PCI: 03:00.0 resource base fc900000 size 20000 align 17 gran 17 limit fc91ffff flags 60000200 index 10
|
|
PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
|
|
PCI: 03:00.0 resource base fc920000 size 4000 align 14 gran 14 limit fc923fff flags 60000200 index 1c
|
|
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
|
|
PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
|
|
PCI: 00:0a.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:0a.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20
|
|
PCI: 04:00.0
|
|
PCI: 04:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10
|
|
PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
|
|
PCI: 04:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c
|
|
PCI: 00:0b.0
|
|
PCI: 00:0b.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c
|
|
PCI: 00:0b.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:0b.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
|
|
PCI: 00:0c.0
|
|
PCI: 00:0c.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c
|
|
PCI: 00:0c.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:0c.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
|
|
PCI: 00:0d.0
|
|
PCI: 00:0d.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c
|
|
PCI: 00:0d.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:0d.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
|
|
PCI: 00:11.0
|
|
PCI: 00:11.0 resource base 4020 size 8 align 3 gran 3 limit 4027 flags 60000100 index 10
|
|
PCI: 00:11.0 resource base 4040 size 4 align 2 gran 2 limit 4043 flags 60000100 index 14
|
|
PCI: 00:11.0 resource base 4028 size 8 align 3 gran 3 limit 402f flags 60000100 index 18
|
|
PCI: 00:11.0 resource base 4044 size 4 align 2 gran 2 limit 4047 flags 60000100 index 1c
|
|
PCI: 00:11.0 resource base 4000 size 10 align 4 gran 4 limit 400f flags 60000100 index 20
|
|
PCI: 00:11.0 resource base fcb0d000 size 400 align 12 gran 10 limit fcb0d3ff flags 60000200 index 24
|
|
PCI: 00:12.0
|
|
PCI: 00:12.0 resource base fcb08000 size 1000 align 12 gran 12 limit fcb08fff flags 60000200 index 10
|
|
PCI: 00:12.1
|
|
PCI: 00:12.1 resource base fcb09000 size 1000 align 12 gran 12 limit fcb09fff flags 60000200 index 10
|
|
PCI: 00:12.2
|
|
PCI: 00:12.2 resource base fcb0e000 size 100 align 12 gran 8 limit fcb0e0ff flags 60000200 index 10
|
|
PCI: 00:13.0
|
|
PCI: 00:13.0 resource base fcb0a000 size 1000 align 12 gran 12 limit fcb0afff flags 60000200 index 10
|
|
PCI: 00:13.1
|
|
PCI: 00:13.1 resource base fcb0b000 size 1000 align 12 gran 12 limit fcb0bfff flags 60000200 index 10
|
|
PCI: 00:13.2
|
|
PCI: 00:13.2 resource base fcb0f000 size 100 align 12 gran 8 limit fcb0f0ff flags 60000200 index 10
|
|
PCI: 00:14.0 child on link 0 I2C: 01:50
|
|
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
|
|
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
|
|
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
|
|
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
|
|
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
|
|
I2C: 01:50
|
|
I2C: 01:51
|
|
I2C: 01:52
|
|
I2C: 01:53
|
|
I2C: 01:54
|
|
I2C: 01:55
|
|
I2C: 01:56
|
|
I2C: 01:57
|
|
I2C: 01:2f
|
|
PCI: 00:14.1
|
|
PCI: 00:14.1 resource base 4030 size 8 align 3 gran 3 limit 4037 flags 60000100 index 10
|
|
PCI: 00:14.1 resource base 4048 size 4 align 2 gran 2 limit 404b flags 60000100 index 14
|
|
PCI: 00:14.1 resource base 4038 size 8 align 3 gran 3 limit 403f flags 60000100 index 18
|
|
PCI: 00:14.1 resource base 404c size 4 align 2 gran 2 limit 404f flags 60000100 index 1c
|
|
PCI: 00:14.1 resource base 4010 size 10 align 4 gran 4 limit 401f flags 60000100 index 20
|
|
PCI: 00:14.2
|
|
PCI: 00:14.2 resource base fcb04000 size 4000 align 14 gran 14 limit fcb07fff flags 60000201 index 10
|
|
PCI: 00:14.3 child on link 0 PNP: 002e.0
|
|
PCI: 00:14.3 resource base fcb10000 size 1 align 12 gran 0 limit fcb10000 flags 60000200 index a0
|
|
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
|
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
|
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
|
PNP: 002e.0
|
|
PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
|
|
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
|
|
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
|
|
PNP: 002e.1
|
|
PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
|
|
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
|
|
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
|
|
PNP: 002e.2
|
|
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
|
|
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
|
|
PNP: 002e.3
|
|
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
|
|
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
|
|
PNP: 002e.5
|
|
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
|
|
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
|
|
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
|
|
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
|
|
PNP: 002e.106
|
|
PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
|
|
PNP: 002e.107
|
|
PNP: 002e.207
|
|
PNP: 002e.307
|
|
PNP: 002e.407
|
|
PNP: 002e.8
|
|
PNP: 002e.108
|
|
PNP: 002e.9
|
|
PNP: 002e.109
|
|
PNP: 002e.209
|
|
PNP: 002e.309
|
|
PNP: 002e.a
|
|
PNP: 002e.b
|
|
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
|
|
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
|
|
PNP: 002e.c
|
|
PNP: 002e.d
|
|
PNP: 002e.f
|
|
PCI: 00:14.4 child on link 0 PCI: 08:01.0
|
|
PCI: 00:14.4 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
|
|
PCI: 00:14.4 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24
|
|
PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20
|
|
PCI: 08:01.0
|
|
PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10
|
|
PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14
|
|
PCI: 08:01.0 resource base 3000 size 80 align 7 gran 7 limit 307f flags 60000100 index 18
|
|
PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
|
|
PCI: 08:02.0
|
|
PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10
|
|
PCI: 08:03.0
|
|
PCI: 00:14.5
|
|
PCI: 00:14.5 resource base fcb0c000 size 1000 align 12 gran 12 limit fcb0cfff flags 60000200 index 10
|
|
PCI: 00:18.1
|
|
PCI: 00:18.2
|
|
PCI: 00:18.3
|
|
PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94
|
|
PCI: 00:18.4
|
|
PCI: 00:18.5
|
|
PCI: 00:19.0
|
|
PCI: 00:19.1
|
|
PCI: 00:19.2
|
|
PCI: 00:19.3
|
|
PCI: 00:19.4
|
|
PCI: 00:19.5
|
|
PCI: 00:1a.0
|
|
PCI: 00:1a.1
|
|
PCI: 00:1a.2
|
|
PCI: 00:1a.3
|
|
PCI: 00:1a.4
|
|
PCI: 00:1a.5
|
|
PCI: 00:1b.0
|
|
PCI: 00:1b.1
|
|
PCI: 00:1b.2
|
|
PCI: 00:1b.3
|
|
PCI: 00:1b.4
|
|
PCI: 00:1b.5
|
|
Done allocating resources.
|
|
BS: BS_DEV_RESOURCES times (us): entry 0 run 2240014 exit 0
|
|
POST: 0x74
|
|
Enabling resources...
|
|
PCI: 00:18.0 cmd <- 00
|
|
PCI: 00:18.1 subsystem <- 1043/8163
|
|
PCI: 00:18.1 cmd <- 00
|
|
PCI: 00:18.2 subsystem <- 1043/8163
|
|
PCI: 00:18.2 cmd <- 00
|
|
PCI: 00:18.3 cmd <- 00
|
|
PCI: 00:18.4 cmd <- 00
|
|
PCI: 00:18.5 cmd <- 00
|
|
PCI: 00:19.0 cmd <- 00
|
|
PCI: 00:19.1 subsystem <- 1043/8163
|
|
PCI: 00:19.1 cmd <- 00
|
|
PCI: 00:19.2 subsystem <- 1043/8163
|
|
PCI: 00:19.2 cmd <- 00
|
|
PCI: 00:19.3 cmd <- 00
|
|
PCI: 00:19.4 cmd <- 00
|
|
PCI: 00:19.5 cmd <- 00
|
|
PCI: 00:00.0 subsystem <- 1043/8163
|
|
PCI: 00:00.0 cmd <- 02
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Initializing IOMMU
|
|
PCI: 00:02.0 bridge ctrl <- 0003
|
|
PCI: 00:02.0 cmd <- 00
|
|
PCI: 00:04.0 bridge ctrl <- 0003
|
|
PCI: 00:04.0 cmd <- 00
|
|
PCI: 00:09.0 bridge ctrl <- 0003
|
|
PCI: 00:09.0 cmd <- 07
|
|
PCI: 00:0a.0 bridge ctrl <- 0003
|
|
PCI: 00:0a.0 cmd <- 07
|
|
PCI: 00:0b.0 bridge ctrl <- 0003
|
|
PCI: 00:0b.0 cmd <- 00
|
|
PCI: 00:0c.0 bridge ctrl <- 0003
|
|
PCI: 00:0c.0 cmd <- 00
|
|
PCI: 00:0d.0 bridge ctrl <- 0003
|
|
PCI: 00:0d.0 cmd <- 00
|
|
PCI: 00:11.0 subsystem <- 1043/8163
|
|
PCI: 00:11.0 cmd <- 03
|
|
PCI: 00:12.0 subsystem <- 1043/8163
|
|
PCI: 00:12.0 cmd <- 02
|
|
PCI: 00:12.1 subsystem <- 1043/8163
|
|
PCI: 00:12.1 cmd <- 02
|
|
PCI: 00:12.2 subsystem <- 1043/8163
|
|
PCI: 00:12.2 cmd <- 02
|
|
PCI: 00:13.0 subsystem <- 1043/8163
|
|
PCI: 00:13.0 cmd <- 02
|
|
PCI: 00:13.1 subsystem <- 1043/8163
|
|
PCI: 00:13.1 cmd <- 02
|
|
PCI: 00:13.2 subsystem <- 1043/8163
|
|
PCI: 00:13.2 cmd <- 02
|
|
PCI: 00:14.0 subsystem <- 1043/8163
|
|
PCI: 00:14.0 cmd <- 403
|
|
PCI: 00:14.1 subsystem <- 1043/8163
|
|
PCI: 00:14.1 cmd <- 01
|
|
PCI: 00:14.2 subsystem <- 1043/8163
|
|
PCI: 00:14.2 cmd <- 02
|
|
PCI: 00:14.3 subsystem <- 1043/8163
|
|
PCI: 00:14.3 cmd <- 0f
|
|
sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
|
|
sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
|
|
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
|
|
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
|
|
sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
|
|
PCI: 00:14.4 bridge ctrl <- 000b
|
|
PCI: 00:14.4 cmd <- 07
|
|
PCI: 00:14.5 subsystem <- 1043/8163
|
|
PCI: 00:14.5 cmd <- 02
|
|
PCI: 03:00.0 cmd <- 03
|
|
PCI: 04:00.0 cmd <- 03
|
|
PCI: 08:01.0 cmd <- 03
|
|
PCI: 08:02.0 subsystem <- 1043/8163
|
|
PCI: 08:02.0 cmd <- 02
|
|
done.
|
|
BS: BS_DEV_ENABLE times (us): entry 0 run 113048 exit 0
|
|
POST: 0x75
|
|
Initializing devices...
|
|
Root Device init ...
|
|
Root Device init finished in 1061 usecs
|
|
POST: 0x75
|
|
CPU_CLUSTER: 0 init ...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Enabling probe filter
|
|
Enabling ATM mode
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
start_eip=0x00001000, code_size=0x00000031
|
|
CPU1: stack_base 0014f000, stack_end 0014fff8
|
|
Asserting INIT.
|
|
Waiting for send to finish...
|
|
+Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+#startup loops: 1.
|
|
Sending STARTUP #1 to 1.
|
|
After apic_write.
|
|
Initializing CPU #1
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
After Startup.
|
|
CPU: family 15, model 01, stepping 02
|
|
CPU2: stack_base 0014e000, stack_end 0014eff8
|
|
nodeid = 00, coreid = 01
|
|
Asserting INIT.
|
|
POST: 0x60
|
|
Waiting for send to finish...
|
|
+Enabling cache
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+#startup loops: 1.
|
|
Sending STARTUP #1 to 2.
|
|
After apic_write.
|
|
Initializing CPU #2
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
After Startup.
|
|
CPU3: stack_base 0014d000, stack_end 0014dff8
|
|
CPU: family 15, model 01, stepping 02
|
|
Asserting INIT.
|
|
Waiting for send to finish...
|
|
+nodeid = 00, coreid = 02
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+POST: 0x60
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 3.
|
|
After apic_write.
|
|
Enabling cache
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+Initializing CPU #3
|
|
After Startup.
|
|
CPU4: stack_base 0014c000, stack_end 0014cff8
|
|
CPU: vendor AMD device 600f12
|
|
Asserting INIT.
|
|
CPU: family 15, model 01, stepping 02
|
|
Waiting for send to finish...
|
|
+nodeid = 00, coreid = 03
|
|
Deasserting INIT.
|
|
POST: 0x60
|
|
Waiting for send to finish...
|
|
+Enabling cache
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 4.
|
|
After apic_write.
|
|
CPU ID 0x80000001: 600f12
|
|
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+MTRR: Physical address space:
|
|
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
|
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
|
0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
|
|
0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
|
|
0x0000000100000000 - 0x0000000840000000 size 0x740000000 type 6
|
|
After Startup.
|
|
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
CPU5: stack_base 0014b000, stack_end 0014bff8
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
Asserting INIT.
|
|
Waiting for send to finish...
|
|
+Initializing CPU #4
|
|
Deasserting INIT.
|
|
MTRR: default type WB/UC MTRR counts: 1/2.
|
|
Waiting for send to finish...
|
|
+MTRR: WB selected as default type.
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 5.
|
|
After apic_write.
|
|
MTRR: 0 base 0x00000000c0000000 mask 0x0000ffffc0000000 type 0
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: After Startup.
|
|
Enabled
|
|
|
|
POST: 0x93
|
|
CPU6: stack_base 0014a000, stack_end 0014aff8
|
|
Setting up local apic...Asserting INIT.
|
|
apic_id: 0x02 done.
|
|
POST: 0x9b
|
|
Waiting for send to finish...
|
|
+CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
Deasserting INIT.
|
|
siblings = 15, Waiting for send to finish...
|
|
+Disabling SMM ASeg memory
|
|
#startup loops: 1.
|
|
CPU #2 initialized
|
|
Sending STARTUP #1 to 6.
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
After apic_write.
|
|
CPU: vendor AMD device 600f12
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+Setting up local apic...After Startup.
|
|
apic_id: 0x03 done.
|
|
POST: 0x9b
|
|
CPU7: stack_base 00149000, stack_end 00149ff8
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
Asserting INIT.
|
|
siblings = 15, Waiting for send to finish...
|
|
Disabling SMM ASeg memory
|
|
+CPU #3 initialized
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+CPU: family 15, model 01, stepping 02
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 7.
|
|
After apic_write.
|
|
Initializing CPU #5
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
After Startup.
|
|
CPU8: stack_base 00148000, stack_end 00148ff8
|
|
nodeid = 00, coreid = 04
|
|
Asserting INIT.
|
|
POST: 0x60
|
|
Waiting for send to finish...
|
|
+Initializing CPU #7
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+CPU: family 15, model 01, stepping 02
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 8.
|
|
After apic_write.
|
|
Enabling cache
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
After Startup.
|
|
CPU9: stack_base 00147000, stack_end 00147ff8
|
|
CPU: family 15, model 01, stepping 02
|
|
Asserting INIT.
|
|
nodeid = 00, coreid = 05
|
|
Waiting for send to finish...
|
|
+POST: 0x60
|
|
Deasserting INIT.
|
|
Initializing CPU #8
|
|
Waiting for send to finish...
|
|
+Initializing CPU #6
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 9.
|
|
CPU: vendor AMD device 600f12
|
|
After apic_write.
|
|
Enabling cache
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
CPU ID 0x80000001: 600f12
|
|
+CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
After Startup.
|
|
CPU10: stack_base 00146000, stack_end 00146ff8
|
|
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
Asserting INIT.
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
Waiting for send to finish...
|
|
+nodeid = 00, coreid = 07
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 10.
|
|
|
|
MTRR check
|
|
Fixed MTRRs : After apic_write.
|
|
Enabled
|
|
Variable MTRRs: Enabled
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+
|
|
POST: 0x93
|
|
After Startup.
|
|
CPU11: stack_base 00145000, stack_end 00145ff8
|
|
Setting up local apic...Asserting INIT.
|
|
apic_id: 0x04 done.
|
|
Waiting for send to finish...
|
|
POST: 0x9b
|
|
+CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
Deasserting INIT.
|
|
siblings = 15, Waiting for send to finish...
|
|
+Disabling SMM ASeg memory
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 11.
|
|
|
|
MTRR check
|
|
Fixed MTRRs : After apic_write.
|
|
CPU #4 initialized
|
|
Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+Setting up local apic...After Startup.
|
|
apic_id: 0x05 done.
|
|
POST: 0x9b
|
|
CPU12: stack_base 00144000, stack_end 00144ff8
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
Asserting INIT.
|
|
siblings = 15, Waiting for send to finish...
|
|
Disabling SMM ASeg memory
|
|
+CPU #5 initialized
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+Initializing CPU #11
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 12.
|
|
After apic_write.
|
|
Initializing CPU #10
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
After Startup.
|
|
CPU13: stack_base 00143000, stack_end 00143ff8
|
|
POST: 0x60
|
|
Asserting INIT.
|
|
Waiting for send to finish...
|
|
+CPU: family 15, model 01, stepping 02
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+CPU: family 15, model 01, stepping 02
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 13.
|
|
After apic_write.
|
|
nodeid = 00, coreid = 06
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+Initializing CPU #9
|
|
After Startup.
|
|
CPU14: stack_base 00142000, stack_end 00142ff8
|
|
Initializing CPU #12
|
|
Asserting INIT.
|
|
Waiting for send to finish...
|
|
+Enabling cache
|
|
Deasserting INIT.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 14.
|
|
After apic_write.
|
|
POST: 0x60
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+Enabling cache
|
|
After Startup.
|
|
CPU15: stack_base 00141000, stack_end 00141ff8
|
|
CPU ID 0x80000001: 600f12
|
|
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
Asserting INIT.
|
|
Waiting for send to finish...
|
|
+MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
Deasserting INIT.
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
Waiting for send to finish...
|
|
+MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
#startup loops: 1.
|
|
Sending STARTUP #1 to 15.
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
After apic_write.
|
|
CPU: vendor AMD device 600f12
|
|
Startup point 1.
|
|
Waiting for send to finish...
|
|
+CPU: vendor AMD device 600f12
|
|
After Startup.
|
|
Initializing CPU #0
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
CPU: vendor AMD device 600f12
|
|
CPU: family 15, model 01, stepping 02
|
|
Variable MTRRs: Enabled
|
|
nodeid = 00, coreid = 00
|
|
|
|
POST: 0x93
|
|
POST: 0x60
|
|
Enabling cache
|
|
Initializing CPU #14
|
|
Setting up local apic...CPU ID 0x80000001: 600f12
|
|
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
apic_id: 0x06 done.
|
|
POST: 0x9b
|
|
nodeid = 01, coreid = 02
|
|
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
siblings = 15, MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
Disabling SMM ASeg memory
|
|
CPU: family 15, model 01, stepping 02
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
CPU #6 initialized
|
|
POST: 0x93
|
|
Setting up local apic...Initializing CPU #15
|
|
apic_id: 0x07 done.
|
|
POST: 0x9b
|
|
Setting up local apic...CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
apic_id: 0x00 siblings = 15, done.
|
|
Disabling SMM ASeg memory
|
|
POST: 0x9b
|
|
CPU #7 initialized
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
CPU: family 15, model 01, stepping 02
|
|
siblings = 15, Initializing CPU #13
|
|
Disabling SMM ASeg memory
|
|
CPU: family 15, model 01, stepping 02
|
|
CPU #0 initialized
|
|
Waiting for 9 CPUS to stop
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
CPU: vendor AMD device 600f12
|
|
nodeid = 01, coreid = 04
|
|
Setting up local apic...CPU: family 15, model 01, stepping 02
|
|
apic_id: 0x01 done.
|
|
POST: 0x9b
|
|
CPU: vendor AMD device 600f12
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
CPU: family 15, model 01, stepping 02
|
|
siblings = 15, nodeid = 01, coreid = 03
|
|
Disabling SMM ASeg memory
|
|
CPU: family 15, model 01, stepping 02
|
|
CPU #1 initialized
|
|
Waiting for 8 CPUS to stop
|
|
POST: 0x60
|
|
POST: 0x60
|
|
CPU: vendor AMD device 600f12
|
|
Enabling cache
|
|
nodeid = 01, coreid = 06
|
|
POST: 0x60
|
|
POST: 0x60
|
|
nodeid = 01, coreid = 05
|
|
CPU ID 0x80000001: 600f12
|
|
Enabling cache
|
|
POST: 0x60
|
|
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
nodeid = 01, coreid = 00
|
|
CPU: family 15, model 01, stepping 02
|
|
CPU ID 0x80000001: 600f12
|
|
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
POST: 0x60
|
|
Enabling cache
|
|
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
nodeid = 01, coreid = 07
|
|
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
POST: 0x60
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
Setting up local apic...nodeid = 01, coreid = 01
|
|
apic_id: 0x0c done.
|
|
POST: 0x9b
|
|
Enabling cache
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
siblings = 15, POST: 0x60
|
|
Disabling SMM ASeg memory
|
|
Enabling cache
|
|
CPU #12 initialized
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
Setting up local apic...Waiting for 7 CPUS to stop
|
|
apic_id: 0x0d done.
|
|
POST: 0x9b
|
|
Setting up local apic...CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
apic_id: 0x0e done.
|
|
POST: 0x9b
|
|
siblings = 15, CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
Disabling SMM ASeg memory
|
|
siblings = 15, CPU #13 initialized
|
|
Disabling SMM ASeg memory
|
|
Waiting for 6 CPUS to stop
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
Enabling cache
|
|
CPU ID 0x80000001: 600f12
|
|
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
CPU #14 initialized
|
|
Setting up local apic...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
apic_id: 0x0f done.
|
|
POST: 0x9b
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
Waiting for 5 CPUS to stop
|
|
siblings = 15, Enabling cache
|
|
Disabling SMM ASeg memory
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
CPU #15 initialized
|
|
Enabling cache
|
|
Waiting for 4 CPUS to stop
|
|
CPU ID 0x80000001: 600f12
|
|
Setting up local apic...CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
|
|
apic_id: 0x0a done.
|
|
POST: 0x9b
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
|
|
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
|
|
siblings = 15, Disabling SMM ASeg memory
|
|
CPU #10 initialized
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
Waiting for 3 CPUS to stop
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
Setting up local apic... apic_id: 0x0b done.
|
|
POST: 0x9b
|
|
Setting up local apic...CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
apic_id: 0x08 done.
|
|
siblings = 15, POST: 0x9b
|
|
Disabling SMM ASeg memory
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
CPU #11 initialized
|
|
siblings = 15, Waiting for 2 CPUS to stop
|
|
Disabling SMM ASeg memory
|
|
CPU #8 initialized
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
POST: 0x93
|
|
Waiting for 1 CPUS to stop
|
|
Setting up local apic... apic_id: 0x09 done.
|
|
POST: 0x9b
|
|
CPU model: AMD Opteron(tm) Processor 6262 HE
|
|
siblings = 15, Disabling SMM ASeg memory
|
|
CPU #9 initialized
|
|
All AP CPUs stopped (35304 loops)
|
|
CPU0: stack: 00150000 - 00151000, lowest used address 001509e0, stack used: 1568 bytes
|
|
CPU1: stack: 0014f000 - 00150000, lowest used address 0014fdd8, stack used: 552 bytes
|
|
CPU2: stack: 0014e000 - 0014f000, lowest used address 0014ec9c, stack used: 868 bytes
|
|
CPU3: stack: 0014d000 - 0014e000, lowest used address 0014ddd8, stack used: 552 bytes
|
|
CPU4: stack: 0014c000 - 0014d000, lowest used address 0014cd18, stack used: 744 bytes
|
|
CPU5: stack: 0014b000 - 0014c000, lowest used address 0014bdd8, stack used: 552 bytes
|
|
CPU6: stack: 0014a000 - 0014b000, lowest used address 0014ad18, stack used: 744 bytes
|
|
CPU7: stack: 00149000 - 0014a000, lowest used address 00149dd8, stack used: 552 bytes
|
|
CPU8: stack: 00148000 - 00149000, lowest used address 00148d18, stack used: 744 bytes
|
|
CPU9: stack: 00147000 - 00148000, lowest used address 00147dd8, stack used: 552 bytes
|
|
CPU10: stack: 00146000 - 00147000, lowest used address 00146d18, stack used: 744 bytes
|
|
CPU11: stack: 00145000 - 00146000, lowest used address 00145dd8, stack used: 552 bytes
|
|
CPU12: stack: 00144000 - 00145000, lowest used address 00144d18, stack used: 744 bytes
|
|
CPU13: stack: 00143000 - 00144000, lowest used address 00143dd8, stack used: 552 bytes
|
|
CPU14: stack: 00142000 - 00143000, lowest used address 00142d18, stack used: 744 bytes
|
|
CPU15: stack: 00141000 - 00142000, lowest used address 00141dd8, stack used: 552 bytes
|
|
CPU_CLUSTER: 0 init finished in 849181 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
PCI: 00:18.0 init ...
|
|
PCI: 00:18.0 init finished in 1109 usecs
|
|
POST: 0x75
|
|
PCI: 00:18.1 init ...
|
|
PCI: 00:18.1 init finished in 1108 usecs
|
|
POST: 0x75
|
|
PCI: 00:18.2 init ...
|
|
PCI: 00:18.2 init finished in 1108 usecs
|
|
POST: 0x75
|
|
PCI: 00:18.3 init ...
|
|
NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done.
|
|
PCI: 00:18.3 init finished in 9759 usecs
|
|
POST: 0x75
|
|
PCI: 00:18.4 init ...
|
|
NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done.
|
|
PCI: 00:18.4 init finished in 16481 usecs
|
|
POST: 0x75
|
|
PCI: 00:18.5 init ...
|
|
NB: Function 5 Northbridge Control.. done.
|
|
PCI: 00:18.5 init finished in 3232 usecs
|
|
POST: 0x75
|
|
PCI: 00:19.0 init ...
|
|
PCI: 00:19.0 init finished in 1109 usecs
|
|
POST: 0x75
|
|
PCI: 00:19.1 init ...
|
|
PCI: 00:19.1 init finished in 1109 usecs
|
|
POST: 0x75
|
|
PCI: 00:19.2 init ...
|
|
PCI: 00:19.2 init finished in 1109 usecs
|
|
POST: 0x75
|
|
PCI: 00:19.3 init ...
|
|
NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done.
|
|
PCI: 00:19.3 init finished in 9763 usecs
|
|
POST: 0x75
|
|
PCI: 00:19.4 init ...
|
|
NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
done.
|
|
PCI: 00:19.4 init finished in 16472 usecs
|
|
POST: 0x75
|
|
PCI: 00:19.5 init ...
|
|
NB: Function 5 Northbridge Control.. done.
|
|
PCI: 00:19.5 init finished in 3232 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
PCI: 00:00.0 init ...
|
|
pcie_init in sr5650_ht.c
|
|
IOAPIC: Initializing IOAPIC at 0xfcc00000
|
|
IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
IOAPIC: ID = 0x01
|
|
IOAPIC: Dumping registers
|
|
reg 0x0000: 0x01000000
|
|
reg 0x0001: 0x001f8021
|
|
reg 0x0002: 0x00000000
|
|
IOAPIC: 32 interrupts
|
|
IOAPIC: Enabling interrupts on FSB
|
|
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
|
|
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
|
|
PCI: 00:00.0 init finished in 95375 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
PCI: 00:11.0 init ...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
rev_id=15
|
|
sata_bar0=4020
|
|
sata_bar1=4040
|
|
sata_bar2=4028
|
|
sata_bar3=4044
|
|
sata_bar4=4000
|
|
sata_bar5=fcb0d000
|
|
ide_bar0=4030
|
|
ide_bar1=4048
|
|
ide_bar2=4038
|
|
ide_bar3=404c
|
|
Maximum SATA port count supported by silicon: 6
|
|
SATA port 0 status = 23
|
|
0x6=a0, 0x7=80
|
|
drive detection not yet completed, waiting...
|
|
drive detection done after 10 ms
|
|
AHCI device 0 is ready after 1 tries
|
|
SATA port 1 status = 0
|
|
No AHCI SATA drive on Slot1
|
|
SATA port 2 status = 0
|
|
No AHCI SATA drive on Slot2
|
|
SATA port 3 status = 0
|
|
No AHCI SATA drive on Slot3
|
|
SATA port 4 status = 0
|
|
No AHCI SATA drive on Slot4
|
|
SATA port 5 status = 0
|
|
No AHCI SATA drive on Slot5
|
|
PCI: 00:11.0 init finished in 57997 usecs
|
|
POST: 0x75
|
|
PCI: 00:12.0 init ...
|
|
PCI: 00:12.0 init finished in 1126 usecs
|
|
POST: 0x75
|
|
PCI: 00:12.1 init ...
|
|
PCI: 00:12.1 init finished in 1125 usecs
|
|
POST: 0x75
|
|
PCI: 00:12.2 init ...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
usb2_bar0=0xfcb0e000
|
|
rpr 6.23, final dword=849e03c8
|
|
PCI: 00:12.2 init finished in 10643 usecs
|
|
POST: 0x75
|
|
PCI: 00:13.0 init ...
|
|
PCI: 00:13.0 init finished in 1125 usecs
|
|
POST: 0x75
|
|
PCI: 00:13.1 init ...
|
|
PCI: 00:13.1 init finished in 1126 usecs
|
|
POST: 0x75
|
|
PCI: 00:13.2 init ...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
usb2_bar0=0xfcb0f000
|
|
rpr 6.23, final dword=849e03c8
|
|
PCI: 00:13.2 init finished in 10649 usecs
|
|
POST: 0x75
|
|
PCI: 00:14.0 init ...
|
|
sm_init().
|
|
IOAPIC: Initializing IOAPIC at 0xfec00000
|
|
IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
IOAPIC: Dumping registers
|
|
reg 0x0000: 0x00000000
|
|
reg 0x0001: 0x00178021
|
|
reg 0x0002: 0x00000000
|
|
IOAPIC: 24 interrupts
|
|
IOAPIC: Enabling interrupts on FSB
|
|
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
|
|
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
|
|
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
WARNING: No CMOS option 'enable_legacy_usb'.
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
set power "on" after power fail
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
++++++++++no set NMI+++++
|
|
RTC Init
|
|
sm_init() end
|
|
PCI: 00:14.0 init finished in 100609 usecs
|
|
POST: 0x75
|
|
PCI: 00:14.1 init ...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
PCI: 00:14.1 init finished in 7910 usecs
|
|
POST: 0x75
|
|
PCI: 00:14.2 init ...
|
|
base = 0xfcb04000
|
|
No codec!
|
|
PCI: 00:14.2 init finished in 4776 usecs
|
|
POST: 0x75
|
|
PCI: 00:14.3 init ...
|
|
lpc_init
|
|
PCI: 00:14.3 init finished in 1605 usecs
|
|
POST: 0x75
|
|
PCI: 00:14.4 init ...
|
|
PCI: 00:14.4 init finished in 1122 usecs
|
|
POST: 0x75
|
|
PCI: 00:14.5 init ...
|
|
PCI: 00:14.5 init finished in 1126 usecs
|
|
POST: 0x75
|
|
PCI: 03:00.0 init ...
|
|
PCI: 03:00.0 init finished in 1109 usecs
|
|
POST: 0x75
|
|
PCI: 04:00.0 init ...
|
|
PCI: 04:00.0 init finished in 1109 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
|
|
Set SMBUS controller to channel 1
|
|
Found 64 pin W83795G Nuvoton H/W Monitor
|
|
W83795G/ADG work in Thermal Cruise Mode
|
|
Fan CTFS(celsius) TTTI(celsius)
|
|
1 80 80
|
|
2 80 80
|
|
3 80 80
|
|
4 80 80
|
|
5 80 80
|
|
6 80 80
|
|
DTS1 current value: 1e
|
|
DTS2 current value: 0
|
|
DTS3 current value: 0
|
|
DTS4 current value: 0
|
|
DTS5 current value: 0
|
|
DTS6 current value: 0
|
|
DTS7 current value: 0
|
|
DTS8 current value: 0
|
|
Set SMBUS controller to channel 0
|
|
I2C: 01:2f init finished in 215242 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
PNP: 002e.2 init ...
|
|
PNP: 002e.2 init finished in 1060 usecs
|
|
POST: 0x75
|
|
PNP: 002e.3 init ...
|
|
PNP: 002e.3 init finished in 1061 usecs
|
|
POST: 0x75
|
|
PNP: 002e.5 init ...
|
|
Keyboard init...
|
|
PS/2 auxiliary channel detected...
|
|
PS/2 device detected on auxiliary channel
|
|
No PS/2 keyboard detected.
|
|
PNP: 002e.5 init finished in 72921 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
PNP: 002e.a init ...
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
set power on after power fail
|
|
PNP: 002e.a init finished in 9252 usecs
|
|
POST: 0x75
|
|
PNP: 002e.b init ...
|
|
PNP: 002e.b init finished in 1061 usecs
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
POST: 0x75
|
|
PCI: 08:01.0 init ...
|
|
ASpeed AST2050: initializing video device
|
|
ast_detect_chip: AST 1100 detected
|
|
ast_detect_chip: VGA not enabled on entry, requesting chip POST
|
|
ast_detect_chip: Analog VGA only
|
|
ast_driver_load: dram 820800000 0 32 00800000
|
|
ASpeed VGA text mode initialized
|
|
PCI: 08:01.0 init finished in 25401 usecs
|
|
POST: 0x75
|
|
PCI: 08:02.0 init ...
|
|
PCI: 08:02.0 init finished in 1109 usecs
|
|
POST: 0x75
|
|
Devices initialized
|
|
Show all devs... After init.
|
|
Root Device: enabled 1
|
|
CPU_CLUSTER: 0: enabled 1
|
|
APIC: 00: enabled 1
|
|
DOMAIN: 0000: enabled 1
|
|
PCI: 00:18.0: enabled 1
|
|
PCI: 00:00.0: enabled 1
|
|
PCI: 00:00.1: enabled 0
|
|
PCI: 00:00.2: enabled 1
|
|
PCI: 00:02.0: enabled 1
|
|
PCI: 00:03.0: enabled 0
|
|
PCI: 00:04.0: enabled 1
|
|
PCI: 00:05.0: enabled 0
|
|
PCI: 00:06.0: enabled 0
|
|
PCI: 00:07.0: enabled 0
|
|
PCI: 00:08.0: enabled 0
|
|
PCI: 00:09.0: enabled 1
|
|
PCI: 00:0a.0: enabled 1
|
|
PCI: 00:0b.0: enabled 1
|
|
PCI: 00:0c.0: enabled 1
|
|
PCI: 00:0d.0: enabled 1
|
|
PCI: 00:11.0: enabled 1
|
|
PCI: 00:12.0: enabled 1
|
|
PCI: 00:12.1: enabled 1
|
|
PCI: 00:12.2: enabled 1
|
|
PCI: 00:13.0: enabled 1
|
|
PCI: 00:13.1: enabled 1
|
|
PCI: 00:13.2: enabled 1
|
|
PCI: 00:14.0: enabled 1
|
|
I2C: 01:50: enabled 1
|
|
I2C: 01:51: enabled 1
|
|
I2C: 01:52: enabled 1
|
|
I2C: 01:53: enabled 1
|
|
I2C: 01:54: enabled 1
|
|
I2C: 01:55: enabled 1
|
|
I2C: 01:56: enabled 1
|
|
I2C: 01:57: enabled 1
|
|
I2C: 01:2f: enabled 1
|
|
PCI: 00:14.1: enabled 1
|
|
PCI: 00:14.2: enabled 1
|
|
PCI: 00:14.3: enabled 1
|
|
PNP: 002e.0: enabled 0
|
|
PNP: 002e.1: enabled 0
|
|
PNP: 002e.2: enabled 1
|
|
PNP: 002e.3: enabled 1
|
|
PNP: 002e.5: enabled 1
|
|
PNP: 002e.106: enabled 0
|
|
PNP: 002e.107: enabled 0
|
|
PNP: 002e.207: enabled 0
|
|
PNP: 002e.307: enabled 0
|
|
PNP: 002e.407: enabled 0
|
|
PNP: 002e.8: enabled 0
|
|
PNP: 002e.108: enabled 0
|
|
PNP: 002e.9: enabled 0
|
|
PNP: 002e.109: enabled 0
|
|
PNP: 002e.209: enabled 0
|
|
PNP: 002e.309: enabled 0
|
|
PNP: 002e.a: enabled 1
|
|
PNP: 002e.b: enabled 1
|
|
PNP: 002e.c: enabled 0
|
|
PNP: 002e.d: enabled 0
|
|
PNP: 002e.f: enabled 0
|
|
PCI: 00:14.4: enabled 1
|
|
PCI: 08:01.0: enabled 1
|
|
PCI: 08:02.0: enabled 1
|
|
PCI: 08:03.0: enabled 0
|
|
PCI: 00:14.5: enabled 1
|
|
PCI: 00:18.1: enabled 1
|
|
PCI: 00:18.2: enabled 1
|
|
PCI: 00:18.3: enabled 1
|
|
PCI: 00:18.4: enabled 1
|
|
PCI: 00:18.5: enabled 1
|
|
PCI: 00:19.0: enabled 1
|
|
PCI: 00:19.1: enabled 1
|
|
PCI: 00:19.2: enabled 1
|
|
PCI: 00:19.3: enabled 1
|
|
PCI: 00:19.4: enabled 1
|
|
PCI: 00:19.5: enabled 1
|
|
PCI: 00:1a.0: enabled 0
|
|
PCI: 00:1a.1: enabled 0
|
|
PCI: 00:1a.2: enabled 0
|
|
PCI: 00:1a.3: enabled 0
|
|
PCI: 00:1a.4: enabled 0
|
|
PCI: 00:1a.5: enabled 0
|
|
PCI: 00:1b.0: enabled 0
|
|
PCI: 00:1b.1: enabled 0
|
|
PCI: 00:1b.2: enabled 0
|
|
PCI: 00:1b.3: enabled 0
|
|
PCI: 00:1b.4: enabled 0
|
|
PCI: 00:1b.5: enabled 0
|
|
APIC: 01: enabled 1
|
|
APIC: 02: enabled 1
|
|
APIC: 03: enabled 1
|
|
APIC: 04: enabled 1
|
|
APIC: 05: enabled 1
|
|
APIC: 06: enabled 1
|
|
APIC: 07: enabled 1
|
|
APIC: 08: enabled 1
|
|
APIC: 09: enabled 1
|
|
APIC: 0a: enabled 1
|
|
APIC: 0b: enabled 1
|
|
APIC: 0c: enabled 1
|
|
APIC: 0d: enabled 1
|
|
APIC: 0e: enabled 1
|
|
APIC: 0f: enabled 1
|
|
PCI: 03:00.0: enabled 1
|
|
PCI: 04:00.0: enabled 1
|
|
BS: BS_DEV_INIT times (us): entry 0 run 1807717 exit 0
|
|
POST: 0x76
|
|
Finalize devices...
|
|
Devices finalized
|
|
BS: BS_POST_DEVICE times (us): entry 0 run 2515 exit 0
|
|
POST: 0x77
|
|
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 584 exit 0
|
|
POST: 0x79
|
|
POST: 0x9a
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
Writing IRQ routing tables to 0xf0000...done.
|
|
Writing IRQ routing tables to 0xb7cc0000...done.
|
|
PIRQ table: 48 bytes.
|
|
POST: 0x9b
|
|
Wrote the mp table end at: 000f0410 - 000f076c
|
|
Wrote the mp table end at: b7cbf010 - b7cbf36c
|
|
MP table: 876 bytes.
|
|
POST: 0x9c
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'fallback/dsdt.aml'
|
|
CBFS: Found @ offset 2a380 size 256b
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'fallback/slic'
|
|
CBFS: 'fallback/slic' not found.
|
|
ACPI: Writing ACPI tables at b7c9b000.
|
|
ACPI: * FACS
|
|
ACPI: * DSDT
|
|
ACPI: * FADT
|
|
pm_base: 0x0800
|
|
ACPI: added table 1/32, length now 40
|
|
ACPI: * SSDT
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
processor_brand=AMD Opteron(tm) Processor 6262 HE
|
|
Pstates algorithm ...
|
|
Pstate_freq[0] = 1600MHz Pstate_power[0] = 3792mw
|
|
Pstate_latency[0] = 5us
|
|
Pstate_freq[1] = 1500MHz Pstate_power[1] = 3558mw
|
|
Pstate_latency[1] = 5us
|
|
Pstate_freq[2] = 1400MHz Pstate_power[2] = 3195mw
|
|
Pstate_latency[2] = 5us
|
|
Pstate_freq[3] = 1200MHz Pstate_power[3] = 2800mw
|
|
Pstate_latency[3] = 5us
|
|
Pstate_freq[4] = 1000MHz Pstate_power[4] = 2295mw
|
|
Pstate_latency[4] = 5us
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
PSS: 1600MHz power 3792 control 0x0 status 0x0
|
|
PSS: 1500MHz power 3558 control 0x1 status 0x1
|
|
PSS: 1400MHz power 3195 control 0x2 status 0x2
|
|
PSS: 1200MHz power 2800 control 0x3 status 0x3
|
|
PSS: 1000MHz power 2295 control 0x4 status 0x4
|
|
ACPI: added table 2/32, length now 44
|
|
ACPI: * MCFG
|
|
ACPI: added table 3/32, length now 48
|
|
ACPI: * TCPA
|
|
TCPA log created at b7c8b000
|
|
ACPI: added table 4/32, length now 52
|
|
ACPI: * MADT
|
|
ACPI: added table 5/32, length now 56
|
|
current = b7c9f9a0
|
|
ACPI: * SRAT at b7c9f9a0
|
|
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
|
|
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
|
|
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
|
|
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
|
|
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
|
|
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
|
|
SRAT: lapic cpu_index=06, node_id=00, apic_id=06
|
|
SRAT: lapic cpu_index=07, node_id=00, apic_id=07
|
|
SRAT: lapic cpu_index=08, node_id=01, apic_id=08
|
|
SRAT: lapic cpu_index=09, node_id=01, apic_id=09
|
|
SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
|
|
SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
|
|
SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
|
|
SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
|
|
SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
|
|
SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=01d00000
|
|
ACPI: added table 6/32, length now 60
|
|
ACPI: * SLIT at b7c9fb48
|
|
ACPI: added table 7/32, length now 64
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
ACPI: * IVRS at b7c9fb80
|
|
Capability: type 0x01 @ 0xc8
|
|
Capability: type 0x05 @ 0xd0
|
|
Capability: type 0x10 @ 0xe0
|
|
Capability: type 0x01 @ 0xc8
|
|
Capability: type 0x05 @ 0xd0
|
|
Capability: type 0x10 @ 0xe0
|
|
Capability: type 0x01 @ 0x40
|
|
Capability: type 0x01 @ 0x44
|
|
ACPI: added table 8/32, length now 68
|
|
ACPI: * HPET
|
|
ACPI: added table 9/32, length now 72
|
|
ACPI: * SRAT at b7c9fcb0
|
|
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
|
|
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
|
|
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
|
|
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
|
|
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
|
|
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
|
|
SRAT: lapic cpu_index=06, node_id=00, apic_id=06
|
|
SRAT: lapic cpu_index=07, node_id=00, apic_id=07
|
|
SRAT: lapic cpu_index=08, node_id=01, apic_id=08
|
|
SRAT: lapic cpu_index=09, node_id=01, apic_id=09
|
|
SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
|
|
SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
|
|
SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
|
|
SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
|
|
SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
|
|
SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
|
|
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=01d00000
|
|
ACPI: added table 10/32, length now 76
|
|
ACPI: * SLIT at b7c9fe58
|
|
ACPI: added table 11/32, length now 80
|
|
ACPI: done.
|
|
ACPI tables: 20112 bytes.
|
|
smbios_write_tables: b7c8a000
|
|
Root Device (ASUS KGPE-D16)
|
|
CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
|
|
APIC: 00 (unknown)
|
|
DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
|
|
PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:00.0 (ATI SR5650)
|
|
PCI: 00:00.1 (ATI SR5650)
|
|
PCI: 00:00.2 (ATI SR5650)
|
|
PCI: 00:02.0 (ATI SR5650)
|
|
PCI: 00:03.0 (ATI SR5650)
|
|
PCI: 00:04.0 (ATI SR5650)
|
|
PCI: 00:05.0 (ATI SR5650)
|
|
PCI: 00:06.0 (ATI SR5650)
|
|
PCI: 00:07.0 (ATI SR5650)
|
|
PCI: 00:08.0 (ATI SR5650)
|
|
PCI: 00:09.0 (ATI SR5650)
|
|
PCI: 00:0a.0 (ATI SR5650)
|
|
PCI: 00:0b.0 (ATI SR5650)
|
|
PCI: 00:0c.0 (ATI SR5650)
|
|
PCI: 00:0d.0 (ATI SR5650)
|
|
PCI: 00:11.0 (ATI SP5100)
|
|
PCI: 00:12.0 (ATI SP5100)
|
|
PCI: 00:12.1 (ATI SP5100)
|
|
PCI: 00:12.2 (ATI SP5100)
|
|
PCI: 00:13.0 (ATI SP5100)
|
|
PCI: 00:13.1 (ATI SP5100)
|
|
PCI: 00:13.2 (ATI SP5100)
|
|
PCI: 00:14.0 (ATI SP5100)
|
|
I2C: 01:50 (unknown)
|
|
I2C: 01:51 (unknown)
|
|
I2C: 01:52 (unknown)
|
|
I2C: 01:53 (unknown)
|
|
I2C: 01:54 (unknown)
|
|
I2C: 01:55 (unknown)
|
|
I2C: 01:56 (unknown)
|
|
I2C: 01:57 (unknown)
|
|
I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
|
|
PCI: 00:14.1 (ATI SP5100)
|
|
PCI: 00:14.2 (ATI SP5100)
|
|
PCI: 00:14.3 (ATI SP5100)
|
|
PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.a (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.b (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.c (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.d (WINBOND W83667HG-A Super I/O)
|
|
PNP: 002e.f (WINBOND W83667HG-A Super I/O)
|
|
PCI: 00:14.4 (ATI SP5100)
|
|
PCI: 08:01.0 (ATI SP5100)
|
|
PCI: 08:02.0 (ATI SP5100)
|
|
PCI: 08:03.0 (ATI SP5100)
|
|
PCI: 00:14.5 (ATI SP5100)
|
|
PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1a.0 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1a.1 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1a.2 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1a.3 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1a.4 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1a.5 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1b.0 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1b.1 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1b.2 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1b.3 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1b.4 (AMD Family 10h/15h Northbridge)
|
|
PCI: 00:1b.5 (AMD Family 10h/15h Northbridge)
|
|
APIC: 01 (unknown)
|
|
APIC: 02 (unknown)
|
|
APIC: 03 (unknown)
|
|
APIC: 04 (unknown)
|
|
APIC: 05 (unknown)
|
|
APIC: 06 (unknown)
|
|
APIC: 07 (unknown)
|
|
APIC: 08 (unknown)
|
|
APIC: 09 (unknown)
|
|
APIC: 0a (unknown)
|
|
APIC: 0b (unknown)
|
|
APIC: 0c (unknown)
|
|
APIC: 0d (unknown)
|
|
APIC: 0e (unknown)
|
|
APIC: 0f (unknown)
|
|
PCI: 03:00.0 (unknown)
|
|
PCI: 04:00.0 (unknown)
|
|
SMBIOS tables: 530 bytes.
|
|
Writing table forward entry at 0x00000500
|
|
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3812
|
|
Writing coreboot table at 0xb7cc1000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
1. 0000000000001000-000000000009ffff: RAM
|
|
2. 00000000000a0000-00000000000bffff: RESERVED
|
|
3. 00000000000c0000-00000000b7c89fff: RAM
|
|
4. 00000000b7c8a000-00000000b7ffffff: CONFIGURATION TABLES
|
|
5. 00000000b8000000-00000000bfffffff: RAM
|
|
6. 00000000c0000000-00000000cfffffff: RESERVED
|
|
7. 00000000fcb00000-00000000fcb03fff: RESERVED
|
|
8. 00000000feb00000-00000000feb00fff: RESERVED
|
|
9. 00000000fec00000-00000000fec00fff: RESERVED
|
|
10. 00000000fed00000-00000000fed00fff: RESERVED
|
|
11. 0000000100000000-0000000837ffffff: RAM
|
|
12. 0000000838000000-000000083fffffff: RESERVED
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
FMAP: Found "FLASH" version 1.1 at 0.
|
|
FMAP: base = ffe00000 size = 200000 #areas = 3
|
|
Wrote coreboot table at: b7cc1000, 0x11c0 bytes, checksum 3dfb
|
|
coreboot table: 4568 bytes.
|
|
IMD ROOT 0. b7fff000 00001000
|
|
IMD SMALL 1. b7ffe000 00001000
|
|
CAR GLOBALS 2. b7ff3000 0000a480
|
|
CONSOLE 3. b7fd3000 00020000
|
|
AMDMEM INFO 4. b7fc9000 0000919c
|
|
ACPI RESUME 5. b7cc9000 00300000
|
|
COREBOOT 6. b7cc1000 00008000
|
|
IRQ TABLE 7. b7cc0000 00001000
|
|
SMP TABLE 8. b7cbf000 00001000
|
|
ACPI 9. b7c9b000 00024000
|
|
TCPA LOG 10. b7c8b000 00010000
|
|
SMBIOS 11. b7c8a000 00000800
|
|
IMD small region:
|
|
IMD ROOT 0. b7ffec00 00000400
|
|
ROMSTAGE 1. b7ffebe0 00000004
|
|
GDT 2. b7ffe9e0 00000200
|
|
Writing AMD DCT configuration to Flash
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 's3nv'
|
|
CBFS: Found @ offset 2fec0 size 10000
|
|
SF: Detected W25Q16 with sector size 0x1000, total 0x200000
|
|
SF: Successfully erased 32768 bytes @ 0x38000
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'cmos_layout.bin'
|
|
CBFS: Found @ offset 294c0 size e84
|
|
BS: BS_WRITE_TABLES times (us): entry 0 run 1201886 exit 0
|
|
POST: 0x7a
|
|
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
|
|
CBFS: Locating 'fallback/payload'
|
|
CBFS: Found @ offset 54ec0 size e984
|
|
Loading segment from rom address 0xffe54ff8
|
|
code (compression=1)
|
|
New segment dstaddr 0xe41ac memsize 0x1be54 srcaddr 0xffe55030 filesize 0xe94c
|
|
Loading segment from rom address 0xffe55014
|
|
Entry Point 0x000ff06e
|
|
Bounce Buffer at bfdd3000, 2278624 bytes
|
|
Loading Segment: addr: 0x00000000000e41ac memsz: 0x000000000001be54 filesz: 0x000000000000e94c
|
|
lb: [0x0000000000100000, 0x0000000000216270)
|
|
Post relocation: addr: 0x00000000000e41ac memsz: 0x000000000001be54 filesz: 0x000000000000e94c
|
|
using LZMA
|
|
[ 0x000e41ac, 00100000, 0x00100000) <- ffe55030
|
|
dest 000e41ac, end 00100000, bouncebuffer bfdd3000
|
|
Loaded segments
|
|
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 56280 exit 0
|
|
POST: 0x7b
|
|
Jumping to boot code at 000ff06e(b7cc1000)
|
|
POST: 0xf8
|
|
CPU0: stack: 00150000 - 00151000, lowest used address 001509e0, stack used: 1568 bytes
|
|
entry = 0x000ff06e
|
|
lb_start = 0x00100000
|
|
lb_size = 0x00116270
|
|
buffer = 0xbfdd3000
|
|
[ 0.000000] Initializing cgroup subsys cpuset
|
|
[ 0.000000] Initializing cgroup subsys cpu
|
|
[ 0.000000] Initializing cgroup subsys cpuacct
|
|
[ 0.000000] Linux version 3.13.0-37-generic (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #64+7.0trisquel2 SMP Sat Oct 11 02:26:48 UTC 2014 (Ubuntu 3.13.0-37.64+7.0trisquel2-generic 3.13.11.7-gnu)
|
|
[ 0.000000] Command line: initrd=/casper/initrd.netinst vga=788 console=ttyS0,115200n8 console=tty1 BOOT_IMAGE=linux -- BOOT_IMAGE=/casper/vmlinuz.netinst
|
|
[ 0.000000] KERNEL supported cpus:
|
|
[ 0.000000] Intel GenuineIntel
|
|
[ 0.000000] AMD AuthenticAMD
|
|
[ 0.000000] Centaur CentaurHauls
|
|
[ 0.000000] e820: BIOS-provided physical RAM map:
|
|
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009fbff] usable
|
|
[ 0.000000] BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000000f0000-0x00000000000fffff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000b7c89fff] usable
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000b7c8a000-0x00000000b7ffffff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000b8000000-0x00000000bfffcfff] usable
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000bfffd000-0x00000000cfffffff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000fcb00000-0x00000000fcb03fff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000feb00000-0x00000000feb00fff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed00fff] reserved
|
|
[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x0000000837ffffff] usable
|
|
[ 0.000000] BIOS-e820: [mem 0x0000000838000000-0x000000083fffffff] reserved
|
|
[ 0.000000] NX (Execute Disable) protection: active
|
|
[ 0.000000] SMBIOS 2.7 present.
|
|
[ 0.000000] No AGP bridge found
|
|
[ 0.000000] e820: last_pfn = 0x838000 max_arch_pfn = 0x400000000
|
|
[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
|
|
[ 0.000000] e820: last_pfn = 0xbfffd max_arch_pfn = 0x400000000
|
|
[ 0.000000] Scanning 1 areas for low memory corruption
|
|
[ 0.000000] Using GB pages for direct mapping
|
|
[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
|
|
[ 0.000000] init_memory_mapping: [mem 0x837e00000-0x837ffffff]
|
|
[ 0.000000] init_memory_mapping: [mem 0x834000000-0x837dfffff]
|
|
[ 0.000000] init_memory_mapping: [mem 0x800000000-0x833ffffff]
|
|
[ 0.000000] init_memory_mapping: [mem 0x00100000-0xb7c89fff]
|
|
[ 0.000000] init_memory_mapping: [mem 0xb8000000-0xbfffcfff]
|
|
[ 0.000000] init_memory_mapping: [mem 0x100000000-0x7ffffffff]
|
|
[ 0.000000] RAMDISK: [mem 0x7f620000-0x7fffefff]
|
|
[ 0.000000] ACPI: RSDP 00000000000f0c80 000024 (v02 CORE )
|
|
[ 0.000000] ACPI: XSDT 00000000b7c9b0e0 00007C (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: FACP 00000000b7c9d7f0 0000F4 (v03 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: DSDT 00000000b7c9b280 00256B (v03 ASUS COREBOOT 00000001 INTL 20150619)
|
|
[ 0.000000] ACPI: FACS 00000000b7c9b240 000040
|
|
[ 0.000000] ACPI: SSDT 00000000b7c9d8f0 001F4E (v02 CORE COREBOOT 0000002A CORE 0000002A)
|
|
[ 0.000000] ACPI: MCFG 00000000b7c9f840 00003C (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: TCPA 00000000b7c9f880 000032 (v02 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: APIC 00000000b7c9f8c0 0000DE (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: SRAT 00000000b7c9f9a0 0001A8 (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: SLIT 00000000b7c9fb48 000030 (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: IVRS 00000000b7c9fb80 0000E8 (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: HPET 00000000b7c9fc70 000038 (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: SRAT 00000000b7c9fcb0 0001A8 (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] ACPI: SLIT 00000000b7c9fe58 000030 (v01 CORE COREBOOT 00000000 CORE 00000000)
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x00 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x01 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x02 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x03 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x04 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x05 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x06 -> Node 0
|
|
[ 0.000000] SRAT: PXM 0 -> APIC 0x07 -> Node 0
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x08 -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x09 -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x0a -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x0b -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x0c -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x0d -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x0e -> Node 1
|
|
[ 0.000000] SRAT: PXM 1 -> APIC 0x0f -> Node 1
|
|
[ 0.000000] SRAT: Node 0 PXM 0 [mem 0x00000000-0x0009ffff]
|
|
[ 0.000000] SRAT: Node 0 PXM 0 [mem 0x00100000-0xbfffffff]
|
|
[ 0.000000] SRAT: Node 0 PXM 0 [mem 0x100000000-0x83fffffff]
|
|
[ 0.000000] NUMA: Node 0 [mem 0x00000000-0x0009ffff] + [mem 0x00100000-0xbfffffff] -> [mem 0x00000000-0xbfffffff]
|
|
[ 0.000000] NUMA: Node 0 [mem 0x00000000-0xbfffffff] + [mem 0x100000000-0x837ffffff] -> [mem 0x00000000-0x837ffffff]
|
|
[ 0.000000] Initmem setup node 0 [mem 0x00000000-0x837ffffff]
|
|
[ 0.000000] NODE_DATA [mem 0x837ff8000-0x837ffcfff]
|
|
[ 0.000000] Zone ranges:
|
|
[ 0.000000] DMA [mem 0x00001000-0x00ffffff]
|
|
[ 0.000000] DMA32 [mem 0x01000000-0xffffffff]
|
|
[ 0.000000] Normal [mem 0x100000000-0x837ffffff]
|
|
[ 0.000000] Movable zone start for each node
|
|
[ 0.000000] Early memory node ranges
|
|
[ 0.000000] node 0: [mem 0x00001000-0x0009efff]
|
|
[ 0.000000] node 0: [mem 0x00100000-0xb7c89fff]
|
|
[ 0.000000] node 0: [mem 0xb8000000-0xbfffcfff]
|
|
[ 0.000000] node 0: [mem 0x100000000-0x837ffffff]
|
|
[ 0.000000] ACPI: PM-Timer IO Port: 0x820
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x04] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x05] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x06] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x07] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x08] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x09] lapic_id[0x09] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x0a] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x0b] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x0c] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x0d] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x0e] enabled)
|
|
[ 0.000000] ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x0f] enabled)
|
|
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0xff] dfl dfl lint[0x1])
|
|
[ 0.000000] ACPI: IOAPIC (id[0x20] address[0xfec00000] gsi_base[0])
|
|
[ 0.000000] IOAPIC[0]: apic_id 32, version 33, address 0xfec00000, GSI 0-23
|
|
[ 0.000000] ACPI: IOAPIC (id[0x21] address[0xfcc00000] gsi_base[24])
|
|
[ 0.000000] IOAPIC[1]: apic_id 33, version 33, address 0xfcc00000, GSI 24-55
|
|
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
|
|
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
|
|
[ 0.000000] Using ACPI (MADT) for SMP configuration information
|
|
[ 0.000000] ACPI: HPET id: 0x43538301 base: 0xfed00000
|
|
[ 0.000000] smpboot: Allowing 16 CPUs, 0 hotplug CPUs
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000effff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0x000f0000-0x000fffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xb7c8a000-0xb7ffffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xbfffd000-0xcfffffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xd0000000-0xfcafffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfcb00000-0xfcb03fff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfcb04000-0xfeafffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfeb00000-0xfeb00fff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfeb01000-0xfebfffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfecfffff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfed00000-0xfed00fff]
|
|
[ 0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xffffffff]
|
|
[ 0.000000] e820: [mem 0xd0000000-0xfcafffff] available for PCI devices
|
|
[ 0.000000] Booting paravirtualized kernel on bare hardware
|
|
[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:16 nr_node_ids:2
|
|
[ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff880837c00000 s86400 r8192 d24192 u131072
|
|
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 8224285
|
|
[ 0.000000] Policy zone: Normal
|
|
[ 0.000000] Kernel command line: initrd=/casper/initrd.netinst vga=788 console=ttyS0,115200n8 console=tty1 BOOT_IMAGE=linux -- BOOT_IMAGE=/casper/vmlinuz.netinst
|
|
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
|
|
[ 0.000000] xsave: enabled xstate_bv 0x7, cntxt size 0x340
|
|
[ 0.000000] Checking aperture...
|
|
[ 0.000000] No AGP bridge found
|
|
[ 0.000000] Node 0: aperture @ f8000000 size 64 MB
|
|
[ 0.000000] Node 1: aperture @ f8000000 size 64 MB
|
|
[ 0.000000] Memory: 32802496K/33419412K available (7403K kernel code, 1146K rwdata, 3420K rodata, 1336K init, 1444K bss, 616916K reserved)
|
|
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=16, Nodes=2
|
|
[ 0.000000] Hierarchical RCU implementation.
|
|
[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled.
|
|
[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=16.
|
|
[ 0.000000] Offload RCU callbacks from all CPUs
|
|
[ 0.000000] Offload RCU callbacks from CPUs: 0-15.
|
|
[ 0.000000] NR_IRQS:16640 nr_irqs:1352 16
|
|
[ 0.000000] Console: colour VGA+ 80x25
|
|
[ 0.000000] console [tty1] enabled
|
|
[ 0.000000] console [ttyS0] enabled
|
|
[ 0.000000] allocated 133693440 bytes of page_cgroup
|
|
[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
|
|
[ 0.000000] Enabling automatic NUMA balancing. Configure with numa_balancing= or the kernel.numa_balancing sysctl
|
|
[ 0.004000] tsc: Fast TSC calibration using PIT
|
|
[ 0.008000] tsc: Detected 1600.090 MHz processor
|
|
[ 0.000007] Calibrating delay loop (skipped), value calculated using timer frequency.. 3200.18 BogoMIPS (lpj=6400360)
|
|
[ 0.010843] pid_max: default: 32768 minimum: 301
|
|
[ 0.015615] Security Framework initialized
|
|
[ 0.019849] AppArmor: AppArmor initialized
|
|
[ 0.024050] Yama: becoming mindful.
|
|
[ 0.031798] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes)
|
|
[ 0.051967] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes)
|
|
[ 0.064918] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes)
|
|
[ 0.071978] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes)
|
|
[ 0.080065] Initializing cgroup subsys memory
|
|
[ 0.084538] Initializing cgroup subsys devices
|
|
[ 0.089087] Initializing cgroup subsys freezer
|
|
[ 0.093636] Initializing cgroup subsys blkio
|
|
[ 0.098014] Initializing cgroup subsys bfqio
|
|
[ 0.102390] Initializing cgroup subsys perf_event
|
|
[ 0.107203] Initializing cgroup subsys hugetlb
|
|
[ 0.111795] CPU: Physical Processor ID: 0
|
|
[ 0.115910] CPU: Processor Core ID: 0
|
|
[ 0.119680] mce: CPU supports 7 MCE banks
|
|
[ 0.123804] LVT offset 1 assigned for vector 0xf9
|
|
[ 0.128621] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512
|
|
[ 0.128621] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 512
|
|
[ 0.128621] tlb_flushall_shift: 5
|
|
[ 0.144171] Freeing SMP alternatives memory: 32K (ffffffff81e6e000 - ffffffff81e76000)
|
|
[ 0.153550] ACPI: Core revision 20131115
|
|
[ 0.159906] ACPI: All ACPI Tables successfully acquired
|
|
[ 0.165382] ftrace: allocating 28645 entries in 112 pages
|
|
[ 0.283530] Switched APIC routing to physical flat.
|
|
[ 0.289169] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
|
|
[ 0.334972] smpboot: CPU0: AMD Opteron(tm) Processor 6262 HE (fam: 15, model: 01, stepping: 02)
|
|
[ 0.451037] Performance Events: Fam15h core perfctr, AMD PMU driver.
|
|
[ 0.457713] ... version: 0
|
|
[ 0.461821] ... bit width: 48
|
|
[ 0.466016] ... generic registers: 6
|
|
[ 0.470124] ... value mask: 0000ffffffffffff
|
|
[ 0.475541] ... max period: 00007fffffffffff
|
|
[ 0.480958] ... fixed-purpose events: 0
|
|
[ 0.485065] ... event mask: 000000000000003f
|
|
[ 0.493643] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
|
|
[ 0.501910] x86: Booting SMP configuration:
|
|
[ 0.506198] .... node #0, CPUs: #1[ 0.524413] do_IRQ: 1.55 No irq handler for vector (irq -1)
|
|
#2[ 0.538480] do_IRQ: 2.55 No irq handler for vector (irq -1)
|
|
#3[ 0.552050] do_IRQ: 3.55 No irq handler for vector (irq -1)
|
|
#4[ 0.565622] do_IRQ: 4.55 No irq handler for vector (irq -1)
|
|
#5[ 0.579185] do_IRQ: 5.55 No irq handler for vector (irq -1)
|
|
#6[ 0.592751] do_IRQ: 6.55 No irq handler for vector (irq -1)
|
|
#7[ 0.606318] do_IRQ: 7.55 No irq handler for vector (irq -1)
|
|
#8[ 0.619882] do_IRQ: 8.55 No irq handler for vector (irq -1)
|
|
#9[ 0.633445] do_IRQ: 9.55 No irq handler for vector (irq -1)
|
|
#10[ 0.647018] do_IRQ: 10.55 No irq handler for vector (irq -1)
|
|
#11 #12 #13 #14 #15
|
|
[ 0.716955] x86: Booted up 1 node, 16 CPUs
|
|
[ 0.721438] smpboot: Total of 16 processors activated (51202.88 BogoMIPS)
|
|
[ 0.778686] devtmpfs: initialized
|
|
[ 0.790359] EVM: security.selinux
|
|
[ 0.793776] EVM: security.SMACK64
|
|
[ 0.797192] EVM: security.ima
|
|
[ 0.800258] EVM: security.capability
|
|
[ 0.805607] pinctrl core: initialized pinctrl subsystem
|
|
[ 0.811065] regulator-dummy: no parameters
|
|
[ 0.815298] RTC time: 0:22:42, date: 00/15/20
|
|
[ 0.819906] NET: Registered protocol family 16
|
|
[ 0.824654] cpuidle: using governor ladder
|
|
[ 0.828853] cpuidle: using governor menu
|
|
[ 0.833048] ACPI: bus type PCI registered
|
|
[ 0.837163] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
|
|
[ 0.843819] PCI: MMCONFIG for domain 0000 [bus 00-1f] at [mem 0xc0000000-0xc1ffffff] (base 0xc0000000)
|
|
[ 0.853276] PCI: MMCONFIG at [mem 0xc0000000-0xc1ffffff] reserved in E820
|
|
[ 0.862575] PCI: Using configuration type 1 for base access
|
|
[ 0.871046] bio: create slab <bio-0> at 0
|
|
[ 0.875646] ACPI: Added _OSI(Module Device)
|
|
[ 0.879936] ACPI: Added _OSI(Processor Device)
|
|
[ 0.884484] ACPI: Added _OSI(3.0 _SCP Extensions)
|
|
[ 0.889304] ACPI: Added _OSI(Processor Aggregator Device)
|
|
[ 0.902483] ACPI: Interpreter enabled
|
|
[ 0.906258] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580)
|
|
[ 0.915797] ACPI: (supports S0 S1 S3 S4 S5)
|
|
[ 0.920087] ACPI: Using IOAPIC for interrupt routing
|
|
[ 0.925258] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
|
|
[ 0.934695] ACPI: No dock devices found.
|
|
[ 0.946923] ACPI: PCI Interrupt Link [LNKA] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 0.955602] ACPI: PCI Interrupt Link [LNKB] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 0.964276] ACPI: PCI Interrupt Link [LNKC] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 0.972930] ACPI: PCI Interrupt Link [LNKD] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 0.981579] ACPI: PCI Interrupt Link [LNKE] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 0.990247] ACPI: PCI Interrupt Link [LNKF] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 0.998905] ACPI: PCI Interrupt Link [LNKG] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 1.007588] ACPI: PCI Interrupt Link [LNKH] (IRQs 4 7 10 11 12 14 15) *0, disabled.
|
|
[ 1.035895] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-08])
|
|
[ 1.042196] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
|
|
[ 1.050570] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
|
|
[ 1.097557] acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0x0cf7]; [io 0x03b0-0x03df] ignored
|
|
[ 1.107801] PCI host bridge to bus 0000:00
|
|
[ 1.112007] pci_bus 0000:00: root bus resource [bus 00-08]
|
|
[ 1.117604] pci_bus 0000:00: root bus resource [io 0x0d00-0x4fff]
|
|
[ 1.123895] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
|
|
[ 1.130882] pci_bus 0000:00: root bus resource [mem 0xfc000000-0xfcbfffff]
|
|
[ 1.137865] pci_bus 0000:00: root bus resource [mem 0xfcc00000-0xfccfffff]
|
|
[ 1.144852] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7]
|
|
[ 1.151578] pci 0000:00:02.0: System wakeup disabled by ACPI
|
|
[ 1.157504] pci 0000:00:04.0: System wakeup disabled by ACPI
|
|
[ 1.163435] pci 0000:00:09.0: System wakeup disabled by ACPI
|
|
[ 1.169368] pci 0000:00:0a.0: System wakeup disabled by ACPI
|
|
[ 1.175286] pci 0000:00:0b.0: System wakeup disabled by ACPI
|
|
[ 1.181205] pci 0000:00:0c.0: System wakeup disabled by ACPI
|
|
[ 1.187131] pci 0000:00:0d.0: System wakeup disabled by ACPI
|
|
[ 1.193131] pci 0000:00:11.0: System wakeup disabled by ACPI
|
|
[ 1.199081] pci 0000:00:12.0: System wakeup disabled by ACPI
|
|
[ 1.205028] pci 0000:00:12.1: System wakeup disabled by ACPI
|
|
[ 1.211039] pci 0000:00:12.2: System wakeup disabled by ACPI
|
|
[ 1.216991] pci 0000:00:13.0: System wakeup disabled by ACPI
|
|
[ 1.222937] pci 0000:00:13.1: System wakeup disabled by ACPI
|
|
[ 1.228940] pci 0000:00:13.2: System wakeup disabled by ACPI
|
|
[ 1.235101] pci 0000:00:14.1: System wakeup disabled by ACPI
|
|
[ 1.241380] pci 0000:00:14.4: System wakeup disabled by ACPI
|
|
[ 1.247322] pci 0000:00:14.5: System wakeup disabled by ACPI
|
|
[ 1.254513] pci 0000:00:02.0: PCI bridge to [bus 01]
|
|
[ 1.259642] pci 0000:00:04.0: PCI bridge to [bus 02]
|
|
[ 1.271025] pci 0000:00:09.0: PCI bridge to [bus 03]
|
|
[ 1.283020] pci 0000:00:0a.0: PCI bridge to [bus 04]
|
|
[ 1.288173] pci 0000:00:0b.0: PCI bridge to [bus 05]
|
|
[ 1.293307] pci 0000:00:0c.0: PCI bridge to [bus 06]
|
|
[ 1.298433] pci 0000:00:0d.0: PCI bridge to [bus 07]
|
|
[ 1.304027] pci 0000:00:14.4: PCI bridge to [bus 08] (subtractive decode)
|
|
[ 1.311521] ACPI: Enabled 4 GPEs in block 00 to 1F
|
|
[ 1.316887] vgaarb: device added: PCI:0000:08:01.0,decodes=io+mem,owns=io+mem,locks=none
|
|
[ 1.325147] vgaarb: loaded
|
|
[ 1.327962] vgaarb: bridge control possible 0000:08:01.0
|
|
[ 1.333727] SCSI subsystem initialized
|
|
[ 1.337781] ACPI: bus type USB registered
|
|
[ 1.341925] usbcore: registered new interface driver usbfs
|
|
[ 1.347536] usbcore: registered new interface driver hub
|
|
[ 1.353034] usbcore: registered new device driver usb
|
|
[ 1.358540] PCI: Using ACPI for IRQ routing
|
|
[ 1.364024] NetLabel: Initializing
|
|
[ 1.367525] NetLabel: domain hash size = 128
|
|
[ 1.371988] NetLabel: protocols = UNLABELED CIPSOv4
|
|
[ 1.377075] NetLabel: unlabeled traffic allowed by default
|
|
[ 1.382918] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
|
|
[ 1.388515] hpet0: 4 comparators, 32-bit 14.318180 MHz counter
|
|
[ 1.396628] Switched to clocksource hpet
|
|
[ 1.411179] AppArmor: AppArmor Filesystem Enabled
|
|
[ 1.416019] pnp: PnP ACPI init
|
|
[ 1.419198] ACPI: bus type PNP registered
|
|
[ 1.424184] pnp: PnP ACPI: found 7 devices
|
|
[ 1.428389] ACPI: bus type PNP unregistered
|
|
[ 1.442076] pci 0000:00:02.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.448725] pci 0000:00:02.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.455804] pci 0000:00:04.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.462450] pci 0000:00:04.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.469532] pci 0000:00:09.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.476612] pci 0000:00:0a.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.483696] pci 0000:00:0b.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.490341] pci 0000:00:0b.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.498799] pci 0000:00:0c.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.505446] pci 0000:00:0c.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.512528] pci 0000:00:0d.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.519176] pci 0000:00:0d.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.526256] pci 0000:00:02.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.532643] pci 0000:00:04.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.539030] pci 0000:00:0b.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.545418] pci 0000:00:0c.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.551805] pci 0000:00:0d.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.558197] pci 0000:00:0d.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.564841] pci 0000:00:0d.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.571920] pci 0000:00:0d.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.578309] pci 0000:00:0c.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.584957] pci 0000:00:0c.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.592036] pci 0000:00:0c.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.598423] pci 0000:00:0b.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.605070] pci 0000:00:0b.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.612152] pci 0000:00:0b.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.618539] pci 0000:00:0a.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.625619] pci 0000:00:09.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.632701] pci 0000:00:04.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.639349] pci 0000:00:04.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.646431] pci 0000:00:04.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.652817] pci 0000:00:02.0: BAR 14: can't assign mem (size 0x200000)
|
|
[ 1.659465] pci 0000:00:02.0: BAR 15: can't assign mem pref (size 0x200000)
|
|
[ 1.666545] pci 0000:00:02.0: BAR 13: can't assign io (size 0x1000)
|
|
[ 1.672933] pci 0000:00:02.0: PCI bridge to [bus 01]
|
|
[ 1.678016] pci 0000:00:04.0: PCI bridge to [bus 02]
|
|
[ 1.683101] pci 0000:00:09.0: PCI bridge to [bus 03]
|
|
[ 1.688175] pci 0000:00:09.0: bridge window [io 0x1000-0x1fff]
|
|
[ 1.694384] pci 0000:00:09.0: bridge window [mem 0xfc900000-0xfc9fffff]
|
|
[ 1.701292] pci 0000:00:0a.0: PCI bridge to [bus 04]
|
|
[ 1.706369] pci 0000:00:0a.0: bridge window [io 0x2000-0x2fff]
|
|
[ 1.712584] pci 0000:00:0a.0: bridge window [mem 0xfca00000-0xfcafffff]
|
|
[ 1.719492] pci 0000:00:0b.0: PCI bridge to [bus 05]
|
|
[ 1.724572] pci 0000:00:0c.0: PCI bridge to [bus 06]
|
|
[ 1.729652] pci 0000:00:0d.0: PCI bridge to [bus 07]
|
|
[ 1.734739] pci 0000:00:14.4: PCI bridge to [bus 08]
|
|
[ 1.739822] pci 0000:00:14.4: bridge window [io 0x3000-0x3fff]
|
|
[ 1.746039] pci 0000:00:14.4: bridge window [mem 0xfc000000-0xfc8fffff]
|
|
[ 1.753048] NET: Registered protocol family 2
|
|
[ 1.758125] TCP established hash table entries: 262144 (order: 9, 2097152 bytes)
|
|
[ 1.766705] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
|
|
[ 1.773909] TCP: Hash tables configured (established 262144 bind 65536)
|
|
[ 1.780708] TCP: reno registered
|
|
[ 1.784114] UDP hash table entries: 16384 (order: 7, 524288 bytes)
|
|
[ 1.790687] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes)
|
|
[ 1.797747] NET: Registered protocol family 1
|
|
[ 1.858637] Trying to unpack rootfs image as initramfs...
|
|
[ 5.068701] Freeing initrd memory: 10108K (ffff88007f620000 - ffff88007ffff000)
|
|
[ 5.076941] AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40
|
|
[ 5.082368] AMD-Vi: Interrupt remapping enabled
|
|
[ 5.099627] AMD-Vi: Lazy IO/TLB flushing enabled
|
|
[ 5.233638] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
|
|
[ 5.240199] software IO TLB [mem 0xbbffd000-0xbfffd000] (64MB) mapped at [ffff8800bbffd000-ffff8800bfffcfff]
|
|
[ 5.251142] perf: AMD NB counters detected
|
|
[ 5.255641] LVT offset 0 assigned for vector 0x400
|
|
[ 5.260672] perf: AMD IBS detected (0x000000ff)
|
|
[ 5.265423] microcode: CPU0: patch_level=0x00000000
|
|
[ 5.270423] microcode: CPU1: patch_level=0x00000000
|
|
[ 5.275434] microcode: CPU2: patch_level=0x00000000
|
|
[ 5.280435] microcode: CPU3: patch_level=0x00000000
|
|
[ 5.285442] microcode: CPU4: patch_level=0x00000000
|
|
[ 5.290435] microcode: CPU5: patch_level=0x00000000
|
|
[ 5.295441] microcode: CPU6: patch_level=0x00000000
|
|
[ 5.300436] microcode: CPU7: patch_level=0x00000000
|
|
[ 5.305441] microcode: CPU8: patch_level=0x00000000
|
|
[ 5.310443] microcode: CPU9: patch_level=0x00000000
|
|
[ 5.315452] microcode: CPU10: patch_level=0x00000000
|
|
[ 5.320536] microcode: CPU11: patch_level=0x00000000
|
|
[ 5.325632] microcode: CPU12: patch_level=0x00000000
|
|
[ 5.330719] microcode: CPU13: patch_level=0x00000000
|
|
[ 5.335794] microcode: CPU14: patch_level=0x00000000
|
|
[ 5.340880] microcode: CPU15: patch_level=0x00000000
|
|
[ 5.346078] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
|
|
[ 5.355025] Scanning for low memory corruption every 60 seconds
|
|
[ 5.361785] Initialise system trusted keyring
|
|
[ 5.366358] audit: initializing netlink socket (disabled)
|
|
[ 5.412475] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
|
[ 5.422461] zbud: loaded
|
|
[ 5.425370] VFS: Disk quotas dquot_6.5.2
|
|
[ 5.429478] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
|
|
[ 5.436871] fuse init (API version 7.22)
|
|
[ 5.441035] msgmni has been set to 32768
|
|
[ 5.445158] Key type big_key registered
|
|
[ 5.450033] Key type asymmetric registered
|
|
[ 5.454243] Asymmetric key parser 'x509' registered
|
|
[ 5.459283] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
|
|
[ 5.467011] io scheduler noop registered
|
|
[ 5.471046] io scheduler deadline registered (default)
|
|
[ 5.476339] io scheduler cfq registered
|
|
[ 5.480292] io scheduler bfq registered
|
|
[ 5.484237] BFQ I/O-scheduler version: v7r5
|
|
[ 5.488456] pcieport 0000:00:02.0: device [1002:5a16] has invalid IRQ; check vendor BIOS
|
|
[ 5.497229] pcieport 0000:00:04.0: device [1002:5a18] has invalid IRQ; check vendor BIOS
|
|
[ 5.505553] pcieport 0000:00:04.0: can't derive routing for PCI INT A
|
|
[ 5.512112] pcieport 0000:00:04.0: PCI INT A: no GSI
|
|
[ 5.517284] pcieport 0000:00:09.0: device [1002:5a1c] has invalid IRQ; check vendor BIOS
|
|
[ 5.525710] pcieport 0000:00:0a.0: device [1002:5a1d] has invalid IRQ; check vendor BIOS
|
|
[ 5.534141] pcieport 0000:00:0b.0: device [1002:5a1f] has invalid IRQ; check vendor BIOS
|
|
[ 5.542563] pcieport 0000:00:0c.0: device [1002:5a20] has invalid IRQ; check vendor BIOS
|
|
[ 5.550980] pcieport 0000:00:0d.0: device [1002:5a1e] has invalid IRQ; check vendor BIOS
|
|
[ 5.559434] pcieport 0000:00:02.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.566534] pcieport 0000:00:04.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.573631] pcieport 0000:00:09.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.580710] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.587376] pcieport 0000:00:0a.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.594453] pci 0000:04:00.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.601121] pcieport 0000:00:0b.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.608221] pcieport 0000:00:0c.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.615322] pcieport 0000:00:0d.0: Signaling PME through PCIe PME interrupt
|
|
[ 5.622429] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
|
|
[ 6.248713] tsc: Refined TSC clocksource calibration: 1600.019 MHz
|
|
[ 7.224714] pciehp 0000:00:02.0:pcie04: HPC vendor_id 1002 device_id 5a16 ss_vid 1002 ss_did 5a10
|
|
[ 7.253083] Switched to clocksource tsc
|
|
[ 10.832751] pciehp 0000:00:04.0:pcie04: HPC vendor_id 1002 device_id 5a18 ss_vid 1002 ss_did 5a10
|
|
[ 14.440793] pciehp 0000:00:09.0:pcie04: HPC vendor_id 1002 device_id 5a1c ss_vid 1002 ss_did 5a10
|
|
[ 17.048837] pciehp 0000:00:0a.0:pcie04: HPC vendor_id 1002 device_id 5a1d ss_vid 1002 ss_did 5a10
|
|
[ 19.656855] pciehp 0000:00:0b.0:pcie04: HPC vendor_id 1002 device_id 5a1f ss_vid 1002 ss_did 5a10
|
|
[ 23.264912] pciehp 0000:00:0c.0:pcie04: HPC vendor_id 1002 device_id 5a20 ss_vid 1002 ss_did 5a10
|
|
[ 26.872941] pciehp 0000:00:0d.0:pcie04: HPC vendor_id 1002 device_id 5a1e ss_vid 1002 ss_did 5a10
|
|
[ 28.881020] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
|
|
[ 28.887855] ipmi message handler version 39.2
|
|
[ 28.892440] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0
|
|
[ 28.900779] ACPI: Power Button [PWRB]
|
|
[ 28.904593] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
|
|
[ 28.912137] ACPI: Power Button [PWRF]
|
|
[ 28.917193] GHES: HEST is not enabled!
|
|
[ 28.921255] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
|
|
[ 28.948251] 00:05: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
|
|
[ 28.976299] serial8250: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
|
|
[ 28.986903] Linux agpgart interface v0.103
|
|
[ 28.993822] brd: module loaded
|
|
[ 28.998379] loop: module loaded
|
|
[ 29.002325] libphy: Fixed MDIO Bus: probed
|
|
[ 29.006676] tun: Universal TUN/TAP device driver, 1.6
|
|
[ 29.011837] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
|
[ 29.018229] PPP generic driver version 2.4.2
|
|
[ 29.022702] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
|
|
[ 29.029349] ehci-pci: EHCI PCI platform driver
|
|
[ 29.034046] ehci-pci 0000:00:12.2: EHCI Host Controller
|
|
[ 29.039389] ehci-pci 0000:00:12.2: new USB bus registered, assigned bus number 1
|
|
[ 29.046941] ehci-pci 0000:00:12.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround
|
|
[ 29.055809] ehci-pci 0000:00:12.2: debug port 1
|
|
[ 29.060532] ehci-pci 0000:00:12.2: irq 17, io mem 0xfcb0e000
|
|
[ 29.076971] ehci-pci 0000:00:12.2: USB 2.0 started, EHCI 1.00
|
|
[ 29.082925] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
|
|
[ 29.089833] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.097206] usb usb1: Product: EHCI Host Controller
|
|
[ 29.102189] usb usb1: Manufacturer: Linux 3.13.0-37-generic ehci_hcd
|
|
[ 29.108655] usb usb1: SerialNumber: 0000:00:12.2
|
|
[ 29.113571] hub 1-0:1.0: USB hub found
|
|
[ 29.117434] hub 1-0:1.0: 6 ports detected
|
|
[ 29.121893] ehci-pci 0000:00:13.2: EHCI Host Controller
|
|
[ 29.128612] ehci-pci 0000:00:13.2: new USB bus registered, assigned bus number 2
|
|
[ 29.136158] ehci-pci 0000:00:13.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround
|
|
[ 29.145022] ehci-pci 0000:00:13.2: debug port 1
|
|
[ 29.149710] ehci-pci 0000:00:13.2: irq 19, io mem 0xfcb0f000
|
|
[ 29.164974] ehci-pci 0000:00:13.2: USB 2.0 started, EHCI 1.00
|
|
[ 29.170917] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
|
|
[ 29.177819] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.185192] usb usb2: Product: EHCI Host Controller
|
|
[ 29.190174] usb usb2: Manufacturer: Linux 3.13.0-37-generic ehci_hcd
|
|
[ 29.196640] usb usb2: SerialNumber: 0000:00:13.2
|
|
[ 29.201536] hub 2-0:1.0: USB hub found
|
|
[ 29.205401] hub 2-0:1.0: 6 ports detected
|
|
[ 29.209715] ehci-platform: EHCI generic platform driver
|
|
[ 29.215058] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
|
|
[ 29.221351] ohci-pci: OHCI PCI platform driver
|
|
[ 29.226146] ohci-pci 0000:00:12.0: OHCI PCI host controller
|
|
[ 29.231874] ohci-pci 0000:00:12.0: new USB bus registered, assigned bus number 3
|
|
[ 29.239454] ohci-pci 0000:00:12.0: irq 16, io mem 0xfcb08000
|
|
[ 29.305004] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
|
|
[ 29.311908] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.319285] usb usb3: Product: OHCI PCI host controller
|
|
[ 29.324621] usb usb3: Manufacturer: Linux 3.13.0-37-generic ohci_hcd
|
|
[ 29.331089] usb usb3: SerialNumber: 0000:00:12.0
|
|
[ 29.336011] hub 3-0:1.0: USB hub found
|
|
[ 29.339876] hub 3-0:1.0: 3 ports detected
|
|
[ 29.344248] ohci-pci 0000:00:12.1: OHCI PCI host controller
|
|
[ 29.349934] ohci-pci 0000:00:12.1: new USB bus registered, assigned bus number 4
|
|
[ 29.357493] ohci-pci 0000:00:12.1: irq 16, io mem 0xfcb09000
|
|
[ 29.421105] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
|
|
[ 29.428008] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.435385] usb usb4: Product: OHCI PCI host controller
|
|
[ 29.440720] usb usb4: Manufacturer: Linux 3.13.0-37-generic ohci_hcd
|
|
[ 29.447189] usb usb4: SerialNumber: 0000:00:12.1
|
|
[ 29.452260] hub 4-0:1.0: USB hub found
|
|
[ 29.456123] hub 4-0:1.0: 3 ports detected
|
|
[ 29.460496] ohci-pci 0000:00:13.0: OHCI PCI host controller
|
|
[ 29.466182] ohci-pci 0000:00:13.0: new USB bus registered, assigned bus number 5
|
|
[ 29.473757] ohci-pci 0000:00:13.0: irq 18, io mem 0xfcb0a000
|
|
[ 29.537106] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
|
|
[ 29.544015] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.551391] usb usb5: Product: OHCI PCI host controller
|
|
[ 29.556727] usb usb5: Manufacturer: Linux 3.13.0-37-generic ohci_hcd
|
|
[ 29.563213] usb usb5: SerialNumber: 0000:00:13.0
|
|
[ 29.568306] hub 5-0:1.0: USB hub found
|
|
[ 29.572178] hub 5-0:1.0: 3 ports detected
|
|
[ 29.576680] ohci-pci 0000:00:13.1: OHCI PCI host controller
|
|
[ 29.582371] ohci-pci 0000:00:13.1: new USB bus registered, assigned bus number 6
|
|
[ 29.589932] ohci-pci 0000:00:13.1: irq 18, io mem 0xfcb0b000
|
|
[ 29.653028] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
|
|
[ 29.659932] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.667297] usb usb6: Product: OHCI PCI host controller
|
|
[ 29.672627] usb usb6: Manufacturer: Linux 3.13.0-37-generic ohci_hcd
|
|
[ 29.679093] usb usb6: SerialNumber: 0000:00:13.1
|
|
[ 29.684191] hub 6-0:1.0: USB hub found
|
|
[ 29.688058] hub 6-0:1.0: 3 ports detected
|
|
[ 29.692518] ohci-pci 0000:00:14.5: OHCI PCI host controller
|
|
[ 29.698211] ohci-pci 0000:00:14.5: new USB bus registered, assigned bus number 7
|
|
[ 29.705778] ohci-pci 0000:00:14.5: irq 18, io mem 0xfcb0c000
|
|
[ 29.769006] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
|
|
[ 29.775910] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
|
|
[ 29.783286] usb usb7: Product: OHCI PCI host controller
|
|
[ 29.788624] usb usb7: Manufacturer: Linux 3.13.0-37-generic ohci_hcd
|
|
[ 29.795089] usb usb7: SerialNumber: 0000:00:14.5
|
|
[ 29.800167] hub 7-0:1.0: USB hub found
|
|
[ 29.804034] hub 7-0:1.0: 2 ports detected
|
|
[ 29.808272] ohci-platform: OHCI generic platform driver
|
|
[ 29.813622] uhci_hcd: USB Universal Host Controller Interface driver
|
|
[ 29.820176] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
|
|
[ 29.825225] usb 2-4: new high-speed USB device number 2 using ehci-pci
|
|
[ 29.833720] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
|
|
[ 29.844807] serio: i8042 KBD port at 0x60,0x64 irq 1
|
|
[ 29.850190] mousedev: PS/2 mouse device common for all mice
|
|
[ 29.856209] rtc_cmos 00:00: RTC can wake from S4
|
|
[ 29.861205] rtc_cmos 00:00: rtc core: registered rtc_cmos as rtc0
|
|
[ 29.867469] rtc_cmos 00:00: alarms up to one day, 114 bytes nvram, hpet irqs
|
|
[ 29.874742] device-mapper: uevent: version 1.0.3
|
|
[ 29.880026] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com
|
|
[ 29.888635] ledtrig-cpu: registered to indicate activity on CPUs
|
|
[ 29.894941] TCP: cubic registered
|
|
[ 29.898507] NET: Registered protocol family 10
|
|
[ 29.903374] NET: Registered protocol family 17
|
|
[ 29.907952] Key type dns_resolver registered
|
|
[ 29.914470] Loading compiled-in X.509 certificates
|
|
[ 29.920490] Loaded X.509 cert 'Magrathea: Glacier signing key: b711d274b1ae56685d7feaff672ef9e8633d25e2'
|
|
[ 29.930166] registered taskstats version 1
|
|
[ 29.938979] Key type trusted registered
|
|
[ 29.945653] Key type encrypted registered
|
|
[ 29.952808] AppArmor: AppArmor sha1 policy hashing enabled
|
|
[ 29.957900] usb 2-4: New USB device found, idVendor=0781, idProduct=5406
|
|
[ 29.957902] usb 2-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
|
|
[ 29.957903] usb 2-4: Product: U3 Cruzer Micro
|
|
[ 29.957905] usb 2-4: Manufacturer: SanDisk
|
|
[ 29.957906] usb 2-4: SerialNumber: 0774201663C1BA4B
|
|
[ 29.986105] IMA: No TPM chip found, activating TPM-bypass!
|
|
[ 29.992182] regulator-dummy: disabling
|
|
[ 29.996475] Magic number: 0:907:354
|
|
[ 30.000297] machinecheck machinecheck10: hash matches
|
|
[ 30.005460] input event0: hash matches
|
|
[ 30.009446] rtc_cmos 00:00: hctosys: invalid date/time
|
|
[ 30.015332] acpi-cpufreq: overriding BIOS provided _PSD data
|
|
[ 30.023214] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
|
|
[ 30.029337] EDD information not available.
|
|
[ 30.035910] Freeing unused kernel memory: 1336K (ffffffff81d20000 - ffffffff81e6e000)
|
|
[ 30.043909] Write protecting the kernel read-only data: 12288k
|
|
[ 30.054189] Freeing unused kernel memory: 776K (ffff88000173e000 - ffff880001800000)
|
|
[ 30.065885] Freeing unused kernel memory: 676K (ffff880001b57000 - ffff880001c00000)
|
|
[ 30.084196] systemd-udevd[197]: starting version 204
|
|
[ 30.093016] usb 3-2: new full-speed USB device number 2 using ohci-pci
|
|
[ 30.116120] pps_core: module verification failed: signature and/or required key missing - tainting kernel
|
|
[ 30.126434] pps_core: LinuxPPS API ver. 1 registered
|
|
[ 30.126439] usb-storage 2-4:1.0: USB Mass Storage device detected
|
|
[ 30.126617] scsi0 : usb-storage 2-4:1.0
|
|
[ 30.126738] usbcore: registered new interface driver usb-storage
|
|
[ 30.147771] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
|
[ 30.157811] PTP clock support registered
|
|
[ 30.164770] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
|
[ 30.170749] e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
|
|
[ 30.177201] e1000e 0000:03:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
|
|
[ 30.282143] usb 3-2: New USB device found, idVendor=0853, idProduct=010e
|
|
[ 30.289005] usb 3-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
|
|
[ 30.296263] usb 3-2: Product: Realforce 86
|
|
[ 30.300464] usb 3-2: Manufacturer: Topre Corporation
|
|
[ 30.306001] e1000e 0000:03:00.0 eth0: registered PHC clock
|
|
[ 30.311605] e1000e 0000:03:00.0 eth0: (PCI Express:2.5GT/s:Width x1) f0:79:59:38:b2:40
|
|
[ 30.319751] e1000e 0000:03:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
|
[ 30.326911] e1000e 0000:03:00.0 eth0: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF
|
|
[ 30.333992] hidraw: raw HID events driver (C) Jiri Kosina
|
|
[ 30.334071] e1000e 0000:04:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
|
|
[ 30.356316] usbcore: registered new interface driver usbhid
|
|
[ 30.362016] usbhid: USB HID core driver
|
|
[ 30.367304] input: Topre Corporation Realforce 86 as /devices/pci0000:00/0000:00:12.0/usb3/3-2/3-2:1.0/input/input3
|
|
[ 30.378159] hid-generic 0003:0853:010E.0001: input,hidraw0: USB HID v1.11 Keyboard [Topre Corporation Realforce 86] on usb-0000:00:12.0-2/input0
|
|
[ 30.453807] e1000e 0000:04:00.0 eth1: registered PHC clock
|
|
[ 30.459405] e1000e 0000:04:00.0 eth1: (PCI Express:2.5GT/s:Width x1) f0:79:59:38:b2:3f
|
|
[ 30.467473] e1000e 0000:04:00.0 eth1: Intel(R) PRO/1000 Network Connection
|
|
[ 30.474537] e1000e 0000:04:00.0 eth1: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF
|
|
[ 30.505530] systemd-udevd[201]: renamed network interface eth1 to p10p1
|
|
[ 30.521494] systemd-udevd[199]: renamed network interface eth0 to p9p1
|