coreboot

[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x8b05 in mcache @0xfef09e4c

[DEBUG] BS: bootblock times (exec / console): total (unknown) / 21 ms





[NOTE ] coreboot-4.17-528-g046541b246-dirty Fri Jul 8 14:25:24 UTC 2022 romstage starting (log level: 7)...

[INFO ] CPU: Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz

[INFO ] CPU: ID 706a1, Geminilake B0, ucode: 00000039

[INFO ] CPU: AES Supported, TXT Not Supported, VT Supported

[INFO ] MCH: device id 31f0 (rev 03) is Geminilake

[INFO ] PCH: device id 31e8 (rev 03) is Geminilake

[INFO ] IGD: device id 3184 (rev 03) is Geminilake

[DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000

[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000

[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000

[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000

[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000

[DEBUG] prsts: 00000000

[DEBUG] tco_sts: 0000 0000

[DEBUG] gen_pmcon1: 08004004 gen_pmcon2: 00003a00 gen_pmcon3: 00000000

[DEBUG] prev_sleep_state 5

[INFO ] CBFS: Found 'fspm.bin' @0x50a80 size 0x2cb68 in mcache @0xfef0a020

[DEBUG] FMAP: area RW_MRC_CACHE found @ 5d0000 (65536 bytes)

[NOTE ] MRC: no data in 'RW_MRC_CACHE'

[DEBUG] FMAP: area RW_VAR_MRC_CACHE found @ 5e0000 (65536 bytes)

[NOTE ] MRC: no data in 'RW_VAR_MRC_CACHE'

[DEBUG] CBMEM:

[DEBUG] IMD: root @ 0x79fff000 254 entries.

[DEBUG] IMD: root @ 0x79ffec00 62 entries.

[DEBUG] External stage cache:

[DEBUG] IMD: root @ 0x7afff000 254 entries.

[DEBUG] IMD: root @ 0x7affec00 62 entries.

[DEBUG] FMAP: area RW_MRC_CACHE found @ 5d0000 (65536 bytes)

[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.

[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000

[NOTE ] MRC: no data in 'RW_MRC_CACHE'

[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.

[DEBUG] MRC: updated 'RW_MRC_CACHE'.

[DEBUG] CPU: frequency set to 2700 MHz

[DEBUG] FMAP: area RW_VAR_MRC_CACHE found @ 5e0000 (65536 bytes)

[DEBUG] MRC: Checking cached data update for 'RW_VAR_MRC_CACHE'.

[NOTE ] MRC: no data in 'RW_VAR_MRC_CACHE'

[DEBUG] MRC: cache data 'RW_VAR_MRC_CACHE' needs update.

[DEBUG] MRC: updated 'RW_VAR_MRC_CACHE'.

[DEBUG] 4 DIMMs found

[DEBUG] SMM Memory Map

[DEBUG] SMRAM : 0x7a000000 0x1000000

[DEBUG] Subregion 0: 0x7a000000 0xf00000

[DEBUG] Subregion 1: 0x7af00000 0x100000

[DEBUG] Subregion 2: 0x7b000000 0x0

[DEBUG] top_of_ram = 0x7a000000

[DEBUG] Normal boot

[INFO ] CBFS: Found 'fallback/postcar' @0xad400 size 0x587c in mcache @0xfef0a0f8

[DEBUG] Loading module at 0x79bcf000 with entry 0x79bcf031. filesize: 0x5460 memsize: 0xb7d0

[DEBUG] Processing 247 relocs. Offset value of 0x77bcf000

[DEBUG] BS: romstage times (exec / console): total (unknown) / 289 ms





[NOTE ] coreboot-4.17-528-g046541b246-dirty Fri Jul 8 14:25:24 UTC 2022 postcar starting (log level: 7)...

[DEBUG] Normal boot

[INFO ] CBFS: Found 'fallback/ramstage' @0x2dc80 size 0x1a60f in mcache @0x79bdd0dc

[DEBUG] Loading module at 0x79b7a000 with entry 0x79b7a000. filesize: 0x38658 memsize: 0x53550

[DEBUG] Processing 3856 relocs. Offset value of 0x75b7a000

[DEBUG] BS: postcar times (exec / console): total (unknown) / 41 ms





[NOTE ] coreboot-4.17-528-g046541b246-dirty Fri Jul 8 14:25:24 UTC 2022 ramstage starting (log level: 7)...

[DEBUG] Normal boot

[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x8c40 size 0x25000 in mcache @0x79bdd0ac

[DEBUG] microcode: sig=0x706a1 pf=0x1 revision=0x39

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[INFO ] CBFS: Found 'fsps.bin' @0x7d640 size 0x2f000 in mcache @0x79bdd234

[DEBUG] Detected 4 core, 4 thread CPU.

[INFO ] Will perform SMM setup.

[INFO ] CPU: Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz.

[INFO ] LAPIC 0x0 in XAPIC mode.

[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178

[DEBUG] Processing 18 relocs. Offset value of 0x00030000

[DEBUG] Attempting to start 3 APs

[DEBUG] Waiting for 10ms after sending INIT.

[DEBUG] Waiting for SIPI to complete...

[DEBUG] done.

[INFO ] LAPIC 0x4 in XAPIC mode.

[INFO ] LAPIC 0x2 in XAPIC mode.

[INFO ] LAPIC 0x6 in XAPIC mode.

[DEBUG] Waiting for SIPI to complete...

[DEBUG] done.

[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x00000039

[INFO ] AP: slot 1 apic_id 6, MCU rev: 0x00000039

[INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000039

[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0

[DEBUG] Processing 11 relocs. Offset value of 0x00038000

[DEBUG] smm_module_setup_stub: stack_top = 0x7a002000

[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800

[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c

[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000

[DEBUG] SMM Module: stub loaded at 38000. Will call 0x79b922aa

[DEBUG] Installing permanent SMM handler to 0x7a000000

[DEBUG] FX_SAVE [0x7aeff800-0x7af00000]

[DEBUG] HANDLER [0x7aefc000-0x7aeff790]



[DEBUG] CPU 0

[DEBUG] ss0 [0x7aefbc00-0x7aefc000]

[DEBUG] stub0 [0x7aef4000-0x7aef41e0]



[DEBUG] CPU 1

[DEBUG] ss1 [0x7aefb800-0x7aefbc00]

[DEBUG] stub1 [0x7aef3c00-0x7aef3de0]



[DEBUG] CPU 2

[DEBUG] ss2 [0x7aefb400-0x7aefb800]

[DEBUG] stub2 [0x7aef3800-0x7aef39e0]



[DEBUG] CPU 3

[DEBUG] ss3 [0x7aefb000-0x7aefb400]

[DEBUG] stub3 [0x7aef3400-0x7aef35e0]



[DEBUG] stacks [0x7a000000-0x7a002000]

[DEBUG] Loading module at 0x7aefc000 with entry 0x7aefcdf9. filesize: 0x3690 memsize: 0x3790

[DEBUG] Processing 218 relocs. Offset value of 0x7aefc000

[DEBUG] Loading module at 0x7aef4000 with entry 0x7aef4000. filesize: 0x1e0 memsize: 0x1e0

[DEBUG] Processing 11 relocs. Offset value of 0x7aef4000

[DEBUG] smm_module_setup_stub: stack_top = 0x7a002000

[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800

[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c

[DEBUG] smm_module_setup_stub: runtime.smm_size = 0xf00000

[DEBUG] SMM Module: placing smm entry code at 7aef3c00, cpu # 0x1

[DEBUG] SMM Module: placing smm entry code at 7aef3800, cpu # 0x2

[DEBUG] SMM Module: placing smm entry code at 7aef3400, cpu # 0x3

[DEBUG] SMM Module: stub loaded at 7aef4000. Will call 0x7aefcdf9

[DEBUG] Clearing SMI status registers

[DEBUG] SMI_STS: PERIODIC TCO 

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeebc00, cpu = 1

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeeb800, cpu = 2

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeec000, cpu = 0

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeeb400, cpu = 3

[DEBUG] Relocation complete.

[INFO ] Initializing CPU #0

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[DEBUG] Clearing out pending MCEs

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[INFO ] CPU #0 initialized

[INFO ] Initializing CPU #1

[INFO ] Initializing CPU #3

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[INFO ] Initializing CPU #2

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[DEBUG] Clearing out pending MCEs

[DEBUG] Clearing out pending MCEs

[INFO ] microcode: load microcode patch

[DEBUG] CPU: vendor Intel device 706a1

[ERROR] microcode: Update failed

[INFO ] microcode: load microcode patch

[DEBUG] CPU: family 06, model 7a, stepping 01

[ERROR] microcode: Update failed

[INFO ] CPU #1 initialized

[DEBUG] Clearing out pending MCEs

[INFO ] CPU #3 initialized

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[INFO ] CPU #2 initialized

[INFO ] bsp_do_flight_plan done after 424 msecs.

[DEBUG] Enabling SMIs.

[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 192 / 370 ms

[INFO ] CBFS: Found 'vbt.bin' @0xac680 size 0x559 in mcache @0x79bdd258

[INFO ] Found a VBT of 5632 bytes after decompression

[WARN ] PCI:00.1: Could not disable the device

[WARN ] PCI:03.0: Could not disable the device

[WARN ] PCI:0d.0: Could not disable the device

[WARN ] PCI:0d.1: Could not disable the device

[WARN ] PCI:0d.3: Could not disable the device

[WARN ] PCI:1a.0: Could not disable the device

[DEBUG] WEAK: src/soc/intel/apollolake/chip.c/mainboard_silicon_init_params called

[INFO ] FSPS returned 0

[INFO ] ITSS IRQ Polarities Before:

[INFO ] IPC0: 0xffffeef8

[INFO ] IPC1: 0xffffffff

[INFO ] IPC2: 0xffffffff

[INFO ] IPC3: 0x00ffffff

[INFO ] ITSS IRQ Polarities After:

[INFO ] IPC0: 0xffffeef8

[INFO ] IPC1: 0x0003ffff

[INFO ] IPC2: 0x00000000

[INFO ] IPC3: 0x00000000

[INFO ] CPU TDP = 6 Watts

[INFO ] CPU PL1 = 10 Watts

[INFO ] CPU PL2 = 15 Watts

[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 167 / 107 ms

[INFO ] Enumerating buses...

[DEBUG] Root Device scanning...

[DEBUG] DOMAIN: 0000 enabled

[DEBUG] CPU_CLUSTER: 0 enabled

[DEBUG] MMIO: fed40000 enabled

[DEBUG] DOMAIN: 0000 scanning...

[DEBUG] PCI: pci_scan_bus for bus 00

[DEBUG] PCI: 00:00.0 [8086/31f0] enabled

[DEBUG] PCI: 00:00.1 [8086/318c] disabled

[DEBUG] PCI: 00:02.0 [8086/3184] enabled

[DEBUG] PCI: 00:0c.0 [8086/31dc] enabled

[DEBUG] PCI: 00:0d.0 [8086/3192] disabled

[DEBUG] PCI: 00:0d.1 [8086/3194] disabled

[DEBUG] PCI: 00:0d.2 [8086/3196] enabled

[DEBUG] PCI: 00:0d.3 [8086/31ec] disabled

[DEBUG] PCI: 00:0e.0 [8086/3198] enabled

[DEBUG] No CMOS option 'me_state'.

[DEBUG] PCI: 00:0f.0 [8086/319a] enabled

[DEBUG] PCI: 00:0f.1 [8086/319c] enabled

[DEBUG] PCI: 00:0f.2 [8086/319e] enabled

[DEBUG] PCI: 00:12.0 [8086/31e3] enabled

[DEBUG] PCI: 00:15.0 [8086/31a8] enabled

[DEBUG] PCI: 00:17.0 [8086/31b4] enabled

[DEBUG] PCI: 00:17.3 [8086/31ba] enabled

[DEBUG] PCI: 00:18.0 [8086/31bc] enabled

[DEBUG] PCI: 00:18.2 [8086/31c0] enabled

[DEBUG] PCI: 00:19.2 [8086/31c6] enabled

[DEBUG] PCI: 00:1f.0 [8086/31e8] enabled

[DEBUG] PCI: 00:1f.1 [8086/31d4] disabled

[WARN ] PCI: Leftover static devices:

[WARN ] PCI: 00:00.2

[WARN ] PCI: 00:03.0

[WARN ] PCI: 00:11.0

[WARN ] PCI: 00:13.0

[WARN ] PCI: 00:13.1

[WARN ] PCI: 00:13.2

[WARN ] PCI: 00:13.3

[WARN ] PCI: 00:14.0

[WARN ] PCI: 00:14.1

[WARN ] PCI: 00:15.1

[WARN ] PCI: 00:16.0

[WARN ] PCI: 00:16.1

[WARN ] PCI: 00:16.2

[WARN ] PCI: 00:16.3

[WARN ] PCI: 00:17.1

[WARN ] PCI: 00:17.2

[WARN ] PCI: 00:18.1

[WARN ] PCI: 00:18.3

[WARN ] PCI: 00:19.0

[WARN ] PCI: 00:19.1

[WARN ] PCI: 00:1a.0

[WARN ] PCI: 00:1b.0

[WARN ] PCI: 00:1c.0

[WARN ] PCI: 00:1d.0

[WARN ] PCI: 00:1e.0

[WARN ] PCI: Check your devicetree.cb.

[DEBUG] PCI: 00:02.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:02.0 finished in 0 msecs

[DEBUG] PCI: 00:0c.0 scanning...

[DEBUG] GENERIC: 0.0 enabled

[DEBUG] scan_bus: bus PCI: 00:0c.0 finished in 3 msecs

[DEBUG] PCI: 00:0e.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:0e.0 finished in 0 msecs

[DEBUG] PCI: 00:15.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:15.0 finished in 0 msecs

[DEBUG] PCI: 00:17.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:17.0 finished in 0 msecs

[DEBUG] PCI: 00:17.3 scanning...

[DEBUG] scan_bus: bus PCI: 00:17.3 finished in 0 msecs

[DEBUG] PCI: 00:19.2 scanning...

[DEBUG] scan_bus: bus PCI: 00:19.2 finished in 0 msecs

[DEBUG] PCI: 00:1f.0 scanning...

[DEBUG] PNP: 004e.0 enabled

[DEBUG] PNP: 004e.1 disabled

[DEBUG] PNP: 004e.2 disabled

[DEBUG] PNP: 004e.4 disabled

[DEBUG] PNP: 004e.5 disabled

[DEBUG] PNP: 004e.6 enabled

[DEBUG] PNP: 004e.a disabled

[DEBUG] PNP: 004e.f disabled

[DEBUG] PNP: 004e.10 disabled

[DEBUG] PNP: 004e.11 disabled

[DEBUG] PNP: 004e.12 disabled

[DEBUG] PNP: 004e.13 disabled

[DEBUG] PNP: 004e.14 disabled

[DEBUG] PNP: 004e.17 disabled

[DEBUG] PNP: 004e.18 disabled

[DEBUG] PNP: 004e.19 disabled

[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 61 msecs

[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 352 msecs

[DEBUG] scan_bus: bus Root Device finished in 374 msecs

[INFO ] done

[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 390 ms

[DEBUG] FMAP: area UNIFIED_MRC_CACHE found @ 5c0000 (196608 bytes)

[INFO ] MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.

[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms

[DEBUG] found VGA at PCI: 00:02.0

[DEBUG] Setting up VGA for PCI: 00:02.0

[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000

[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device

[INFO ] Allocating resources...

[INFO ] Reading resources...

[DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000

[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x8000

[INFO ] Available memory above 4GB: 6144M

[ERROR] PNP: 004e.0 missing read_resources

[INFO ] Done reading resources.

[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===

[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===

[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff

[DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)

[DEBUG] update_constraints: PCI: 00:1f.0 84 base 000006a0 limit 000006af io (fixed)

[DEBUG] update_constraints: PCI: 00:1f.0 88 base 00000080 limit 0000008f io (fixed)

[DEBUG] update_constraints: PNP: 004e.6 60 base 00000060 limit 00000060 io (fixed)

[DEBUG] update_constraints: PNP: 004e.6 62 base 00000064 limit 00000064 io (fixed)

[INFO ] DOMAIN: 0000: Resource ranges:

[INFO ] * Base: 1000, Size: f000, Tag: 100

[DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io

[DEBUG] PCI: 00:12.0 20 * [0x1040 - 0x105f] limit: 105f io

[DEBUG] PCI: 00:12.0 18 * [0x1060 - 0x1067] limit: 1067 io

[DEBUG] PCI: 00:12.0 1c * [0x1068 - 0x106b] limit: 106b io

[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done

[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff

[DEBUG] update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 02 base fed64000 limit fed64fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 03 base fed65000 limit fed65fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 04 base 00000000 limit 0009ffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 05 base 000c0000 limit 79ffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 06 base 7a000000 limit 7fffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 07 base 100000000 limit 27fffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 08 base 000a0000 limit 000bffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 09 base 000c0000 limit 000fffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0a base 11800000 limit 11bfffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0b base 11000000 limit 117fffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0c base 12000000 limit 120fffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0d base 12150000 limit 12150fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0e base 12140000 limit 1214ffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0f base 10000000 limit 10ffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 10 base 11c00000 limit 11ffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 11 base 12100000 limit 1213ffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:18.2 10 base ddffc000 limit ddffcfff mem (fixed)

[INFO ] DOMAIN: 0000: Resource ranges:

[INFO ] * Base: 80000000, Size: 5dffc000, Tag: 200

[INFO ] * Base: ddffd000, Size: 2003000, Tag: 200

[INFO ] * Base: f0000000, Size: ed10000, Tag: 200

[INFO ] * Base: fed18000, Size: 4c000, Tag: 200

[INFO ] * Base: fed66000, Size: 129a000, Tag: 200

[INFO ] * Base: 280000000, Size: 7d80000000, Tag: 100200

[DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem

[DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem

[DEBUG] PCI: 00:0e.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem

[DEBUG] PCI: 00:15.0 10 * [0x91100000 - 0x9110ffff] limit: 9110ffff mem

[DEBUG] PCI: 00:0c.0 10 * [0x91110000 - 0x91113fff] limit: 91113fff mem

[DEBUG] PCI: 00:0e.0 10 * [0x91114000 - 0x91117fff] limit: 91117fff mem

[DEBUG] PCI: 00:12.0 10 * [0x91118000 - 0x91119fff] limit: 91119fff mem

[DEBUG] PCI: 00:0d.2 10 * [0x9111a000 - 0x9111afff] limit: 9111afff mem

[DEBUG] PCI: 00:0f.0 10 * [0x9111b000 - 0x9111bfff] limit: 9111bfff mem

[DEBUG] PCI: 00:0f.1 10 * [0x9111c000 - 0x9111cfff] limit: 9111cfff mem

[DEBUG] PCI: 00:0f.2 10 * [0x9111d000 - 0x9111dfff] limit: 9111dfff mem

[DEBUG] PCI: 00:17.0 10 * [0x9111e000 - 0x9111efff] limit: 9111efff mem

[DEBUG] PCI: 00:17.0 18 * [0x9111f000 - 0x9111ffff] limit: 9111ffff mem

[DEBUG] PCI: 00:17.3 10 * [0x91120000 - 0x91120fff] limit: 91120fff mem

[DEBUG] PCI: 00:17.3 18 * [0x91121000 - 0x91121fff] limit: 91121fff mem

[DEBUG] PCI: 00:18.0 10 * [0x91122000 - 0x91122fff] limit: 91122fff mem

[DEBUG] PCI: 00:18.0 18 * [0x91123000 - 0x91123fff] limit: 91123fff mem

[DEBUG] PCI: 00:18.2 18 * [0x91124000 - 0x91124fff] limit: 91124fff mem

[DEBUG] PCI: 00:19.2 10 * [0x91125000 - 0x91125fff] limit: 91125fff mem

[DEBUG] PCI: 00:19.2 18 * [0x91126000 - 0x91126fff] limit: 91126fff mem

[DEBUG] PCI: 00:12.0 24 * [0x91127000 - 0x911277ff] limit: 911277ff mem

[DEBUG] PCI: 00:12.0 14 * [0x91128000 - 0x911280ff] limit: 911280ff mem

[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done

[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===

[DEBUG] PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64

[DEBUG] PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64

[DEBUG] PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io

[DEBUG] PCI: 00:0c.0 10 <- [0x0091110000 - 0x0091113fff] size 0x00004000 gran 0x0e mem64

[DEBUG] PCI: 00:0d.2 10 <- [0x009111a000 - 0x009111afff] size 0x00001000 gran 0x0c mem

[DEBUG] PCI: 00:0e.0 10 <- [0x0091114000 - 0x0091117fff] size 0x00004000 gran 0x0e mem64

[DEBUG] PCI: 00:0e.0 20 <- [0x0091000000 - 0x00910fffff] size 0x00100000 gran 0x14 mem64

[DEBUG] PCI: 00:0f.0 10 <- [0x009111b000 - 0x009111bfff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:0f.1 10 <- [0x009111c000 - 0x009111cfff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:0f.2 10 <- [0x009111d000 - 0x009111dfff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:12.0 10 <- [0x0091118000 - 0x0091119fff] size 0x00002000 gran 0x0d mem

[DEBUG] PCI: 00:12.0 14 <- [0x0091128000 - 0x00911280ff] size 0x00000100 gran 0x08 mem

[DEBUG] PCI: 00:12.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io

[DEBUG] PCI: 00:12.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io

[DEBUG] PCI: 00:12.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io

[DEBUG] PCI: 00:12.0 24 <- [0x0091127000 - 0x00911277ff] size 0x00000800 gran 0x0b mem

[DEBUG] PCI: 00:15.0 10 <- [0x0091100000 - 0x009110ffff] size 0x00010000 gran 0x10 mem64

[DEBUG] PCI: 00:17.0 10 <- [0x009111e000 - 0x009111efff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:17.0 18 <- [0x009111f000 - 0x009111ffff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:17.3 10 <- [0x0091120000 - 0x0091120fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:17.3 18 <- [0x0091121000 - 0x0091121fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:18.0 10 <- [0x0091122000 - 0x0091122fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:18.0 18 <- [0x0091123000 - 0x0091123fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:18.2 18 <- [0x0091124000 - 0x0091124fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:19.2 10 <- [0x0091125000 - 0x0091125fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:19.2 18 <- [0x0091126000 - 0x0091126fff] size 0x00001000 gran 0x0c mem64

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64

[DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[INFO ] Done setting resources.

[INFO ] Done allocating resources.

[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 957 ms

[DEBUG] WEAK: src/soc/intel/apollolake/lockdown.c/soc_lockdown_config called

[DEBUG] BS: BS_DEV_RESOURCES exit times (exec / console): 0 / 8 ms

[INFO ] full_reset() called!

[DEBUG] CSE is not in normal state, resetting

?[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x8b05 in mcache @0xfef09e4c

[DEBUG] BS: bootblock times (exec / console): total (unknown) / 21 ms





[NOTE ] coreboot-4.17-528-g046541b246-dirty Fri Jul 8 14:25:24 UTC 2022 romstage starting (log level: 7)...

[INFO ] CPU: Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz

[INFO ] CPU: ID 706a1, Geminilake B0, ucode: 00000039

[INFO ] CPU: AES Supported, TXT Not Supported, VT Supported

[INFO ] MCH: device id 31f0 (rev 03) is Geminilake

[INFO ] PCH: device id 31e8 (rev 03) is Geminilake

[INFO ] IGD: device id 3184 (rev 03) is Geminilake

[DEBUG] pm1_sts: 0000 pm1_en: 0100 pm1_cnt: 00000000

[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000

[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000

[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000

[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000

[DEBUG] prsts: 00000000

[DEBUG] tco_sts: 0000 0000

[DEBUG] gen_pmcon1: 04004004 gen_pmcon2: 00003a00 gen_pmcon3: 00000000

[DEBUG] prev_sleep_state 0

[INFO ] CBFS: Found 'fspm.bin' @0x50a80 size 0x2cb68 in mcache @0xfef0a020

[DEBUG] FMAP: area RW_MRC_CACHE found @ 5d0000 (65536 bytes)

[DEBUG] FMAP: area RW_VAR_MRC_CACHE found @ 5e0000 (65536 bytes)

[DEBUG] CBMEM:

[DEBUG] IMD: root @ 0x79fff000 254 entries.

[DEBUG] IMD: root @ 0x79ffec00 62 entries.

[DEBUG] External stage cache:

[DEBUG] IMD: root @ 0x7afff000 254 entries.

[DEBUG] IMD: root @ 0x7affec00 62 entries.

[DEBUG] FMAP: area RW_MRC_CACHE found @ 5d0000 (65536 bytes)

[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.

[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000

[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.

[INFO ] REGF update can't fit. Will empty.

[DEBUG] MRC: updated 'RW_MRC_CACHE'.

[DEBUG] CPU: frequency set to 2700 MHz

[DEBUG] FMAP: area RW_VAR_MRC_CACHE found @ 5e0000 (65536 bytes)

[DEBUG] MRC: Checking cached data update for 'RW_VAR_MRC_CACHE'.

[DEBUG] MRC: cache data 'RW_VAR_MRC_CACHE' needs update.

[DEBUG] MRC: updated 'RW_VAR_MRC_CACHE'.

[DEBUG] 4 DIMMs found

[DEBUG] SMM Memory Map

[DEBUG] SMRAM : 0x7a000000 0x1000000

[DEBUG] Subregion 0: 0x7a000000 0xf00000

[DEBUG] Subregion 1: 0x7af00000 0x100000

[DEBUG] Subregion 2: 0x7b000000 0x0

[DEBUG] top_of_ram = 0x7a000000

[DEBUG] Normal boot

[INFO ] CBFS: Found 'fallback/postcar' @0xad400 size 0x587c in mcache @0xfef0a0f8

[DEBUG] Loading module at 0x79bcf000 with entry 0x79bcf031. filesize: 0x5460 memsize: 0xb7d0

[DEBUG] Processing 247 relocs. Offset value of 0x77bcf000

[DEBUG] BS: romstage times (exec / console): total (unknown) / 274 ms





[NOTE ] coreboot-4.17-528-g046541b246-dirty Fri Jul 8 14:25:24 UTC 2022 postcar starting (log level: 7)...

[DEBUG] Normal boot

[INFO ] CBFS: Found 'fallback/ramstage' @0x2dc80 size 0x1a60f in mcache @0x79bdd0dc

[DEBUG] Loading module at 0x79b7a000 with entry 0x79b7a000. filesize: 0x38658 memsize: 0x53550

[DEBUG] Processing 3856 relocs. Offset value of 0x75b7a000

[DEBUG] BS: postcar times (exec / console): total (unknown) / 41 ms





[NOTE ] coreboot-4.17-528-g046541b246-dirty Fri Jul 8 14:25:24 UTC 2022 ramstage starting (log level: 7)...

[DEBUG] Normal boot

[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x8c40 size 0x25000 in mcache @0x79bdd0ac

[DEBUG] microcode: sig=0x706a1 pf=0x1 revision=0x39

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[INFO ] CBFS: Found 'fsps.bin' @0x7d640 size 0x2f000 in mcache @0x79bdd234

[DEBUG] Detected 4 core, 4 thread CPU.

[INFO ] Will perform SMM setup.

[INFO ] CPU: Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz.

[INFO ] LAPIC 0x0 in XAPIC mode.

[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178

[DEBUG] Processing 18 relocs. Offset value of 0x00030000

[DEBUG] Attempting to start 3 APs

[DEBUG] Waiting for 10ms after sending INIT.

[DEBUG] Waiting for SIPI to complete...

[DEBUG] done.

[INFO ] LAPIC 0x6 in XAPIC mode.

[INFO ] LAPIC 0x4 in XAPIC mode.

[DEBUG] Waiting for SIPI to complete...

[DEBUG] done.

[INFO ] AP: slot 1 apic_id 6, MCU rev: 0x00000039

[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x00000039

[INFO ] LAPIC 0x2 in XAPIC mode.

[INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000039

[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0

[DEBUG] Processing 11 relocs. Offset value of 0x00038000

[DEBUG] smm_module_setup_stub: stack_top = 0x7a002000

[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800

[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c

[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000

[DEBUG] SMM Module: stub loaded at 38000. Will call 0x79b922aa

[DEBUG] Installing permanent SMM handler to 0x7a000000

[DEBUG] FX_SAVE [0x7aeff800-0x7af00000]

[DEBUG] HANDLER [0x7aefc000-0x7aeff790]



[DEBUG] CPU 0

[DEBUG] ss0 [0x7aefbc00-0x7aefc000]

[DEBUG] stub0 [0x7aef4000-0x7aef41e0]



[DEBUG] CPU 1

[DEBUG] ss1 [0x7aefb800-0x7aefbc00]

[DEBUG] stub1 [0x7aef3c00-0x7aef3de0]



[DEBUG] CPU 2

[DEBUG] ss2 [0x7aefb400-0x7aefb800]

[DEBUG] stub2 [0x7aef3800-0x7aef39e0]



[DEBUG] CPU 3

[DEBUG] ss3 [0x7aefb000-0x7aefb400]

[DEBUG] stub3 [0x7aef3400-0x7aef35e0]



[DEBUG] stacks [0x7a000000-0x7a002000]

[DEBUG] Loading module at 0x7aefc000 with entry 0x7aefcdf9. filesize: 0x3690 memsize: 0x3790

[DEBUG] Processing 218 relocs. Offset value of 0x7aefc000

[DEBUG] Loading module at 0x7aef4000 with entry 0x7aef4000. filesize: 0x1e0 memsize: 0x1e0

[DEBUG] Processing 11 relocs. Offset value of 0x7aef4000

[DEBUG] smm_module_setup_stub: stack_top = 0x7a002000

[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800

[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c

[DEBUG] smm_module_setup_stub: runtime.smm_size = 0xf00000

[DEBUG] SMM Module: placing smm entry code at 7aef3c00, cpu # 0x1

[DEBUG] SMM Module: placing smm entry code at 7aef3800, cpu # 0x2

[DEBUG] SMM Module: placing smm entry code at 7aef3400, cpu # 0x3

[DEBUG] SMM Module: stub loaded at 7aef4000. Will call 0x7aefcdf9

[DEBUG] Clearing SMI status registers

[DEBUG] SMI_STS: TCO 

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeeb800, cpu = 2

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeeb400, cpu = 3

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeebc00, cpu = 1

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7aeec000, cpu = 0

[DEBUG] Relocation complete.

[INFO ] Initializing CPU #0

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[INFO ] CPU #0 initialized

[INFO ] Initializing CPU #3

[INFO ] Initializing CPU #1

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[INFO ] Initializing CPU #2

[INFO ] microcode: load microcode patch

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[ERROR] microcode: Update failed

[INFO ] CPU #3 initialized

[INFO ] CPU #1 initialized

[DEBUG] CPU: vendor Intel device 706a1

[DEBUG] CPU: family 06, model 7a, stepping 01

[INFO ] microcode: load microcode patch

[ERROR] microcode: Update failed

[INFO ] CPU #2 initialized

[INFO ] bsp_do_flight_plan done after 411 msecs.

[DEBUG] Enabling SMIs.

[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 179 / 365 ms

[INFO ] CBFS: Found 'vbt.bin' @0xac680 size 0x559 in mcache @0x79bdd258

[INFO ] Found a VBT of 5632 bytes after decompression

[WARN ] PCI:00.1: Could not disable the device

[WARN ] PCI:03.0: Could not disable the device

[WARN ] PCI:0d.0: Could not disable the device

[WARN ] PCI:0d.1: Could not disable the device

[WARN ] PCI:0d.3: Could not disable the device

[WARN ] PCI:1a.0: Could not disable the device

[DEBUG] WEAK: src/soc/intel/apollolake/chip.c/mainboard_silicon_init_params called

[INFO ] FSPS returned 0

[INFO ] ITSS IRQ Polarities Before:

[INFO ] IPC0: 0xffffeef8

[INFO ] IPC1: 0xffffffff

[INFO ] IPC2: 0xffffffff

[INFO ] IPC3: 0x00ffffff

[INFO ] ITSS IRQ Polarities After:

[INFO ] IPC0: 0xffffeef8

[INFO ] IPC1: 0x0003ffff

[INFO ] IPC2: 0x00000000

[INFO ] IPC3: 0x00000000

[INFO ] CPU TDP = 6 Watts

[INFO ] CPU PL1 = 10 Watts

[INFO ] CPU PL2 = 15 Watts

[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 164 / 107 ms

[INFO ] Enumerating buses...

[DEBUG] Root Device scanning...

[DEBUG] DOMAIN: 0000 enabled

[DEBUG] CPU_CLUSTER: 0 enabled

[DEBUG] MMIO: fed40000 enabled

[DEBUG] DOMAIN: 0000 scanning...

[DEBUG] PCI: pci_scan_bus for bus 00

[DEBUG] PCI: 00:00.0 [8086/31f0] enabled

[DEBUG] PCI: 00:00.1 [8086/318c] disabled

[DEBUG] PCI: 00:02.0 [8086/3184] enabled

[DEBUG] PCI: 00:0c.0 [8086/31dc] enabled

[DEBUG] PCI: 00:0d.0 [8086/3192] disabled

[DEBUG] PCI: 00:0d.1 [8086/3194] disabled

[DEBUG] PCI: 00:0d.2 [8086/3196] enabled

[DEBUG] PCI: 00:0d.3 [8086/31ec] disabled

[DEBUG] PCI: 00:0e.0 [8086/3198] enabled

[DEBUG] No CMOS option 'me_state'.

[DEBUG] PCI: 00:0f.0 [8086/319a] enabled

[DEBUG] PCI: 00:0f.1 [8086/319c] enabled

[DEBUG] PCI: 00:0f.2 [8086/319e] enabled

[DEBUG] PCI: 00:12.0 [8086/31e3] enabled

[DEBUG] PCI: 00:15.0 [8086/31a8] enabled

[DEBUG] PCI: 00:17.0 [8086/31b4] enabled

[DEBUG] PCI: 00:17.3 [8086/31ba] enabled

[DEBUG] PCI: 00:18.0 [8086/31bc] enabled

[DEBUG] PCI: 00:18.2 [8086/31c0] enabled

[DEBUG] PCI: 00:19.2 [8086/31c6] enabled

[DEBUG] PCI: 00:1f.0 [8086/31e8] enabled

[DEBUG] PCI: 00:1f.1 [8086/31d4] disabled

[WARN ] PCI: Leftover static devices:

[WARN ] PCI: 00:00.2

[WARN ] PCI: 00:03.0

[WARN ] PCI: 00:11.0

[WARN ] PCI: 00:13.0

[WARN ] PCI: 00:13.1

[WARN ] PCI: 00:13.2

[WARN ] PCI: 00:13.3

[WARN ] PCI: 00:14.0

[WARN ] PCI: 00:14.1

[WARN ] PCI: 00:15.1

[WARN ] PCI: 00:16.0

[WARN ] PCI: 00:16.1

[WARN ] PCI: 00:16.2

[WARN ] PCI: 00:16.3

[WARN ] PCI: 00:17.1

[WARN ] PCI: 00:17.2

[WARN ] PCI: 00:18.1

[WARN ] PCI: 00:18.3

[WARN ] PCI: 00:19.0

[WARN ] PCI: 00:19.1

[WARN ] PCI: 00:1a.0

[WARN ] PCI: 00:1b.0

[WARN ] PCI: 00:1c.0

[WARN ] PCI: 00:1d.0

[WARN ] PCI: 00:1e.0

[WARN ] PCI: Check your devicetree.cb.

[DEBUG] PCI: 00:02.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:02.0 finished in 0 msecs

[DEBUG] PCI: 00:0c.0 scanning...

[DEBUG] GENERIC: 0.0 enabled

[DEBUG] scan_bus: bus PCI: 00:0c.0 finished in 3 msecs

[DEBUG] PCI: 00:0e.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:0e.0 finished in 0 msecs

[DEBUG] PCI: 00:15.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:15.0 finished in 0 msecs

[DEBUG] PCI: 00:17.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:17.0 finished in 0 msecs

[DEBUG] PCI: 00:17.3 scanning...

[DEBUG] scan_bus: bus PCI: 00:17.3 finished in 0 msecs

[DEBUG] PCI: 00:19.2 scanning...

[DEBUG] scan_bus: bus PCI: 00:19.2 finished in 0 msecs

[DEBUG] PCI: 00:1f.0 scanning...

[DEBUG] PNP: 004e.0 enabled

[DEBUG] PNP: 004e.1 disabled

[DEBUG] PNP: 004e.2 disabled

[DEBUG] PNP: 004e.4 disabled

[DEBUG] PNP: 004e.5 disabled

[DEBUG] PNP: 004e.6 enabled

[DEBUG] PNP: 004e.a disabled

[DEBUG] PNP: 004e.f disabled

[DEBUG] PNP: 004e.10 disabled

[DEBUG] PNP: 004e.11 disabled

[DEBUG] PNP: 004e.12 disabled

[DEBUG] PNP: 004e.13 disabled

[DEBUG] PNP: 004e.14 disabled

[DEBUG] PNP: 004e.17 disabled

[DEBUG] PNP: 004e.18 disabled

[DEBUG] PNP: 004e.19 disabled

[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 61 msecs

[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 352 msecs

[DEBUG] scan_bus: bus Root Device finished in 374 msecs

[INFO ] done

[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 390 ms

[DEBUG] FMAP: area UNIFIED_MRC_CACHE found @ 5c0000 (196608 bytes)

[INFO ] MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.

[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms

[DEBUG] found VGA at PCI: 00:02.0

[DEBUG] Setting up VGA for PCI: 00:02.0

[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000

[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device

[INFO ] Allocating resources...

[INFO ] Reading resources...

[DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000

[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x8000

[INFO ] Available memory above 4GB: 6144M

[ERROR] PNP: 004e.0 missing read_resources

[INFO ] Done reading resources.

[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===

[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===

[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff

[DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)

[DEBUG] update_constraints: PCI: 00:1f.0 84 base 000006a0 limit 000006af io (fixed)

[DEBUG] update_constraints: PCI: 00:1f.0 88 base 00000080 limit 0000008f io (fixed)

[DEBUG] update_constraints: PNP: 004e.6 60 base 00000060 limit 00000060 io (fixed)

[DEBUG] update_constraints: PNP: 004e.6 62 base 00000064 limit 00000064 io (fixed)

[INFO ] DOMAIN: 0000: Resource ranges:

[INFO ] * Base: 1000, Size: f000, Tag: 100

[DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io

[DEBUG] PCI: 00:12.0 20 * [0x1040 - 0x105f] limit: 105f io

[DEBUG] PCI: 00:12.0 18 * [0x1060 - 0x1067] limit: 1067 io

[DEBUG] PCI: 00:12.0 1c * [0x1068 - 0x106b] limit: 106b io

[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done

[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff

[DEBUG] update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 02 base fed64000 limit fed64fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 03 base fed65000 limit fed65fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 04 base 00000000 limit 0009ffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 05 base 000c0000 limit 79ffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 06 base 7a000000 limit 7fffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 07 base 100000000 limit 27fffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 08 base 000a0000 limit 000bffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 09 base 000c0000 limit 000fffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0a base 11800000 limit 11bfffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0b base 11000000 limit 117fffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0c base 12000000 limit 120fffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0d base 12150000 limit 12150fff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0e base 12140000 limit 1214ffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 0f base 10000000 limit 10ffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 10 base 11c00000 limit 11ffffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:00.0 11 base 12100000 limit 1213ffff mem (fixed)

[DEBUG] update_constraints: PCI: 00:18.2 10 base ddffc000 limit ddffcfff mem (fixed)

[INFO ] DOMAIN: 0000: Resource ranges:

[INFO ] * Base: 80000000, Size: 5dffc000, Tag: 200

[INFO ] * Base: ddffd000, Size: 2003000, Tag: 200

[INFO ] * Base: f0000000, Size: ed10000, Tag: 200

[INFO ] * Base: fed18000, Size: 4c000, Tag: 200

[INFO ] * Base: fed66000, Size: 129a000, Tag: 200

[INFO ] * Base: 280000000, Size: 7d80000000, Tag: 100200

[DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem

[DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem

[DEBUG] PCI: 00:0e.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem

[DEBUG] PCI: 00:15.0 10 * [0x91100000 - 0x9110ffff] limit: 9110ffff mem

[DEBUG] PCI: 00:0c.0 10 * [0x91110000 - 0x91113fff] limit: 91113fff mem

[DEBUG] PCI: 00:0e.0 10 * [0x91114000 - 0x91117fff] limit: 91117fff mem

[DEBUG] PCI: 00:12.0 10 * [0x91118000 - 0x91119fff] limit: 91119fff mem

[DEBUG] PCI: 00:0d.2 10 * [0x9111a000 - 0x9111afff] limit: 9111afff mem

[DEBUG] PCI: 00:0f.0 10 * [0x9111b000 - 0x9111bfff] limit: 9111bfff mem

[DEBUG] PCI: 00:0f.1 10 * [0x9111c000 - 0x9111cfff] limit: 9111cfff mem

[DEBUG] PCI: 00:0f.2 10 * [0x9111d000 - 0x9111dfff] limit: 9111dfff mem

[DEBUG] PCI: 00:17.0 10 * [0x9111e000 - 0x9111efff] limit: 9111efff mem

[DEBUG] PCI: 00:17.0 18 * [0x9111f000 - 0x9111ffff] limit: 9111ffff mem

[DEBUG] PCI: 00:17.3 10 * [0x91120000 - 0x91120fff] limit: 91120fff mem

[DEBUG] PCI: 00:17.3 18 * [0x91121000 - 0x91121fff] limit: 91121fff mem

[DEBUG] PCI: 00:18.0 10 * [0x91122000 - 0x91122fff] limit: 91122fff mem

[DEBUG] PCI: 00:18.0 18 * [0x91123000 - 0x91123fff] limit: 91123fff mem

[DEBUG] PCI: 00:18.2 18 * [0x91124000 - 0x91124fff] limit: 91124fff mem

[DEBUG] PCI: 00:19.2 10 * [0x91125000 - 0x91125fff] limit: 91125fff mem

[DEBUG] PCI: 00:19.2 18 * [0x91126000 - 0x91126fff] limit: 91126fff mem

[DEBUG] PCI: 00:12.0 24 * [0x91127000 - 0x911277ff] limit: 911277ff mem

[DEBUG] PCI: 00:12.0 14 * [0x91128000 - 0x911280ff] limit: 911280ff mem

[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done

[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===

[DEBUG] PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64

[DEBUG] PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64

[DEBUG] PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io

[DEBUG] PCI: 00:0c.0 10 <- [0x0091110000 - 0x0091113fff] size 0x00004000 gran 0x0e mem64

[DEBUG] PCI: 00:0d.2 10 <- [0x009111a000 - 0x009111afff] size 0x00001000 gran 0x0c mem

[DEBUG] PCI: 00:0e.0 10 <- [0x0091114000 - 0x0091117fff] size 0x00004000 gran 0x0e mem64

[DEBUG] PCI: 00:0e.0 20 <- [0x0091000000 - 0x00910fffff] size 0x00100000 gran 0x14 mem64

[DEBUG] PCI: 00:0f.0 10 <- [0x009111b000 - 0x009111bfff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:0f.1 10 <- [0x009111c000 - 0x009111cfff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:0f.2 10 <- [0x009111d000 - 0x009111dfff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:12.0 10 <- [0x0091118000 - 0x0091119fff] size 0x00002000 gran 0x0d mem

[DEBUG] PCI: 00:12.0 14 <- [0x0091128000 - 0x00911280ff] size 0x00000100 gran 0x08 mem

[DEBUG] PCI: 00:12.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io

[DEBUG] PCI: 00:12.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io

[DEBUG] PCI: 00:12.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io

[DEBUG] PCI: 00:12.0 24 <- [0x0091127000 - 0x00911277ff] size 0x00000800 gran 0x0b mem

[DEBUG] PCI: 00:15.0 10 <- [0x0091100000 - 0x009110ffff] size 0x00010000 gran 0x10 mem64

[DEBUG] PCI: 00:17.0 10 <- [0x009111e000 - 0x009111efff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:17.0 18 <- [0x009111f000 - 0x009111ffff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:17.3 10 <- [0x0091120000 - 0x0091120fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:17.3 18 <- [0x0091121000 - 0x0091121fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:18.0 10 <- [0x0091122000 - 0x0091122fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:18.0 18 <- [0x0091123000 - 0x0091123fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:18.2 18 <- [0x0091124000 - 0x0091124fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:19.2 10 <- [0x0091125000 - 0x0091125fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:19.2 18 <- [0x0091126000 - 0x0091126fff] size 0x00001000 gran 0x0c mem64

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64

[DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[ERROR] LPC IO decode base 0!

[INFO ] Done setting resources.

[INFO ] Done allocating resources.

[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 957 ms

[DEBUG] WEAK: src/soc/intel/apollolake/lockdown.c/soc_lockdown_config called

[DEBUG] BS: BS_DEV_RESOURCES exit times (exec / console): 0 / 8 ms

[INFO ] Enabling resources...

[DEBUG] PCI: 00:00.0 subsystem <- 8086/31f0

[DEBUG] PCI: 00:00.0 cmd <- 07

[DEBUG] PCI: 00:02.0 subsystem <- 8086/3184

[DEBUG] PCI: 00:02.0 cmd <- 03

[DEBUG] PCI: 00:0c.0 subsystem <- 8086/31dc

[DEBUG] PCI: 00:0c.0 cmd <- 02

[DEBUG] PCI: 00:0d.2 subsystem <- 8086/3196

[DEBUG] PCI: 00:0d.2 cmd <- 406

[DEBUG] PCI: 00:0e.0 subsystem <- 8086/3198

[DEBUG] PCI: 00:0e.0 cmd <- 06

[DEBUG] PCI: 00:0f.0 subsystem <- 8086/319a

[DEBUG] PCI: 00:0f.0 cmd <- 06

[DEBUG] PCI: 00:0f.1 subsystem <- ffff/ffff

[DEBUG] PCI: 00:0f.1 cmd <- ffff

[DEBUG] PCI: 00:0f.2 subsystem <- ffff/ffff

[DEBUG] PCI: 00:0f.2 cmd <- ffff

[DEBUG] PCI: 00:12.0 subsystem <- 8086/31e3

[DEBUG] PCI: 00:12.0 cmd <- 03

[DEBUG] PCI: 00:15.0 subsystem <- 8086/31a8

[DEBUG] PCI: 00:15.0 cmd <- 02

[DEBUG] PCI: 00:17.0 subsystem <- 8086/31b4

[DEBUG] PCI: 00:17.0 cmd <- 02

[DEBUG] PCI: 00:17.3 subsystem <- 8086/31ba

[DEBUG] PCI: 00:17.3 cmd <- 02

[DEBUG] PCI: 00:18.0 subsystem <- 8086/31bc

[DEBUG] PCI: 00:18.0 cmd <- 02

[DEBUG] PCI: 00:18.2 subsystem <- 8086/31c0

[DEBUG] PCI: 00:18.2 cmd <- 06

[DEBUG] PCI: 00:19.2 subsystem <- 8086/31c6

[DEBUG] PCI: 00:19.2 cmd <- 02

[DEBUG] PCI: 00:1f.0 subsystem <- 8086/31e8

[DEBUG] PCI: 00:1f.0 cmd <- 07

[INFO ] done.

[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 154 ms

[INFO ] Initialized TPM device Intel iTPM revision 0

[DEBUG] tis_open: Intel PTT is active.

[INFO ] tlcl_send_startup: Startup return code is 0

[INFO ] TPM: setup succeeded

[DEBUG] FMAP: area FPF_STATUS found @ 5b0000 (65536 bytes)

[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000

[ERROR] reply is too large

[DEBUG] BS: BS_DEV_INIT entry times (exec / console): 6 / 38 ms

[INFO ] Initializing devices...

[DEBUG] CPU_CLUSTER: 0 init

[DEBUG] CPU_CLUSTER: 0 init finished in 0 msecs

[DEBUG] PCI: 00:00.0 init

[DEBUG] PCI: 00:00.0 init finished in 0 msecs

[DEBUG] PCI: 00:02.0 init

[INFO ] GMA: Found VBT in CBFS

[INFO ] GMA: Found valid VBT in CBFS

[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

[INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000

[DEBUG] PCI: 00:02.0 init finished in 25 msecs

[DEBUG] PCI: 00:0d.2 init

[DEBUG] PCI: 00:0d.2 init finished in 0 msecs

[DEBUG] PCI: 00:0e.0 init

[DEBUG] azalia_audio: base = 0x91114000

[DEBUG] azalia_audio: codec_mask = 05

[DEBUG] azalia_audio: Initializing codec #2

[DEBUG] azalia_audio: codec viddid: 8086280d

[DEBUG] azalia_audio: verb_size: 16

[DEBUG] azalia_audio: verb loaded.

[DEBUG] azalia_audio: Initializing codec #0

[DEBUG] azalia_audio: codec viddid: 10ec0269

[DEBUG] azalia_audio: verb_size: 60

[DEBUG] azalia_audio: verb loaded.

[DEBUG] PCI: 00:0e.0 init finished in 54 msecs

[DEBUG] PCI: 00:0f.0 init

[DEBUG] PCI: 00:0f.0 init finished in 0 msecs

[DEBUG] PCI: 00:0f.1 init

[DEBUG] PCI: 00:0f.1 init finished in 0 msecs

[DEBUG] PCI: 00:0f.2 init

[DEBUG] PCI: 00:0f.2 init finished in 0 msecs

[DEBUG] PCI: 00:12.0 init

[DEBUG] PCI: 00:12.0 init finished in 0 msecs

[DEBUG] PCI: 00:15.0 init

[DEBUG] PCI: 00:15.0 init finished in 0 msecs

[DEBUG] PCI: 00:17.0 init

[DEBUG] I2C bus 4 version 0x3132312a

[INFO ] DW I2C bus 4 at 0x9111e000 (400 KHz)

[DEBUG] PCI: 00:17.0 init finished in 9 msecs

[DEBUG] PCI: 00:17.3 init

[DEBUG] I2C bus 7 version 0x3132312a

[INFO ] DW I2C bus 7 at 0x91120000 (400 KHz)

[DEBUG] PCI: 00:17.3 init finished in 9 msecs

[DEBUG] PCI: 00:1f.0 init

[DEBUG] RTC Init

[WARN ] RTC: Clear requested

[DEBUG] PCI: 00:1f.0 init finished in 8 msecs

[DEBUG] PNP: 004e.6 init

[DEBUG] PNP: 004e.6 init finished in 14 msecs

[INFO ] Devices initialized

[DEBUG] BS: BS_DEV_INIT run times (exec / console): 23 / 232 ms

[DEBUG] FMAP: area SMMSTORE found @ 5f0000 (262144 bytes)

[DEBUG] smm store: 64 # blocks with size 0x1000

[INFO ] SMMSTORE: Setting up SMI handler

[DEBUG] ME: Version: Unavailable

[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 2 / 21 ms

[INFO ] Finalize devices...

[DEBUG] PCI: 00:0f.0 final

[INFO ] Devices finalized

[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 11 ms

[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x48b00 size 0x2ecf in mcache @0x79bdd198

[WARN ] CBFS: 'fallback/slic' not found.

[INFO ] ACPI: Writing ACPI tables at 79b09000.

[DEBUG] ACPI: * FACS

[DEBUG] ACPI: * DSDT

[DEBUG] ACPI: * FADT

[DEBUG] SCI is IRQ9

[DEBUG] ACPI: added table 1/32, length now 40

[DEBUG] ACPI: * SSDT

[DEBUG] PCI space above 4GB MMIO is at 0x280000000, len = 0x7d80000000

[DEBUG] Found 1 CPU(s) with 4/4 physical/logical core(s) each.

[INFO ] Turbo is available and visible

[DEBUG] PSS: 1101MHz power 6000 control 0x1b00 status 0x1b00

[DEBUG] PSS: 1100MHz power 6000 control 0xb00 status 0xb00

[DEBUG] PSS: 1000MHz power 5388 control 0xa00 status 0xa00

[DEBUG] PSS: 800MHz power 4213 control 0x800 status 0x800

[DEBUG] PSS: 1101MHz power 6000 control 0x1b00 status 0x1b00

[DEBUG] PSS: 1100MHz power 6000 control 0xb00 status 0xb00

[DEBUG] PSS: 1000MHz power 5388 control 0xa00 status 0xa00

[DEBUG] PSS: 800MHz power 4213 control 0x800 status 0x800

[DEBUG] PSS: 1101MHz power 6000 control 0x1b00 status 0x1b00

[DEBUG] PSS: 1100MHz power 6000 control 0xb00 status 0xb00

[DEBUG] PSS: 1000MHz power 5388 control 0xa00 status 0xa00

[DEBUG] PSS: 800MHz power 4213 control 0x800 status 0x800

[DEBUG] PSS: 1101MHz power 6000 control 0x1b00 status 0x1b00

[DEBUG] PSS: 1100MHz power 6000 control 0xb00 status 0xb00

[DEBUG] PSS: 1000MHz power 5388 control 0xa00 status 0xa00

[DEBUG] PSS: 800MHz power 4213 control 0x800 status 0x800

[INFO ] \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0

[DEBUG] ACPI: added table 2/32, length now 44

[DEBUG] ACPI: * MCFG

[DEBUG] ACPI: added table 3/32, length now 48

[DEBUG] ACPI: * TPM2

[DEBUG] TPM2 log created at 0x79af9000

[DEBUG] ACPI: added table 4/32, length now 52

[DEBUG] ACPI: * MADT

[DEBUG] SCI is IRQ9

[DEBUG] ACPI: added table 5/32, length now 56

[DEBUG] current = 79b0cbf0

[DEBUG] ACPI: * DMAR

[DEBUG] ACPI: added table 6/32, length now 60

[DEBUG] ACPI: added table 7/32, length now 64

[DEBUG] ACPI: * HPET

[DEBUG] ACPI: added table 8/32, length now 68

[INFO ] ACPI: done.

[DEBUG] ACPI tables: 15664 bytes.

[DEBUG] smbios_write_tables: 79af1000

[INFO ] Create SMBIOS type 16

[INFO ] Create SMBIOS type 17

[INFO ] Create SMBIOS type 20

[INFO ] GENERIC: 0.0 (WIFI Device)

[DEBUG] SMBIOS tables: 1308 bytes.

[DEBUG] Writing table forward entry at 0x00000500

[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum b62b

[DEBUG] Writing coreboot table at 0x79b2d000

[INFO ] CBFS: Found 'cmos_layout.bin' @0xacd80 size 0x620 in mcache @0x79bdd2b0

[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES

[DEBUG] 1. 0000000000001000-000000000009ffff: RAM

[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED

[DEBUG] 3. 0000000000100000-000000000fffffff: RAM

[DEBUG] 4. 0000000010000000-0000000012150fff: RESERVED

[DEBUG] 5. 0000000012151000-0000000079af0fff: RAM

[DEBUG] 6. 0000000079af1000-0000000079b79fff: CONFIGURATION TABLES

[DEBUG] 7. 0000000079b7a000-0000000079bcdfff: RAMSTAGE

[DEBUG] 8. 0000000079bce000-0000000079ffffff: CONFIGURATION TABLES

[DEBUG] 9. 000000007a000000-000000007fffffff: RESERVED

[DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED

[DEBUG] 11. 00000000fed10000-00000000fed17fff: RESERVED

[DEBUG] 12. 00000000fed64000-00000000fed65fff: RESERVED

[DEBUG] 13. 0000000100000000-000000027fffffff: RAM

[DEBUG] Wrote coreboot table at: 0x79b2d000, 0xb24 bytes, checksum dd3b

[DEBUG] coreboot table: 2876 bytes.

[DEBUG] IMD ROOT 0. 0x79fff000 0x00001000

[DEBUG] IMD SMALL 1. 0x79ffe000 0x00001000

[DEBUG] FSP MEMORY 2. 0x79bfe000 0x00400000

[DEBUG] CONSOLE 3. 0x79bde000 0x00020000

[DEBUG] RO MCACHE 4. 0x79bdd000 0x00000388

[DEBUG] TIME STAMP 5. 0x79bdc000 0x00000910

[DEBUG] MEM INFO 6. 0x79bdb000 0x00000768

[DEBUG] AFTER CAR 7. 0x79bce000 0x0000d000

[DEBUG] RAMSTAGE 8. 0x79b79000 0x00055000

[DEBUG] REFCODE 9. 0x79b4a000 0x0002f000

[DEBUG] SMM BACKUP 10. 0x79b3a000 0x00010000

[DEBUG] IGD OPREGION11. 0x79b36000 0x00003597

[DEBUG] SMM COMBUFFER12. 0x79b35000 0x00001000

[DEBUG] COREBOOT 13. 0x79b2d000 0x00008000

[DEBUG] ACPI 14. 0x79b09000 0x00024000

[DEBUG] TPM2 TCGLOG15. 0x79af9000 0x00010000

[DEBUG] SMBIOS 16. 0x79af1000 0x00008000

[DEBUG] IMD small region:

[DEBUG] IMD ROOT 0. 0x79ffec00 0x00000400

[DEBUG] FSP RUNTIME 1. 0x79ffebe0 0x00000004

[DEBUG] FMAP 2. 0x79ffea00 0x000001dc

[DEBUG] POWER STATE 3. 0x79ffe9c0 0x00000040

[DEBUG] ROMSTAGE 4. 0x79ffe9a0 0x00000004

[DEBUG] ROMSTG STCK 5. 0x79ffe8e0 0x000000a8

[DEBUG] ACPI GNVS 6. 0x79ffe8a0 0x00000030

[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 2 / 537 ms

[DEBUG] MTRR: Physical address space:

[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6

[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0

[DEBUG] 0x00000000000c0000 - 0x0000000079ffffff size 0x79f40000 type 6

[DEBUG] 0x000000007a000000 - 0x000000007fffffff size 0x06000000 type 0

[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1

[DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0

[DEBUG] 0x0000000100000000 - 0x000000027fffffff size 0x180000000 type 6

[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] CPU physical address size: 39 bits

[DEBUG] MTRR: default type WB/UC MTRR counts: 6/6.

[DEBUG] MTRR: UC selected as default type.

[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: 1 base 0x000000007a000000 mask 0x0000007ffe000000 type 0

[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0

[DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1

[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] CPU physical address size: 39 bits

[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] CPU physical address size: 39 bits

[DEBUG] CPU physical address size: 39 bits

[DEBUG] MTRR: TEMPORARY Physical address space:

[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6

[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0

[DEBUG] 0x00000000000c0000 - 0x0000000079ffffff size 0x79f40000 type 6

[DEBUG] 0x000000007a000000 - 0x00000000ff7fffff size 0x85800000 type 0

[DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5

[DEBUG] 0x0000000100000000 - 0x000000027fffffff size 0x180000000 type 6

[DEBUG] MTRR: default type WB/UC MTRR counts: 11/6.

[DEBUG] MTRR: UC selected as default type.

[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: 1 base 0x000000007a000000 mask 0x0000007ffe000000 type 0

[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0

[DEBUG] MTRR: 3 base 0x00000000ff800000 mask 0x0000007fff800000 type 5

[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6



[DEBUG] MTRR check

[DEBUG] Fixed MTRRs : Enabled

[DEBUG] Variable MTRRs: Enabled



[DEBUG] BS: BS_WRITE_TABLES exit times (exec / console): 142 / 309 ms

[INFO ] CBFS: Found 'fallback/payload' @0xb2cc0 size 0xb8dc6 in mcache @0x79bdd31c

[DEBUG] Checking segment from ROM address 0xffdd3cec

[DEBUG] Checking segment from ROM address 0xffdd3d08

[DEBUG] Loading segment from ROM address 0xffdd3cec

[DEBUG] code (compression=1)

[DEBUG] New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xffdd3d24 filesize 0xb8d8e

[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x00000000000b8d8e

[DEBUG] using LZMA

[DEBUG] Loading segment from ROM address 0xffdd3d08

[DEBUG] Entry Point 0x00801626

[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 223 / 64 ms

[DEBUG] CSE FWSTS1: 0x80003052

[DEBUG] CSE FWSTS2: 0x3b220000

[DEBUG] CSE FWSTS3: 0x00000000

[DEBUG] CSE FWSTS4: 0x00080004

[DEBUG] CSE FWSTS5: 0x00000000

[DEBUG] CSE FWSTS6: 0x40000000

[DEBUG] ME: Manufacturing Mode : YES

[DEBUG] ME: FPF status : unknown

[INFO ] Disabling Heci using PCR

[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 8 / 38 ms

[DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 1 / 0 ms

[DEBUG] mp_park_aps done after 0 msecs.

[DEBUG] Jumping to boot code at 0x00801626(0x79b2d000)