|
|
|
|
|
coreboot-4.14-1258-gfbc46a3bfb Sat Jul 31 09:15:37 UTC 2021 bootblock starting (log level: 6)...
|
|
FMAP: Found "FLASH" version 1.1 at 0x10000.
|
|
FMAP: base = 0xfff00000 size = 0x100000 #areas = 4
|
|
FMAP: area COREBOOT found @ 10200 (982528 bytes)
|
|
CBFS: mcache @0xfeffae00 built for 16 files, used 0x344 of 0x4000 bytes
|
|
CBFS: Found 'fallback/romstage' @0x80 size 0xf058 in mcache @0xfeffae2c
|
|
BS: bootblock times (exec / console): total (unknown) / 24 ms
|
|
PROG_RUN: Setting MTRR to cache XIP stage. base: 0xfff10000, size: 0x00010000
|
|
|
|
|
|
coreboot-4.14-1258-gfbc46a3bfb Sat Jul 31 09:15:37 UTC 2021 romstage starting (log level: 6)...
|
|
SMBus controller enabled
|
|
Setting up static southbridge registers... done.
|
|
Disabling Watchdog reboot... done.
|
|
Setting up RAM controller.
|
|
FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)
|
|
Using cached raminit settings
|
|
2 CPU cores
|
|
Selected timings:
|
|
FSB: 1334MHz
|
|
DDR: 1067MHz
|
|
CAS: 7
|
|
tRAS: 20
|
|
tRP: 7
|
|
tRCD: 7
|
|
tWR: 8
|
|
tRFC: 86
|
|
tWTR: 4
|
|
tRRD: 4
|
|
tRTP: 4
|
|
Done clk crossing
|
|
Done I/O clk
|
|
Done launch
|
|
Done timings
|
|
RCOMP
|
|
Done ODT
|
|
Done RCOMP update
|
|
DDR3 Reset.
|
|
Done pre-jedec
|
|
MRS...
|
|
CH0: Found Rank 0
|
|
MRS done
|
|
Done jedec steps
|
|
Software initiated DDR3 reset.
|
|
MRS...
|
|
CH0: Found Rank 0
|
|
MRS done
|
|
Done post-jedec
|
|
Done dummy reads
|
|
Done rcven
|
|
Total memory: 2048 + 0 = 2048MiB
|
|
Done DRADRB
|
|
Done memory map
|
|
Done enhanced mode
|
|
Done PRCOMP
|
|
Done power settings
|
|
Done raminit
|
|
RAM initialization finished.
|
|
CBMEM:
|
|
IMD: root @ 0x7b7ff000 254 entries.
|
|
IMD: root @ 0x7b7fec00 62 entries.
|
|
FMAP: area COREBOOT found @ 10200 (982528 bytes)
|
|
External stage cache:
|
|
IMD: root @ 0x7bbff000 254 entries.
|
|
IMD: root @ 0x7bbfec00 62 entries.
|
|
Memory initialized
|
|
Done Egress Port
|
|
Done DMI setup
|
|
x4x late init complete
|
|
SMM Memory Map
|
|
SMRAM : 0x7ba00000 0x200000
|
|
Subregion 0: 0x7ba00000 0x100000
|
|
Subregion 1: 0x7bb00000 0x100000
|
|
Subregion 2: 0x7bc00000 0x0
|
|
MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
|
|
MTRR Range: Start=7ba00000 End=7bc00000 (Size 200000)
|
|
MTRR Range: Start=fff00000 End=0 (Size 100000)
|
|
Normal boot
|
|
CBFS: Found 'fallback/postcar' @0x776c0 size 0x4058 in mcache @0xfeffb03c
|
|
Loading module at 0x7b7d6000 with entry 0x7b7d6031. filesize: 0x3d10 memsize: 0x41b0
|
|
Processing 194 relocs. Offset value of 0x797d6000
|
|
BS: romstage times (exec / console): total (unknown) / 20 ms
|
|
|
|
|
|
coreboot-4.14-1258-gfbc46a3bfb Sat Jul 31 09:15:37 UTC 2021 postcar starting (log level: 6)...
|
|
Normal boot
|
|
FMAP: area COREBOOT found @ 10200 (982528 bytes)
|
|
CBFS: Found 'fallback/ramstage' @0x3b1c0 size 0x32860 in mcache @0x7b7dd0dc
|
|
Loading module at 0x7b794000 with entry 0x7b794000. filesize: 0x2f4d8 memsize: 0x40450
|
|
Processing 3282 relocs. Offset value of 0x7a994000
|
|
BS: postcar times (exec / console): total (unknown) / 16 ms
|
|
|
|
|
|
coreboot-4.14-1258-gfbc46a3bfb Sat Jul 31 09:15:37 UTC 2021 ramstage starting (log level: 6)...
|
|
Normal boot
|
|
Enumerating buses...
|
|
Root Device scanning...
|
|
CPU_CLUSTER: 0 enabled
|
|
DOMAIN: 0000 enabled
|
|
DOMAIN: 0000 scanning...
|
|
PCI: pci_scan_bus for bus 00
|
|
PCI: 00:00.0 [8086/2e30] enabled
|
|
PCI: 00:01.0 subordinate bus PCI Express
|
|
PCI: 00:01.0 [8086/2e31] enabled
|
|
PCI: 00:02.0 [8086/2e32] enabled
|
|
PCI: 00:02.1 [8086/2e33] enabled
|
|
PCI: 00:1b.0 [8086/27d8] enabled
|
|
PCI: 00:1c.0 [8086/27d0] enabled
|
|
PCI: 00:1c.1 [8086/27d2] enabled
|
|
PCI: 00:1c.2: Disabling device
|
|
PCI: 00:1c.2 [8086/27d4] disabled
|
|
PCI: 00:1c.3: Disabling device
|
|
PCI: 00:1c.2: Disabling device
|
|
PCI: 00:1c.2: Disabling device
|
|
PCI: 00:1c.3: Disabling device
|
|
PCI: 00:1c.3: Disabling device
|
|
PCI: 00:1c.3 [8086/27d6] disabled
|
|
PCI: 00:1d.0 [8086/27c8] enabled
|
|
PCI: 00:1d.1 [8086/27c9] enabled
|
|
PCI: 00:1d.2 [8086/27ca] enabled
|
|
PCI: 00:1d.3 [8086/27cb] enabled
|
|
PCI: 00:1d.7 [8086/27cc] enabled
|
|
PCI: 00:1e.0 [8086/244e] enabled
|
|
PCI: 00:1e.2: Disabling device
|
|
PCI: 00:1e.2: Disabling device
|
|
PCI: 00:1e.2 [8086/27de] disabled
|
|
PCI: 00:1e.3: Disabling device
|
|
PCI: 00:1e.3: Disabling device
|
|
PCI: 00:1e.3 [8086/27dd] disabled
|
|
PCI: 00:1f.0 [8086/27b8] enabled
|
|
PCI: 00:1f.1 [8086/27df] enabled
|
|
Set SATA mode early
|
|
AHCI not supported, falling back to plain mode.
|
|
Set SATA mode early
|
|
PCI: 00:1f.2 [8086/27c0] enabled
|
|
PCI: 00:1f.3 [8086/27da] enabled
|
|
PCI: Leftover static devices:
|
|
PCI: 00:03.0
|
|
PCI: 00:03.1
|
|
PCI: Check your devicetree.cb.
|
|
PCI: 00:01.0 scanning...
|
|
PCI: 00:01.0: No LTR support
|
|
PCI: pci_scan_bus for bus 01
|
|
scan_bus: bus PCI: 00:01.0 finished in 0 msecs
|
|
PCI: 00:1c.0 scanning...
|
|
PCI: pci_scan_bus for bus 02
|
|
scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
|
|
PCI: 00:1c.1 scanning...
|
|
PCI: pci_scan_bus for bus 03
|
|
PCI: 03:00.0 [1969/2062] enabled
|
|
scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
|
|
PCI: 00:1e.0 scanning...
|
|
PCI: pci_scan_bus for bus 04
|
|
PCI: 04:02.0 [10ec/8185] enabled
|
|
scan_bus: bus PCI: 00:1e.0 finished in 0 msecs
|
|
PCI: 00:1f.0 scanning...
|
|
PNP: 002e.0 disabled
|
|
PNP: 002e.1 enabled
|
|
PNP: 002e.2 enabled
|
|
PNP: 002e.3 disabled
|
|
PNP: 002e.5 enabled
|
|
PNP: 002e.6 disabled
|
|
PNP: 002e.7 disabled
|
|
PNP: 002e.8 disabled
|
|
PNP: 002e.9 enabled
|
|
PNP: 002e.109 disabled
|
|
PNP: 002e.209 enabled
|
|
PNP: 002e.309 disabled
|
|
PNP: 002e.a enabled
|
|
PNP: 002e.b enabled
|
|
PNP: 002e.c disabled
|
|
PNP: 002e.307 enabled
|
|
scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
|
|
PCI: 00:1f.3 scanning...
|
|
I2C: 01:69 enabled
|
|
bus: PCI: 00:1f.3[0]->scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
|
|
scan_bus: bus DOMAIN: 0000 finished in 8 msecs
|
|
scan_bus: bus Root Device finished in 8 msecs
|
|
done
|
|
BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 11 ms
|
|
FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)
|
|
MRC: No data in cbmem for 'RW_MRC_CACHE'.
|
|
BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 4 ms
|
|
found VGA at PCI: 00:02.0
|
|
Setting up VGA for PCI: 00:02.0
|
|
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
|
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
Allocating resources...
|
|
Reading resources...
|
|
TOUUD 0x80000000 TOLUD 0x80000000 TOM 0x80000000
|
|
IGD decoded, subtracting 64M UMA and 4M GTT
|
|
TSEG decoded, subtracting 2M
|
|
Unused RAM between cbmem_top and TOM: 0x800K
|
|
Available memory below 4GB: 1976M
|
|
Adding UMA memory area base=0x7b800000 size=0x04800000
|
|
Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000.
|
|
Done reading resources.
|
|
=== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
|
|
PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
PCI: 03:00.0 18 * [0x0 - 0x7f] io
|
|
PCI: 00:1c.1 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 03:00.0 10 * [0x0 - 0x3ffff] mem
|
|
PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
PCI: 04:02.0 10 * [0x0 - 0xff] io
|
|
PCI: 00:1e.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
PCI: 00:1e.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
PCI: 04:02.0 14 * [0x0 - 0x1ff] mem
|
|
PCI: 00:1e.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
|
|
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
update_constraints: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed)
|
|
update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
|
|
update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
|
|
update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
|
|
update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
|
|
update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
DOMAIN: 0000: Resource ranges:
|
|
* Base: 1000, Size: f000, Tag: 100
|
|
PCI: 00:1c.1 1c * [0x1000 - 0x1fff] limit: 1fff io
|
|
PCI: 00:1e.0 1c * [0x2000 - 0x2fff] limit: 2fff io
|
|
PCI: 00:1d.0 20 * [0x3000 - 0x301f] limit: 301f io
|
|
PCI: 00:1d.1 20 * [0x3020 - 0x303f] limit: 303f io
|
|
PCI: 00:1d.2 20 * [0x3040 - 0x305f] limit: 305f io
|
|
PCI: 00:1d.3 20 * [0x3060 - 0x307f] limit: 307f io
|
|
PCI: 00:1f.1 20 * [0x3080 - 0x308f] limit: 308f io
|
|
PCI: 00:1f.2 20 * [0x3090 - 0x309f] limit: 309f io
|
|
PCI: 00:02.0 20 * [0x30a0 - 0x30a7] limit: 30a7 io
|
|
PCI: 00:1f.1 10 * [0x30a8 - 0x30af] limit: 30af io
|
|
PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] limit: 30b7 io
|
|
PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] limit: 30bf io
|
|
PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] limit: 30c7 io
|
|
PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] limit: 30cb io
|
|
PCI: 00:1f.1 1c * [0x30cc - 0x30cf] limit: 30cf io
|
|
PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] limit: 30d3 io
|
|
PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] limit: 30d7 io
|
|
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
update_constraints: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed)
|
|
update_constraints: DOMAIN: 0000 04 base 000a0000 limit 000bffff mem (fixed)
|
|
update_constraints: DOMAIN: 0000 05 base 000c0000 limit 000fffff mem (fixed)
|
|
update_constraints: DOMAIN: 0000 06 base 00100000 limit 7b7fffff mem (fixed)
|
|
update_constraints: DOMAIN: 0000 07 base 7b800000 limit 7fffffff mem (fixed)
|
|
update_constraints: DOMAIN: 0000 08 base fed10000 limit ffffffff mem (fixed)
|
|
update_constraints: DOMAIN: 0000 09 base e0000000 limit efffffff mem (fixed)
|
|
update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed)
|
|
update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
DOMAIN: 0000: Resource ranges:
|
|
* Base: 80000000, Size: 60000000, Tag: 200
|
|
* Base: f0000000, Size: ec00000, Tag: 200
|
|
* Base: fec01000, Size: 10f000, Tag: 200
|
|
* Base: 100000000, Size: f00000000, Tag: 100200
|
|
PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
|
|
PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
|
|
PCI: 00:02.1 10 * [0x90400000 - 0x904fffff] limit: 904fffff mem
|
|
PCI: 00:1c.1 20 * [0x90500000 - 0x905fffff] limit: 905fffff mem
|
|
PCI: 00:1e.0 20 * [0x90600000 - 0x906fffff] limit: 906fffff mem
|
|
PCI: 00:1b.0 10 * [0x90700000 - 0x90703fff] limit: 90703fff mem
|
|
PCI: 00:1d.7 10 * [0x90704000 - 0x907043ff] limit: 907043ff mem
|
|
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff
|
|
PCI: 00:1c.1: Resource ranges:
|
|
* Base: 1000, Size: 1000, Tag: 100
|
|
PCI: 03:00.0 18 * [0x1000 - 0x107f] limit: 107f io
|
|
PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done
|
|
PCI: 00:1c.1 mem: base: 90500000 size: 100000 align: 20 gran: 20 limit: 905fffff
|
|
PCI: 00:1c.1: Resource ranges:
|
|
* Base: 90500000, Size: 100000, Tag: 200
|
|
PCI: 03:00.0 10 * [0x90500000 - 0x9053ffff] limit: 9053ffff mem
|
|
PCI: 00:1c.1 mem: base: 90500000 size: 100000 align: 20 gran: 20 limit: 905fffff done
|
|
PCI: 00:1e.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff
|
|
PCI: 00:1e.0: Resource ranges:
|
|
* Base: 2000, Size: 1000, Tag: 100
|
|
PCI: 04:02.0 10 * [0x2000 - 0x20ff] limit: 20ff io
|
|
PCI: 00:1e.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done
|
|
PCI: 00:1e.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff
|
|
PCI: 00:1e.0: Resource ranges:
|
|
* Base: 90600000, Size: 100000, Tag: 200
|
|
PCI: 04:02.0 14 * [0x90600000 - 0x906001ff] limit: 906001ff mem
|
|
PCI: 00:1e.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff done
|
|
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
|
|
DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem
|
|
DOMAIN: 0000 04 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem
|
|
DOMAIN: 0000 05 <- [0x00000c0000 - 0x00000fffff] size 0x00040000 gran 0x00 mem
|
|
DOMAIN: 0000 06 <- [0x0000100000 - 0x007b7fffff] size 0x7b700000 gran 0x00 mem
|
|
DOMAIN: 0000 07 <- [0x007b800000 - 0x007fffffff] size 0x04800000 gran 0x00 mem
|
|
DOMAIN: 0000 08 <- [0x00fed10000 - 0x00ffffffff] size 0x012f0000 gran 0x00 mem
|
|
DOMAIN: 0000 09 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x00 mem
|
|
PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
|
PCI: 00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
PCI: 00:01.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 01 mem
|
|
PCI: 00:02.0 10 <- [0x0090000000 - 0x00903fffff] size 0x00400000 gran 0x16 mem64
|
|
PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
|
|
PCI: 00:02.0 20 <- [0x00000030a0 - 0x00000030a7] size 0x00000008 gran 0x03 io
|
|
PCI: 00:02.1 10 <- [0x0090400000 - 0x00904fffff] size 0x00100000 gran 0x14 mem64
|
|
PCI: 00:1b.0 10 <- [0x0090700000 - 0x0090703fff] size 0x00004000 gran 0x0e mem64
|
|
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
|
PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
|
PCI: 00:1c.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 02 mem
|
|
PCI: 00:1c.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
|
|
PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
|
PCI: 00:1c.1 20 <- [0x0090500000 - 0x00905fffff] size 0x00100000 gran 0x14 bus 03 mem
|
|
PCI: 03:00.0 10 <- [0x0090500000 - 0x009053ffff] size 0x00040000 gran 0x12 mem64
|
|
PCI: 03:00.0 18 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io
|
|
PCI: 00:1d.0 20 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
|
|
PCI: 00:1d.1 20 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io
|
|
PCI: 00:1d.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
|
|
PCI: 00:1d.3 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
|
|
PCI: 00:1d.7 10 <- [0x0090704000 - 0x00907043ff] size 0x00000400 gran 0x0a mem
|
|
PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
|
|
PCI: 00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
|
|
PCI: 00:1e.0 20 <- [0x0090600000 - 0x00906fffff] size 0x00100000 gran 0x14 bus 04 mem
|
|
PCI: 04:02.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
|
|
PCI: 04:02.0 14 <- [0x0090600000 - 0x00906001ff] size 0x00000200 gran 0x09 mem
|
|
PNP: 002e.1 28 <- [0x0000000070 - 0x000000006f] size 0x00000000 gran 0x00 irq
|
|
PNP: 002e.1 2c <- [0x00000000d2 - 0x00000000d1] size 0x00000000 gran 0x00 irq
|
|
PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
|
|
PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq
|
|
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
|
|
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
|
|
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
|
|
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
|
|
PNP: 002e.209 f4 <- [0x00000000b3 - 0x00000000b2] size 0x00000000 gran 0x00 irq
|
|
PNP: 002e.a e4 <- [0x0000000010 - 0x000000000f] size 0x00000000 gran 0x00 irq
|
|
ERROR: PNP: 002e.a 70 irq size: 0x0000000001 not assigned in devicetree
|
|
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
|
|
PNP: 002e.b 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq
|
|
PCI: 00:1f.1 10 <- [0x00000030a8 - 0x00000030af] size 0x00000008 gran 0x03 io
|
|
PCI: 00:1f.1 14 <- [0x00000030c8 - 0x00000030cb] size 0x00000004 gran 0x02 io
|
|
PCI: 00:1f.1 18 <- [0x00000030b0 - 0x00000030b7] size 0x00000008 gran 0x03 io
|
|
PCI: 00:1f.1 1c <- [0x00000030cc - 0x00000030cf] size 0x00000004 gran 0x02 io
|
|
PCI: 00:1f.1 20 <- [0x0000003080 - 0x000000308f] size 0x00000010 gran 0x04 io
|
|
PCI: 00:1f.2 10 <- [0x00000030b8 - 0x00000030bf] size 0x00000008 gran 0x03 io
|
|
PCI: 00:1f.2 14 <- [0x00000030d0 - 0x00000030d3] size 0x00000004 gran 0x02 io
|
|
PCI: 00:1f.2 18 <- [0x00000030c0 - 0x00000030c7] size 0x00000008 gran 0x03 io
|
|
PCI: 00:1f.2 1c <- [0x00000030d4 - 0x00000030d7] size 0x00000004 gran 0x02 io
|
|
PCI: 00:1f.2 20 <- [0x0000003090 - 0x000000309f] size 0x00000010 gran 0x04 io
|
|
Done setting resources.
|
|
Done allocating resources.
|
|
BS: BS_DEV_RESOURCES run times (exec / console): 1 / 95 ms
|
|
Enabling resources...
|
|
PCI: 00:00.0 subsystem <- 1849/2e30
|
|
PCI: 00:00.0 cmd <- 06
|
|
PCI: 00:01.0 bridge ctrl <- 0013
|
|
PCI: 00:01.0 cmd <- 00
|
|
PCI: 00:02.0 subsystem <- 1849/2e32
|
|
PCI: 00:02.0 cmd <- 03
|
|
PCI: 00:02.1 cmd <- 02
|
|
PCI: 00:1b.0 subsystem <- 1849/3662
|
|
PCI: 00:1b.0 cmd <- 102
|
|
PCI: 00:1c.0 bridge ctrl <- 0013
|
|
PCI: 00:1c.0 subsystem <- 1458/5000
|
|
PCI: 00:1c.0 cmd <- 100
|
|
PCI: 00:1c.1 bridge ctrl <- 0013
|
|
PCI: 00:1c.1 subsystem <- 1458/5000
|
|
PCI: 00:1c.1 cmd <- 107
|
|
PCI: 00:1d.0 subsystem <- 1849/27c8
|
|
PCI: 00:1d.0 cmd <- 01
|
|
PCI: 00:1d.1 subsystem <- 1849/27c9
|
|
PCI: 00:1d.1 cmd <- 01
|
|
PCI: 00:1d.2 subsystem <- 1849/27ca
|
|
PCI: 00:1d.2 cmd <- 01
|
|
PCI: 00:1d.3 subsystem <- 1849/27cb
|
|
PCI: 00:1d.3 cmd <- 01
|
|
PCI: 00:1d.7 subsystem <- 1849/27cc
|
|
PCI: 00:1d.7 cmd <- 102
|
|
PCI: 00:1e.0 bridge ctrl <- 0013
|
|
PCI: 00:1e.0 subsystem <- 1458/5000
|
|
PCI: 00:1e.0 cmd <- 107
|
|
PCI: 00:1f.0 subsystem <- 1849/27b8
|
|
PCI: 00:1f.0 cmd <- 107
|
|
PCI: 00:1f.1 subsystem <- 1849/27df
|
|
PCI: 00:1f.1 cmd <- 01
|
|
PCI: 00:1f.2 subsystem <- 1849/27c0
|
|
PCI: 00:1f.2 cmd <- 01
|
|
PCI: 00:1f.3 subsystem <- 1849/27da
|
|
PCI: 00:1f.3 cmd <- 101
|
|
PCI: 03:00.0 cmd <- 03
|
|
PCI: 04:02.0 cmd <- 03
|
|
done.
|
|
BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
|
|
Initializing devices...
|
|
CPU_CLUSTER: 0 init
|
|
FMAP: area COREBOOT found @ 10200 (982528 bytes)
|
|
CBFS: Found 'cpu_microcode_blob.bin' @0xf180 size 0x2c000 in mcache @0x7b7dd0ac
|
|
microcode: sig=0x10676 pf=0x1 revision=0x60f
|
|
microcode: Update skipped, already up-to-date
|
|
MTRR: Physical address space:
|
|
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
|
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
|
0x00000000000c0000 - 0x000000007b800000 size 0x7b740000 type 6
|
|
0x000000007b800000 - 0x0000000080000000 size 0x04800000 type 0
|
|
0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
|
|
0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
|
|
MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
CPU physical address size: 36 bits
|
|
MTRR: default type WB/UC MTRR counts: 6/4.
|
|
MTRR: UC selected as default type.
|
|
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
MTRR: 1 base 0x000000007b800000 mask 0x0000000fff800000 type 0
|
|
MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
|
|
MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
|
|
|
|
MTRR check
|
|
Fixed MTRRs : Enabled
|
|
Variable MTRRs: Enabled
|
|
|
|
CPU has 2 cores.
|
|
Setting up SMI for CPU
|
|
Will perform SMM setup.
|
|
CPU: Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz.
|
|
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
|
|
Processing 16 relocs. Offset value of 0x00030000
|
|
Attempting to start 1 APs
|
|
Starting CPUs in xapic mode
|
|
Waiting for 10ms after sending INIT.
|
|
Waiting for 1st SIPI to complete...done.
|
|
Waiting for 2nd SIPI to complete...done.
|
|
AP: slot 1 apic_id 1, MCU rev: 0x0000060f
|
|
smm_stub_place_stacks: cpus: 2 : stack space: needed -> 800
|
|
smm_stub_place_stacks: exit, stack_top 0x7ba00800
|
|
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
|
|
Processing 11 relocs. Offset value of 0x00038000
|
|
smm_module_setup_stub: stack_end = 0x7ba00000
|
|
smm_module_setup_stub: stack_top = 0x7ba00800
|
|
smm_module_setup_stub: stack_size = 0x400
|
|
smm_module_setup_stub: runtime.start32_offset = 0x4c
|
|
smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
SMM Module: stub loaded at 0x00038000. Will call 0x7b7abea9
|
|
Installing permanent SMM handler to 0x7ba00000
|
|
smm_load_module: total_smm_space_needed 5280, available -> 100000
|
|
Loading module at 0x7bafc000 with entry 0x7bafc071. filesize: 0x670 memsize: 0x4680
|
|
Processing 28 relocs. Offset value of 0x7bafc000
|
|
smm_load_module: smram_start: 0x0x7ba00000
|
|
smm_load_module: smram_end: 0x7bb00000
|
|
smm_load_module: stack_top: 0x7ba00800
|
|
smm_load_module: handler start 0x7bafc071
|
|
smm_load_module: handler_size 5100
|
|
smm_load_module: fxsave_area 0x7baffc00
|
|
smm_load_module: fxsave_size 400
|
|
smm_load_module: CONFIG_MSEG_SIZE 0x0
|
|
smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
|
|
smm_load_module: handler_mod_params.smbase = 0x7ba00000
|
|
smm_load_module: per_cpu_save_state_size = 0x400
|
|
smm_load_module: num_cpus = 0x2
|
|
smm_load_module: total_save_state_size = 0x800
|
|
smm_load_module: cpu0 entry: 0x7baec000
|
|
smm_create_map: cpus allowed in one segment 30
|
|
smm_create_map: min # of segments needed 1
|
|
smm_stub_place_stacks: cpus: 2 : stack space: needed -> 800
|
|
smm_stub_place_stacks: exit, stack_top 0x7ba00800
|
|
Loading module at 0x7baf4000 with entry 0x7baf4000. filesize: 0x1e0 memsize: 0x1e0
|
|
Processing 11 relocs. Offset value of 0x7baf4000
|
|
smm_place_entry_code: smbase 7baebc00, stack_top 7ba00800
|
|
SMM Module: placing smm entry code at 7baf3c00, cpu # 0x1
|
|
smm_place_entry_code: copying from 7baf4000 to 7baf3c00 0x1e0 bytes
|
|
smm_module_setup_stub: stack_end = 0x7ba00000
|
|
smm_module_setup_stub: stack_top = 0x7ba00800
|
|
smm_module_setup_stub: stack_size = 0x400
|
|
smm_module_setup_stub: runtime.start32_offset = 0x4c
|
|
smm_module_setup_stub: runtime.smm_size = 0x100000
|
|
SMM Module: stub loaded at 0x7baf4000. Will call 0x7bafc071
|
|
Initializing southbridge SMI...
|
|
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7baec000, cpu = 0
|
|
In relocation handler: cpu 0
|
|
New SMBASE=0x7baec000
|
|
SMRR not enabled, skip writing SMRR...
|
|
Relocation complete.
|
|
VMX status: enabled
|
|
VMX status: enabled
|
|
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7baebc00, cpu = 1
|
|
In relocation handler: cpu 1
|
|
New SMBASE=0x7baebc00
|
|
Writing SMRR. base = 0x7ba00000, mask=0xffe00800
|
|
Relocation complete.
|
|
Initializing CPU #0
|
|
CPU: vendor Intel device 10676
|
|
CPU: family 06, model 17, stepping 06
|
|
CPU: Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz.
|
|
Setting up local APIC...
|
|
apic_id: 0x0 done.
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 0: 0, 1, 9, 0x20, 35000; encoded: 0x4920
|
|
CPU #0 initialized
|
|
Initializing CPU #1
|
|
CPU: vendor Intel device 10676
|
|
CPU: family 06, model 17, stepping 06
|
|
CPU: Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz.
|
|
Setting up local APIC...
|
|
apic_id: 0x1 done.
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 1: 0, 0, 6, 0x19, 15000; encoded: 0x0619
|
|
writing P-State 0: 0, 1, 9, 0x20, 35000; encoded: 0x4920
|
|
CPU #1 initialized
|
|
CPU 1 going down...
|
|
bsp_do_flight_plan done after 60 msecs.
|
|
Initializing southbridge SMI...
|
|
SMI_STS:
|
|
GPE0_STS: GPIO12 GPIO11 GPIO1
|
|
ALT_GP_SMI_STS: GPI14 GPI12 GPI11 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
TCO_STS:
|
|
Locking SMM.
|
|
CPU_CLUSTER: 0 init finished in 100 msecs
|
|
DOMAIN: 0000 init
|
|
DOMAIN: 0000 init finished in 0 msecs
|
|
PCI: 00:00.0 init
|
|
PCI: 00:00.0 init finished in 0 msecs
|
|
PCI: 00:02.0 init
|
|
CBFS: Found 'vbt.bin' @0x76f00 size 0x365 in mcache @0x7b7dd1e4
|
|
Found a VBT of 1899 bytes after decompression
|
|
GMA: Found VBT in CBFS
|
|
GMA: Found valid VBT in CBFS
|
|
PCI: 00:02.0 init finished in 28 msecs
|
|
PCI: 00:02.1 init
|
|
PCI: 00:02.1 init finished in 0 msecs
|
|
PCI: 00:1b.0 init
|
|
Azalia: codec type: Azalia
|
|
Azalia: base = 90700000
|
|
Azalia: codec_mask = 01
|
|
Azalia: Initializing codec #0
|
|
Azalia: codec viddid: 11064397
|
|
Azalia: No verb!
|
|
PCI: 00:1b.0 init finished in 3 msecs
|
|
PCI: 00:1c.0 init
|
|
Initializing ICH7 PCIe bridge.
|
|
PCI: 00:1c.0 init finished in 0 msecs
|
|
PCI: 00:1c.1 init
|
|
Initializing ICH7 PCIe bridge.
|
|
PCI: 00:1c.1 init finished in 0 msecs
|
|
PCI: 00:1d.0 init
|
|
UHCI: Setting up controller.. done.
|
|
PCI: 00:1d.0 init finished in 0 msecs
|
|
PCI: 00:1d.1 init
|
|
UHCI: Setting up controller.. done.
|
|
PCI: 00:1d.1 init finished in 0 msecs
|
|
PCI: 00:1d.2 init
|
|
UHCI: Setting up controller.. done.
|
|
PCI: 00:1d.2 init finished in 0 msecs
|
|
PCI: 00:1d.3 init
|
|
UHCI: Setting up controller.. done.
|
|
PCI: 00:1d.3 init finished in 0 msecs
|
|
PCI: 00:1d.7 init
|
|
EHCI: Setting up controller.. done.
|
|
PCI: 00:1d.7 init finished in 0 msecs
|
|
PCI: 00:1e.0 init
|
|
PCI: 00:1e.0 init finished in 0 msecs
|
|
PCI: 00:1f.0 init
|
|
i82801gx: lpc_init
|
|
IOAPIC: Initializing IOAPIC at 0xfec00000
|
|
IOAPIC: ID = 0x02
|
|
Set power on after power failure.
|
|
NMI sources disabled.
|
|
rtc_failed = 0x0
|
|
RTC Init
|
|
apm_control: Disabling ACPI.
|
|
APMC done.
|
|
PCI: 00:1f.0 init finished in 5 msecs
|
|
PCI: 00:1f.1 init
|
|
i82801gx_ide: initializing... IDE0
|
|
PCI: 00:1f.1 init finished in 0 msecs
|
|
PCI: 00:1f.2 init
|
|
i82801gx_sata: initializing...
|
|
SATA controller in plain mode.
|
|
PCI: 00:1f.2 init finished in 0 msecs
|
|
PCI: 03:00.0 init
|
|
PCI: 03:00.0 init finished in 0 msecs
|
|
PCI: 04:02.0 init
|
|
PCI: 04:02.0 init finished in 0 msecs
|
|
PNP: 002e.1 init
|
|
PNP: 002e.1 init finished in 0 msecs
|
|
PNP: 002e.2 init
|
|
PNP: 002e.2 init finished in 0 msecs
|
|
PNP: 002e.5 init
|
|
PNP: 002e.5 init finished in 0 msecs
|
|
PNP: 002e.9 init
|
|
PNP: 002e.9 init finished in 0 msecs
|
|
PNP: 002e.209 init
|
|
PNP: 002e.209 init finished in 0 msecs
|
|
PNP: 002e.a init
|
|
PNP: 002e.a init finished in 0 msecs
|
|
PNP: 002e.b init
|
|
PNP: 002e.b init finished in 0 msecs
|
|
PNP: 002e.307 init
|
|
PNP: 002e.307 init finished in 0 msecs
|
|
smbus: PCI: 00:1f.3[0]->I2C: 01:69 init
|
|
Changing 28 of the 28 ck505 config bytes.
|
|
I2C: 01:69 init finished in 55 msecs
|
|
Devices initialized
|
|
BS: BS_DEV_INIT run times (exec / console): 122 / 75 ms
|
|
Finalize devices...
|
|
PCI: 00:1f.0 final
|
|
Manufacturer: ef
|
|
SF: Detected ef 4014 with sector size 0x1000, total 0x100000
|
|
Devices finalized
|
|
BS: BS_POST_DEVICE run times (exec / console): 0 / 11 ms
|
|
CBFS: Found 'fallback/dsdt.aml' @0x750c0 size 0x1e02 in mcache @0x7b7dd1b8
|
|
CBFS: 'fallback/slic' not found.
|
|
ACPI: Writing ACPI tables at 7b755000.
|
|
ACPI: * FACS
|
|
ACPI: * DSDT
|
|
ACPI: * FADT
|
|
ACPI: added table 1/32, length now 40
|
|
ACPI: * SSDT
|
|
Found 1 CPU(s) with 2 core(s) each.
|
|
clocks between 2000 and 3166 MHz.
|
|
adding 2 P-States between busratio 6 and 9, incl. P0
|
|
PSS: 3166MHz power 35000 control 0x4920 status 0x4920
|
|
PSS: 2000MHz power 15000 control 0x619 status 0x619
|
|
clocks between 2000 and 3166 MHz.
|
|
adding 2 P-States between busratio 6 and 9, incl. P0
|
|
PSS: 3166MHz power 35000 control 0x4920 status 0x4920
|
|
PSS: 2000MHz power 15000 control 0x619 status 0x619
|
|
Generating ACPI PIRQ entries
|
|
CBFS: 'pci8086,2e33.rom' not found.
|
|
PCI Option ROM loading disabled for PCI: 00:02.1
|
|
PCI: 00:02.1: Missing PCI Option ROM
|
|
ACPI: added table 2/32, length now 44
|
|
ACPI: * MCFG
|
|
ACPI: added table 3/32, length now 48
|
|
ACPI: * MADT
|
|
ACPI: added table 4/32, length now 52
|
|
current = 7b757740
|
|
current = 7b757740
|
|
ACPI: * HPET
|
|
ACPI: added table 5/32, length now 56
|
|
ACPI: done.
|
|
ACPI tables: 10112 bytes.
|
|
smbios_write_tables: 7b754000
|
|
SMBIOS firmware version is set to coreboot_version: '4.14-1258-gfbc46a3bfb'
|
|
SMBIOS tables: 553 bytes.
|
|
Writing table forward entry at 0x00000500
|
|
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum f466
|
|
Writing coreboot table at 0x7b779000
|
|
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
1. 0000000000001000-000000000009ffff: RAM
|
|
2. 00000000000a0000-00000000000fffff: RESERVED
|
|
3. 0000000000100000-000000007b753fff: RAM
|
|
4. 000000007b754000-000000007b793fff: CONFIGURATION TABLES
|
|
5. 000000007b794000-000000007b7d4fff: RAMSTAGE
|
|
6. 000000007b7d5000-000000007b7fffff: CONFIGURATION TABLES
|
|
7. 000000007b800000-000000007fffffff: RESERVED
|
|
8. 00000000e0000000-00000000efffffff: RESERVED
|
|
9. 00000000fed10000-00000000ffffffff: RESERVED
|
|
Wrote coreboot table at: 0x7b779000, 0x37c bytes, checksum cc01
|
|
coreboot table: 916 bytes.
|
|
IMD ROOT 0. 0x7b7ff000 0x00001000
|
|
IMD SMALL 1. 0x7b7fe000 0x00001000
|
|
CONSOLE 2. 0x7b7de000 0x00020000
|
|
RO MCACHE 3. 0x7b7dd000 0x00000344
|
|
TIME STAMP 4. 0x7b7dc000 0x00000910
|
|
ROMSTG STCK 5. 0x7b7db000 0x00001000
|
|
AFTER CAR 6. 0x7b7d5000 0x00006000
|
|
RAMSTAGE 7. 0x7b793000 0x00042000
|
|
SMM BACKUP 8. 0x7b783000 0x00010000
|
|
4f444749 9. 0x7b781000 0x00002000
|
|
COREBOOT 10. 0x7b779000 0x00008000
|
|
ACPI 11. 0x7b755000 0x00024000
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SMBIOS 12. 0x7b754000 0x00000800
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IMD small region:
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IMD ROOT 0. 0x7b7fec00 0x00000400
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FMAP 1. 0x7b7feb20 0x000000e0
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ROMSTAGE 2. 0x7b7feb00 0x00000004
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ACPI GNVS 3. 0x7b7fea00 0x00000100
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BS: BS_WRITE_TABLES run times (exec / console): 4 / 22 ms
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CBFS: Found 'fallback/payload' @0x7b780 size 0x1112d in mcache @0x7b7dd280
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Checking segment from ROM address 0xfff8b9ac
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Payload being loaded at below 1MiB without region being marked as RAM usable.
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Checking segment from ROM address 0xfff8b9c8
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Loading segment from ROM address 0xfff8b9ac
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code (compression=1)
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New segment dstaddr 0x000df980 memsize 0x20680 srcaddr 0xfff8b9e4 filesize 0x110f5
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Loading Segment: addr: 0x000df980 memsz: 0x0000000000020680 filesz: 0x00000000000110f5
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using LZMA
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Loading segment from ROM address 0xfff8b9c8
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Entry Point 0x000fd26a
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BS: BS_PAYLOAD_LOAD run times (exec / console): 38 / 7 ms
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ICH-NM10-PCH: watchdog disabled
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Jumping to boot code at 0x000fd26a(0x7b779000)
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SeaBIOS (version rel-1.14.0-0-g155821a)
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BUILD: gcc: (coreboot toolchain v2021-05-22_b2b5781bb4) 8.3.0 binutils: (GNU Binutils) 2.35.1
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Found coreboot cbmem console @ 7b7de000
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Found mainboard ASROCK G41M-VS3 R2.0
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Relocating init from 0x000e10a0 to 0x7b706c20 (size 54080)
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Found CBFS header at 0xfff1022c
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multiboot: eax=7b7c2d9c, ebx=7b7c2d64
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Found 19 PCI devices (max PCI bus is 04)
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Copying SMBIOS entry point from 0x7b754000 to 0x000f6280
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Copying ACPI RSDP from 0x7b755000 to 0x000f6250
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table(50434146)=0x7b7570a0 (via xsdt)
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Using pmtimer, ioport 0x508
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|
Scan for VGA option rom
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Running option rom at c000:0003
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pmm call arg1=0
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Turning on vga text mode console
|
|
SeaBIOS (version rel-1.14.0-0-g155821a)
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EHCI init on dev 00:1d.7 (regs=0x90704020)
|
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UHCI init on dev 00:1d.0 (io=3000)
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UHCI init on dev 00:1d.1 (io=3020)
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UHCI init on dev 00:1d.2 (io=3040)
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UHCI init on dev 00:1d.3 (io=3060)
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ATA controller 1 at 1f0/3f4/0 (irq 14 dev f9)
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ATA controller 2 at 170/374/0 (irq 15 dev f9)
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ATA controller 3 at 30b8/30d0/0 (irq 0 dev fa)
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ATA controller 4 at 30c0/30d4/0 (irq 0 dev fa)
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Searching bootorder for: HALT
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|
Found 1 lpt ports
|
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Found 1 serial ports
|
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PS2 keyboard initialized
|
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ata3-0: ST3250318AS ATA-8 Hard-Disk (232 GiBytes)
|
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Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0
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Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@1/disk@0
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|
ata2-0: WDC WD2500AAJS-75M0A0 ATA-8 Hard-Disk (232 GiBytes)
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Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
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Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
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All threads complete.
|
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Scan for option roms
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|
|
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Press ESC for boot menu.
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|
|
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Searching bootorder for: HALT
|
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drive 0x000f6170: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=488281250
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drive 0x000f61a0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=488397168
|
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Space available for UMB: c7000-ed800, f5aa0-f6170
|
|
Returned 262144 bytes of ZoneHigh
|
|
e820 map has 7 items:
|
|
0: 0000000000000000 - 000000000009fc00 = 1 RAM
|
|
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
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|
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
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|
3: 0000000000100000 - 000000007b754000 = 1 RAM
|
|
4: 000000007b754000 - 0000000080000000 = 2 RESERVED
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|
5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
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|
6: 00000000fed10000 - 0000000100000000 = 2 RESERVED
|
|
enter handle_19:
|
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NULL
|
|
Booting from Hard Disk...
|
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Booting from 0000:7c00
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