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Bug #151 » coreboot-4.6-2480-g6cfa8e2.cap

Log of commit 4.6-2479-g8e4384d (current master) with 4.5-1097-g610d1c6 reverted - Patrick McDermott, 12/31/2017 05:39 AM

 


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de40 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x3806684c
FIDVID on BSP, APIC_id: 00
BSP fid = 0
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 0 as APIC ID for node 0, core 0
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
Wait for AP stage 1: ap_apicid = 1
readback = 1000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 2
readback = 2000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 3
readback = 3000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 4
readback = 4000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 5
readback = 5000014
common_fid(packed) = 0
common_fid = 0
End FIDVIDMSR 0xc0010071 0x5aca009e 0x3806684c
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
...WARM RESET...


soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de40 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
...WARM RESET...


soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de40 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01stopped
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02stopped
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03stopped
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04stopped
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05stopped

fill_mem_ctrl() detected 1 nodes
raminit_amdmct()
raminit_amdmct begin:
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_preInitDCT
DIMMPresence: DIMMValid=4
DIMMPresence: DIMMPresent=4
DIMMPresence: RegDIMMPresent=4
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=4
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=4
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=4
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done

DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
mctAutoInitMCT_D: DIMMSetVoltage
Node 00 DIMM voltage set to index 01
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 5
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000020
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c20
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3ffffff BottomIO: c00000
Node: 00 base: 03 limit: 43fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0042
Lane 00 nibble 0 adjusted value (pre nibble): 0042
Lane 00 nibble 0 adjusted value (post nibble): 0042
Lane 01 nibble 0 raw readback: 003f
Lane 01 nibble 0 adjusted value (pre nibble): 003f
Lane 01 nibble 0 adjusted value (post nibble): 003f
Lane 02 nibble 0 raw readback: 003c
Lane 02 nibble 0 adjusted value (pre nibble): 003c
Lane 02 nibble 0 adjusted value (post nibble): 003c
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0041
Lane 06 nibble 0 adjusted value (pre nibble): 0041
Lane 06 nibble 0 adjusted value (post nibble): 0041
Lane 07 nibble 0 raw readback: 0044
Lane 07 nibble 0 adjusted value (pre nibble): 0044
Lane 07 nibble 0 adjusted value (post nibble): 0044
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c20)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0048
Lane 00 nibble 0 adjusted value (pre nibble): 0048
Lane 00 nibble 0 adjusted value (post nibble): 0048
Lane 01 nibble 0 raw readback: 0046
Lane 01 nibble 0 adjusted value (pre nibble): 0046
Lane 01 nibble 0 adjusted value (post nibble): 0046
Lane 02 nibble 0 raw readback: 0041
Lane 02 nibble 0 adjusted value (pre nibble): 0041
Lane 02 nibble 0 adjusted value (post nibble): 0041
Lane 03 nibble 0 raw readback: 003c
Lane 03 nibble 0 adjusted value (pre nibble): 003c
Lane 03 nibble 0 adjusted value (post nibble): 003c
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 0040
Lane 05 nibble 0 adjusted value (pre nibble): 0040
Lane 05 nibble 0 adjusted value (post nibble): 0040
Lane 06 nibble 0 raw readback: 0047
Lane 06 nibble 0 adjusted value (pre nibble): 0047
Lane 06 nibble 0 adjusted value (post nibble): 0047
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0035
Lane 08 nibble 0 adjusted value (pre nibble): 0035
Lane 08 nibble 0 adjusted value (post nibble): 0035
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c20)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0055
Lane 00 new seed: 0055
Lane 01 scaled delay: 0052
Lane 01 new seed: 0052
Lane 02 scaled delay: 004b
Lane 02 new seed: 004b
Lane 03 scaled delay: 0045
Lane 03 new seed: 0045
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 004a
Lane 05 new seed: 004a
Lane 06 scaled delay: 0053
Lane 06 new seed: 0053
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003b
Lane 08 new seed: 003b
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0052
Lane 01 nibble 0 adjusted value (pre nibble): 0052
Lane 01 nibble 0 adjusted value (post nibble): 0052
Lane 02 nibble 0 raw readback: 004c
Lane 02 nibble 0 adjusted value (pre nibble): 004c
Lane 02 nibble 0 adjusted value (post nibble): 004c
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0041
Lane 04 nibble 0 adjusted value (pre nibble): 0041
Lane 04 nibble 0 adjusted value (post nibble): 0041
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0053
Lane 06 nibble 0 adjusted value (pre nibble): 0053
Lane 06 nibble 0 adjusted value (post nibble): 0053
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003c
Lane 08 nibble 0 adjusted value (pre nibble): 003c
Lane 08 nibble 0 adjusted value (post nibble): 003c
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c20)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005e
Lane 01 new seed: 005e
Lane 02 scaled delay: 0057
Lane 02 new seed: 0057
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 0049
Lane 04 new seed: 0049
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 005f
Lane 06 new seed: 005f
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0043
Lane 08 new seed: 0043
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005d
Lane 01 nibble 0 adjusted value (pre nibble): 005d
Lane 01 nibble 0 adjusted value (post nibble): 005d
Lane 02 nibble 0 raw readback: 0056
Lane 02 nibble 0 adjusted value (pre nibble): 0056
Lane 02 nibble 0 adjusted value (post nibble): 0056
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0053
Lane 05 nibble 0 adjusted value (pre nibble): 0053
Lane 05 nibble 0 adjusted value (post nibble): 0053
Lane 06 nibble 0 raw readback: 005f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0040
Lane 08 nibble 0 adjusted value (pre nibble): 0040
Lane 08 nibble 0 adjusted value (post nibble): 0040
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 4000
TrainDQSReceiverEnCyc: ErrStatus 4000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

TrainMaxRdLatency: Status 2205
TrainMaxRdLatency: ErrStatus 4000
TrainMaxRdLatency: ErrCode 0
TrainMaxRdLatency: Done

mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 2205
InterleaveNodes_D: ErrStatus 4000
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done

InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 2205
InterleaveChannels_D: ErrStatus 4000
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done

mctAutoInitMCT_D: ECCInit_D
ECC enabled on node: 00
DCTMemClr_Sync_D: Start
DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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.
DCTMemClr_Sync_D: Done
ECCInit: Node 00
ECCInit: Status 2205
ECCInit: ErrStatus 4000
ECCInit: ErrCode 0
ECCInit: Done
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:c00000
CPUMemTyping: Bottom32bIO:c00000
CPUMemTyping: Bottom40bIO:4400000
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
mctAutoInitMCT_D Done: Global Status: 12
raminit_amdmct end:
CBMEM:
IMD: root @ bffff000 254 entries.
IMD: root @ bfffec00 62 entries.
amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
disable_spd()
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 3ff00 size 15c5d


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 ramstage starting...
Moving GDT to bfffe9e0...ok
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:00.2: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:2f: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.106: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 0
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.108: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 0
PNP: 002e.f: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:05.0: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:19.1: enabled 1
PCI: 00:19.2: enabled 1
PCI: 00:19.3: enabled 1
PCI: 00:19.4: enabled 1
PCI: 00:19.5: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:00.2: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:2f: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.106: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 0
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.108: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 0
PNP: 002e.f: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:05.0: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:19.1: enabled 1
PCI: 00:19.2: enabled 1
PCI: 00:19.3: enabled 1
PCI: 00:19.4: enabled 1
PCI: 00:19.5: enabled 1
Mainboard KCMA-D8 initializing, dev=0x0012e4e0
mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000004
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000004
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
PCI: 00:18.5 siblings=5
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
CPU: APIC: 03 enabled
CPU: APIC: 04 enabled
CPU: APIC: 05 enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 15135 usecs
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1600] bus ops
PCI: 00:18.0 [1022/1600] enabled
PCI: 00:18.1 [1022/1601] enabled
PCI: 00:18.2 [1022/1602] enabled
PCI: 00:18.3 [1022/1603] ops
PCI: 00:18.3 [1022/1603] enabled
PCI: 00:18.4 [1022/1604] ops
PCI: 00:18.4 [1022/1604] enabled
PCI: 00:18.5 [1022/1605] ops
PCI: 00:18.5 [1022/1605] enabled
PCI: Static device PCI: 00:19.0 not found, disabling it.
PCI: Static device PCI: 00:19.1 not found, disabling it.
PCI: Static device PCI: 00:19.2 not found, disabling it.
PCI: Static device PCI: 00:19.3 not found, disabling it.
PCI: Static device PCI: 00:19.4 not found, disabling it.
PCI: Static device PCI: 00:19.5 not found, disabling it.
PCI: 00:18.0 scanning...
do_hypertransport_scan_chain for bus 00
sr5650_enable: dev=00130cc0, VID_DID=0x5a121002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x00130720, port=0x8
PciePowerOffGppPorts() port 8
NB_PCI_REG04 = 2.
NB_PCI_REG84 = 3000010.
NB_PCI_REG4C = 52042.
Sysmem TOM = 0_c0000000
Sysmem TOM2 = 4_40000000
PCI: 00:00.0 [1002/5a12] ops
PCI: 00:00.0 [1002/5a12] enabled
Capability: type 0x08 @ 0xf0
flags: 0xa803
Capability: type 0x08 @ 0xf0
Capability: type 0x08 @ 0xc4
flags: 0x0280
PCI: 00:00.0 count: 0014 static_count: 0015
PCI: 00:00.0 [1002/5a12] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
sr5650_enable: dev=00130cc0, VID_DID=0x5a121002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x00130720, port=0x8
PciePowerOffGppPorts() port 8
NB_PCI_REG04 = 2.
NB_PCI_REG84 = 3000010.
NB_PCI_REG4C = 52042.
Sysmem TOM = 0_c0000000
Sysmem TOM2 = 4_40000000
PCI: 00:00.0 [1002/5a12] enabled
sr5650_enable: dev=00130c20, VID_DID=0xffffffff
Bus-0, Dev-0, Fun-1.
PCI: Static device PCI: 00:00.1 not found, disabling it.
sr5650_enable: dev=00130b80, VID_DID=0x5a231002
Bus-0, Dev-0, Fun-2.
PCI: 00:00.2 [1002/5a23] ops
PCI: 00:00.2 [1002/5a23] enabled
sr5650_enable: dev=00130ae0, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x00130ae0, port=0x2
PcieLinkTraining port=2:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=10
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:02.0 subordinate bus PCI Express
PCI: 00:02.0 [1002/5a16] enabled
sr5650_enable: dev=00130a40, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
sr5650_enable: dev=001309a0, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x001309a0, port=0x4
PcieLinkTraining port=4:lc current state=2030400
sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
PciePowerOffGppPorts() port 4
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1002/5a18] enabled
sr5650_enable: dev=00130900, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
sr5650_enable: dev=00130860, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
sr5650_enable: dev=001307c0, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
sr5650_enable: dev=00130720, VID_DID=0xffffffff
Bus-0, Dev-8, Fun-0. enable=0
disable_pcie_bar3
sr5650_enable: dev=00130680, VID_DID=0xffffffff
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x00130680, port=0x9
PcieLinkTraining port=5:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=48
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1002/5a1c] enabled
sr5650_enable: dev=001305e0, VID_DID=0xffffffff
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x001305e0, port=0xa
PcieLinkTraining port=6:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1002/5a1d] enabled
sr5650_enable: dev=00130540, VID_DID=0xffffffff
Bus-0, Dev-11,12, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130cc0, dev=0x00130540, port=0xb
PcieLinkTraining port=b:lc current state=2030400
sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0
PciePowerOffGppPorts() port 11
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0b.0 subordinate bus PCI Express
PCI: 00:0b.0 [1002/5a1f] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:02.0 scanning...
do_pci_scan_bridge for PCI: 00:02.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [10de/1187] enabled
PCI: 01:00.1 [10de/0e0a] enabled
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
ASPM: Enabled L0s
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
ASPM: Enabled L0s
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Failed to enable LTR for dev = PCI: 01:00.0
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Failed to enable LTR for dev = PCI: 01:00.1
scan_bus: scanning of bus PCI: 00:02.0 took 65853 usecs
PCI: 00:04.0 scanning...
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:04.0 took 7264 usecs
PCI: 00:09.0 scanning...
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [8086/10d3] enabled
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Failed to enable LTR for dev = PCI: 03:00.0
scan_bus: scanning of bus PCI: 00:09.0 took 39870 usecs
PCI: 00:0a.0 scanning...
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [8086/10d3] enabled
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Failed to enable LTR for dev = PCI: 04:00.0
scan_bus: scanning of bus PCI: 00:0a.0 took 39870 usecs
PCI: 00:0b.0 scanning...
do_pci_scan_bridge for PCI: 00:0b.0
PCI: pci_scan_bus for bus 05
scan_bus: scanning of bus PCI: 00:0b.0 took 7264 usecs
PCI: 00:14.0 scanning...
scan_generic_bus for PCI: 00:14.0
bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
bus: PCI: 00:14.0[0]->I2C: 01:54 enabled
bus: PCI: 00:14.0[0]->I2C: 01:55 enabled
bus: PCI: 00:14.0[0]->I2C: 01:56 enabled
bus: PCI: 00:14.0[0]->I2C: 01:57 enabled
bus: PCI: 00:14.0[0]->I2C: 01:2f enabled
scan_generic_bus for PCI: 00:14.0 done
scan_bus: scanning of bus PCI: 00:14.0 took 37351 usecs
PCI: 00:14.3 scanning...
scan_lpc_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.106 disabled
PNP: 002e.107 disabled
PNP: 002e.207 disabled
PNP: 002e.307 disabled
PNP: 002e.407 disabled
PNP: 002e.8 disabled
PNP: 002e.108 disabled
PNP: 002e.9 disabled
PNP: 002e.109 disabled
PNP: 002e.209 disabled
PNP: 002e.309 disabled
PNP: 002e.a enabled
PNP: 002e.b enabled
PNP: 002e.c disabled
PNP: 002e.d disabled
PNP: 002e.f disabled
scan_lpc_bus for PCI: 00:14.3 done
scan_bus: scanning of bus PCI: 00:14.3 took 44530 usecs
PCI: 00:14.4 scanning...
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 06
sb7xx_51xx_enable()
PCI: Static device PCI: 06:01.0 not found, disabling it.
sb7xx_51xx_enable()
PCI: Static device PCI: 06:02.0 not found, disabling it.
sb7xx_51xx_enable()
PCI: Static device PCI: 06:03.0 not found, disabling it.
sb7xx_51xx_enable()
PCI: 06:05.0 [1a03/2000] ops
PCI: 06:05.0 [1a03/2000] enabled
scan_bus: scanning of bus PCI: 00:14.4 took 32318 usecs
scan_bus: scanning of bus PCI: 00:18.0 took 1068696 usecs
DOMAIN: 0000 passpw: enabled
scan_bus: scanning of bus DOMAIN: 0000 took 1132488 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 1178910 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 1516765 exit 0
found VGA at PCI: 06:05.0
found VGA at PCI: 01:00.0
Setting up VGA for PCI: 06:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 2
sr5690_read_resource: PCI: 00:00.0
PCI: 00:02.0 read_resources bus 1 link: 0
PCI: 00:02.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 2 link: 0
PCI: 00:04.0 read_resources bus 2 link: 0 done
PCI: 00:09.0 read_resources bus 3 link: 0
PCI: 00:09.0 read_resources bus 3 link: 0 done
PCI: 00:0a.0 read_resources bus 4 link: 0
PCI: 00:0a.0 read_resources bus 4 link: 0 done
PCI: 00:0b.0 read_resources bus 5 link: 0
PCI: 00:0b.0 read_resources bus 5 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
I2C: 01:54 missing read_resources
I2C: 01:55 missing read_resources
I2C: 01:56 missing read_resources
I2C: 01:57 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 6 link: 0
PCI: 00:14.4 read_resources bus 6 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
PCI: 00:18.4 read_resources bus 0 link: 0
PCI: 00:18.4 read_resources bus 0 link: 0 done
PCI: 00:18.4 read_resources bus 0 link: 1
PCI: 00:18.4 read_resources bus 0 link: 1 done
PCI: 00:18.4 read_resources bus 0 link: 2
PCI: 00:18.4 read_resources bus 0 link: 2 done
PCI: 00:18.4 read_resources bus 0 link: 3
PCI: 00:18.4 read_resources bus 0 link: 3 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
APIC: 02
APIC: 03
APIC: 04
APIC: 05
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 210b0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 210b8
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 210d8
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
PCI: 00:00.1
PCI: 00:00.2
PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
PCI: 00:02.0 child on link 0 PCI: 01:00.0
PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
PCI: 01:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffffffffffff flags 1201 index 14
PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c
PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
PCI: 01:00.1
PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0 child on link 0 PCI: 03:00.0
PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:0b.0
PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:2f
PCI: 00:14.1
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 002e.106
PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
PNP: 002e.107
PNP: 002e.207
PNP: 002e.307
PNP: 002e.407
PNP: 002e.8
PNP: 002e.108
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.d
PNP: 002e.f
PCI: 00:14.4 child on link 0 PCI: 06:01.0
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 06:01.0
PCI: 06:02.0
PCI: 06:03.0
PCI: 06:05.0
PCI: 06:05.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
PCI: 06:05.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
PCI: 06:05.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:19.0
PCI: 00:19.1
PCI: 00:19.2
PCI: 00:19.3
PCI: 00:19.4
PCI: 00:19.5
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 01:00.0 24 * [0x0 - 0x7f] io
PCI: 00:02.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 18 * [0x0 - 0x1f] io
PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 04:00.0 18 * [0x0 - 0x1f] io
PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 06:05.0 18 * [0x0 - 0x7f] io
PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:02.0 1c * [0x0 - 0xfff] io
PCI: 00:09.0 1c * [0x1000 - 0x1fff] io
PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
PCI: 00:14.4 1c * [0x3000 - 0x3fff] io
PCI: 00:11.0 20 * [0x4000 - 0x400f] io
PCI: 00:14.1 20 * [0x4010 - 0x401f] io
PCI: 00:11.0 10 * [0x4020 - 0x4027] io
PCI: 00:11.0 18 * [0x4028 - 0x402f] io
PCI: 00:14.1 10 * [0x4030 - 0x4037] io
PCI: 00:14.1 18 * [0x4038 - 0x403f] io
PCI: 00:11.0 14 * [0x4040 - 0x4043] io
PCI: 00:11.0 1c * [0x4044 - 0x4047] io
PCI: 00:14.1 14 * [0x4048 - 0x404b] io
PCI: 00:14.1 1c * [0x404c - 0x404f] io
PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 210d8 * [0x0 - 0x4fff] io
DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 01:00.0 14 * [0x0 - 0x7ffffff] prefmem
PCI: 01:00.0 1c * [0x8000000 - 0x9ffffff] prefmem
PCI: 00:02.0 prefmem: base: a000000 size: a000000 align: 27 gran: 20 limit: ffffffffffffffff done
PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 24 * [0x0 - 0x9ffffff] prefmem
PCI: 00:00.0 fc * [0xa000000 - 0xa0000ff] prefmem
PCI: 00:18.0 prefmem: base: a000100 size: a100000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0xffffff] mem
PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem
PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem
PCI: 00:02.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 06:05.0 10 * [0x0 - 0x7fffff] mem
PCI: 06:05.0 14 * [0x800000 - 0x81ffff] mem
PCI: 00:14.4 mem: base: 820000 size: 900000 align: 23 gran: 20 limit: ffffffff done
PCI: 00:02.0 20 * [0x0 - 0x10fffff] mem
PCI: 00:14.4 20 * [0x1800000 - 0x20fffff] mem
PCI: 00:09.0 20 * [0x2100000 - 0x21fffff] mem
PCI: 00:0a.0 20 * [0x2200000 - 0x22fffff] mem
PCI: 00:00.2 44 * [0x2300000 - 0x2303fff] mem
PCI: 00:14.2 10 * [0x2304000 - 0x2307fff] mem
PCI: 00:12.0 10 * [0x2308000 - 0x2308fff] mem
PCI: 00:12.1 10 * [0x2309000 - 0x2309fff] mem
PCI: 00:13.0 10 * [0x230a000 - 0x230afff] mem
PCI: 00:13.1 10 * [0x230b000 - 0x230bfff] mem
PCI: 00:14.5 10 * [0x230c000 - 0x230cfff] mem
PCI: 00:11.0 24 * [0x230d000 - 0x230d3ff] mem
PCI: 00:12.2 10 * [0x230e000 - 0x230e0ff] mem
PCI: 00:13.2 10 * [0x230f000 - 0x230f0ff] mem
PCI: 00:14.3 a0 * [0x2310000 - 0x2310000] mem
PCI: 00:18.0 mem: base: 2310001 size: 2400000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:18.0 210b0 * [0x0 - 0xa0fffff] prefmem
PCI: 00:18.3 94 * [0xc000000 - 0xfffffff] mem
PCI: 00:18.0 210b8 * [0x10000000 - 0x123fffff] mem
DOMAIN: 0000 mem: base: 12400000 size: 12400000 align: 27 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
constrain_resources: PCI: 00:14.0 9c base feb00000 limit feb00fff mem (fixed)
constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e8000000 limit feafffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
PCI: 00:18.0 210d8 * [0x1000 - 0x5fff] io
DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
PCI: 00:02.0 1c * [0x1000 - 0x1fff] io
PCI: 00:09.0 1c * [0x2000 - 0x2fff] io
PCI: 00:0a.0 1c * [0x3000 - 0x3fff] io
PCI: 00:14.4 1c * [0x4000 - 0x4fff] io
PCI: 00:11.0 20 * [0x5000 - 0x500f] io
PCI: 00:14.1 20 * [0x5010 - 0x501f] io
PCI: 00:11.0 10 * [0x5020 - 0x5027] io
PCI: 00:11.0 18 * [0x5028 - 0x502f] io
PCI: 00:14.1 10 * [0x5030 - 0x5037] io
PCI: 00:14.1 18 * [0x5038 - 0x503f] io
PCI: 00:11.0 14 * [0x5040 - 0x5043] io
PCI: 00:11.0 1c * [0x5044 - 0x5047] io
PCI: 00:14.1 14 * [0x5048 - 0x504b] io
PCI: 00:14.1 1c * [0x504c - 0x504f] io
PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done
PCI: 00:02.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
PCI: 01:00.0 24 * [0x1000 - 0x107f] io
PCI: 00:02.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done
PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
PCI: 00:09.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 03:00.0 18 * [0x2000 - 0x201f] io
PCI: 00:09.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
PCI: 04:00.0 18 * [0x3000 - 0x301f] io
PCI: 00:0a.0 io: next_base: 3020 size: 1000 align: 12 gran: 12 done
PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff
PCI: 06:05.0 18 * [0x4000 - 0x407f] io
PCI: 00:14.4 io: next_base: 4080 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e8000000 size:12400000 align:27 gran:0 limit:feafffff
PCI: 00:18.0 210b0 * [0xe8000000 - 0xf20fffff] prefmem
PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem
PCI: 00:18.0 210b8 * [0xf8000000 - 0xfa3fffff] mem
DOMAIN: 0000 mem: next_base: fa400000 size: 12400000 align: 27 gran: 0 done
PCI: 00:18.0 prefmem: base:e8000000 size:a100000 align:27 gran:20 limit:f20fffff
PCI: 00:02.0 24 * [0xe8000000 - 0xf1ffffff] prefmem
PCI: 00:00.0 fc * [0xf2000000 - 0xf20000ff] prefmem
PCI: 00:18.0 prefmem: next_base: f2000100 size: a100000 align: 27 gran: 20 done
PCI: 00:02.0 prefmem: base:e8000000 size:a000000 align:27 gran:20 limit:f1ffffff
PCI: 01:00.0 14 * [0xe8000000 - 0xefffffff] prefmem
PCI: 01:00.0 1c * [0xf0000000 - 0xf1ffffff] prefmem
PCI: 00:02.0 prefmem: next_base: f2000000 size: a000000 align: 27 gran: 20 done
PCI: 00:04.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff
PCI: 00:04.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff
PCI: 00:09.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done
PCI: 00:0a.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff
PCI: 00:0a.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done
PCI: 00:0b.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff
PCI: 00:0b.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff
PCI: 00:14.4 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 mem: base:f8000000 size:2400000 align:24 gran:20 limit:fa3fffff
PCI: 00:02.0 20 * [0xf8000000 - 0xf90fffff] mem
PCI: 00:14.4 20 * [0xf9800000 - 0xfa0fffff] mem
PCI: 00:09.0 20 * [0xfa100000 - 0xfa1fffff] mem
PCI: 00:0a.0 20 * [0xfa200000 - 0xfa2fffff] mem
PCI: 00:00.2 44 * [0xfa300000 - 0xfa303fff] mem
PCI: 00:14.2 10 * [0xfa304000 - 0xfa307fff] mem
PCI: 00:12.0 10 * [0xfa308000 - 0xfa308fff] mem
PCI: 00:12.1 10 * [0xfa309000 - 0xfa309fff] mem
PCI: 00:13.0 10 * [0xfa30a000 - 0xfa30afff] mem
PCI: 00:13.1 10 * [0xfa30b000 - 0xfa30bfff] mem
PCI: 00:14.5 10 * [0xfa30c000 - 0xfa30cfff] mem
PCI: 00:11.0 24 * [0xfa30d000 - 0xfa30d3ff] mem
PCI: 00:12.2 10 * [0xfa30e000 - 0xfa30e0ff] mem
PCI: 00:13.2 10 * [0xfa30f000 - 0xfa30f0ff] mem
PCI: 00:14.3 a0 * [0xfa310000 - 0xfa310000] mem
PCI: 00:18.0 mem: next_base: fa310001 size: 2400000 align: 24 gran: 20 done
PCI: 00:02.0 mem: base:f8000000 size:1100000 align:24 gran:20 limit:f90fffff
PCI: 01:00.0 10 * [0xf8000000 - 0xf8ffffff] mem
PCI: 01:00.0 30 * [0xf9000000 - 0xf907ffff] mem
PCI: 01:00.1 10 * [0xf9080000 - 0xf9083fff] mem
PCI: 00:02.0 mem: next_base: f9084000 size: 1100000 align: 24 gran: 20 done
PCI: 00:04.0 mem: base:fa3fffff size:0 align:20 gran:20 limit:fa3fffff
PCI: 00:04.0 mem: next_base: fa3fffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 mem: base:fa100000 size:100000 align:20 gran:20 limit:fa1fffff
PCI: 03:00.0 10 * [0xfa100000 - 0xfa11ffff] mem
PCI: 03:00.0 1c * [0xfa120000 - 0xfa123fff] mem
PCI: 00:09.0 mem: next_base: fa124000 size: 100000 align: 20 gran: 20 done
PCI: 00:0a.0 mem: base:fa200000 size:100000 align:20 gran:20 limit:fa2fffff
PCI: 04:00.0 10 * [0xfa200000 - 0xfa21ffff] mem
PCI: 04:00.0 1c * [0xfa220000 - 0xfa223fff] mem
PCI: 00:0a.0 mem: next_base: fa224000 size: 100000 align: 20 gran: 20 done
PCI: 00:0b.0 mem: base:fa3fffff size:0 align:20 gran:20 limit:fa3fffff
PCI: 00:0b.0 mem: next_base: fa3fffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 mem: base:f9800000 size:900000 align:23 gran:20 limit:fa0fffff
PCI: 06:05.0 10 * [0xf9800000 - 0xf9ffffff] mem
PCI: 06:05.0 14 * [0xfa000000 - 0xfa01ffff] mem
PCI: 00:14.4 mem: next_base: fa020000 size: 900000 align: 23 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=00300000, basek=00400000, limitk=01100000
DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 2 has VGA device
PCI: 00:18.0 211b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 2>
PCI: 00:18.0 210b0 <- [0x00e8000000 - 0x00f20fffff] size 0x0a100000 gran 0x14 prefmem <node 0 link 2>
PCI: 00:18.0 210b8 <- [0x00f8000000 - 0x00fa3fffff] size 0x02400000 gran 0x14 mem <node 0 link 2>
PCI: 00:18.0 210d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 2>
PCI: 00:18.0 assign_resources, bus 0 link: 2
PCI: 00:00.0 sr5690_set_resources
sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig>
sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfffa0
PCI: 00:00.0 fc <- [0x00f2000000 - 0x00f20000ff] size 0x00000100 gran 0x08 prefmem
PCI: 00:00.2 44 <- [0x00fa300000 - 0x00fa303fff] size 0x00004000 gran 0x0e mem
PCI: 00:02.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:02.0 24 <- [0x00e8000000 - 0x00f1ffffff] size 0x0a000000 gran 0x14 bus 01 prefmem
PCI: 00:02.0 20 <- [0x00f8000000 - 0x00f90fffff] size 0x01100000 gran 0x14 bus 01 mem
PCI: 00:02.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000 gran 0x18 mem
PCI: 01:00.0 14 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x1b prefmem64
PCI: 01:00.0 1c <- [0x00f0000000 - 0x00f1ffffff] size 0x02000000 gran 0x19 prefmem64
PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io
PCI: 01:00.0 30 <- [0x00f9000000 - 0x00f907ffff] size 0x00080000 gran 0x13 romem
PCI: 01:00.1 10 <- [0x00f9080000 - 0x00f9083fff] size 0x00004000 gran 0x0e mem
PCI: 00:02.0 assign_resources, bus 1 link: 0
PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:04.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:04.0 20 <- [0x00fa3fffff - 0x00fa3ffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:09.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:09.0 20 <- [0x00fa100000 - 0x00fa1fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00fa100000 - 0x00fa11ffff] size 0x00020000 gran 0x11 mem
PCI: 03:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 03:00.0 1c <- [0x00fa120000 - 0x00fa123fff] size 0x00004000 gran 0x0e mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 00:0a.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:0a.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:0a.0 20 <- [0x00fa200000 - 0x00fa2fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00fa200000 - 0x00fa21ffff] size 0x00020000 gran 0x11 mem
PCI: 04:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
PCI: 04:00.0 1c <- [0x00fa220000 - 0x00fa223fff] size 0x00004000 gran 0x0e mem
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:0b.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:0b.0 20 <- [0x00fa3fffff - 0x00fa3ffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00fa30d000 - 0x00fa30d3ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00fa308000 - 0x00fa308fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.1 10 <- [0x00fa309000 - 0x00fa309fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00fa30e000 - 0x00fa30e0ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00fa30a000 - 0x00fa30afff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00fa30b000 - 0x00fa30bfff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00fa30f000 - 0x00fa30f0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00fa304000 - 0x00fa307fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00fa310000 - 0x00fa310000] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 06 io
PCI: 00:14.4 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 06 prefmem
PCI: 00:14.4 20 <- [0x00f9800000 - 0x00fa0fffff] size 0x00900000 gran 0x14 bus 06 mem
PCI: 00:14.4 assign_resources, bus 6 link: 0
PCI: 06:05.0 10 <- [0x00f9800000 - 0x00f9ffffff] size 0x00800000 gran 0x17 mem
PCI: 06:05.0 14 <- [0x00fa000000 - 0x00fa01ffff] size 0x00020000 gran 0x11 mem
PCI: 06:05.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io
PCI: 00:14.4 assign_resources, bus 6 link: 0
PCI: 00:14.5 10 <- [0x00fa30c000 - 0x00fa30cfff] size 0x00001000 gran 0x0c mem
PCI: 00:18.0 assign_resources, bus 0 link: 2
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
APIC: 02
APIC: 03
APIC: 04
APIC: 05
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base e8000000 size 12400000 align 27 gran 0 limit feafffff flags 40040200 index 10000100
DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
DOMAIN: 0000 resource base 100000000 size 340000000 align 0 gran 0 limit 0 flags e0004200 index 30
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base e8000000 size a100000 align 27 gran 20 limit f20fffff flags 60081200 index 210b0
PCI: 00:18.0 resource base f8000000 size 2400000 align 24 gran 20 limit fa3fffff flags 60080200 index 210b8
PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 210d8
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 211b8
PCI: 00:00.0
PCI: 00:00.0 resource base f2000000 size 100 align 12 gran 8 limit f20000ff flags 60001200 index fc
PCI: 00:00.1
PCI: 00:00.2
PCI: 00:00.2 resource base fa300000 size 4000 align 14 gran 14 limit fa303fff flags 70000200 index 44
PCI: 00:02.0 child on link 0 PCI: 01:00.0
PCI: 00:02.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
PCI: 00:02.0 resource base e8000000 size a000000 align 27 gran 20 limit f1ffffff flags 60081202 index 24
PCI: 00:02.0 resource base f8000000 size 1100000 align 24 gran 20 limit f90fffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base f8000000 size 1000000 align 24 gran 24 limit f8ffffff flags 60000200 index 10
PCI: 01:00.0 resource base e8000000 size 8000000 align 27 gran 27 limit efffffff flags 60001201 index 14
PCI: 01:00.0 resource base f0000000 size 2000000 align 25 gran 25 limit f1ffffff flags 60001201 index 1c
PCI: 01:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24
PCI: 01:00.0 resource base f9000000 size 80000 align 19 gran 19 limit f907ffff flags 60002200 index 30
PCI: 01:00.1
PCI: 01:00.1 resource base f9080000 size 4000 align 14 gran 14 limit f9083fff flags 60000200 index 10
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
PCI: 00:04.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24
PCI: 00:04.0 resource base fa3fffff size 0 align 20 gran 20 limit fa3fffff flags 60080202 index 20
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0 child on link 0 PCI: 03:00.0
PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
PCI: 00:09.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24
PCI: 00:09.0 resource base fa100000 size 100000 align 20 gran 20 limit fa1fffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base fa100000 size 20000 align 17 gran 17 limit fa11ffff flags 60000200 index 10
PCI: 03:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
PCI: 03:00.0 resource base fa120000 size 4000 align 14 gran 14 limit fa123fff flags 60000200 index 1c
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
PCI: 00:0a.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
PCI: 00:0a.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24
PCI: 00:0a.0 resource base fa200000 size 100000 align 20 gran 20 limit fa2fffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base fa200000 size 20000 align 17 gran 17 limit fa21ffff flags 60000200 index 10
PCI: 04:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18
PCI: 04:00.0 resource base fa220000 size 4000 align 14 gran 14 limit fa223fff flags 60000200 index 1c
PCI: 00:0b.0
PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
PCI: 00:0b.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24
PCI: 00:0b.0 resource base fa3fffff size 0 align 20 gran 20 limit fa3fffff flags 60080202 index 20
PCI: 00:11.0
PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10
PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14
PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18
PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c
PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20
PCI: 00:11.0 resource base fa30d000 size 400 align 12 gran 10 limit fa30d3ff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base fa308000 size 1000 align 12 gran 12 limit fa308fff flags 60000200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base fa309000 size 1000 align 12 gran 12 limit fa309fff flags 60000200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base fa30e000 size 100 align 12 gran 8 limit fa30e0ff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base fa30a000 size 1000 align 12 gran 12 limit fa30afff flags 60000200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base fa30b000 size 1000 align 12 gran 12 limit fa30bfff flags 60000200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base fa30f000 size 100 align 12 gran 8 limit fa30f0ff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:2f
PCI: 00:14.1
PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10
PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14
PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18
PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c
PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base fa304000 size 4000 align 14 gran 14 limit fa307fff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base fa310000 size 1 align 12 gran 0 limit fa310000 flags 60000200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 002e.106
PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
PNP: 002e.107
PNP: 002e.207
PNP: 002e.307
PNP: 002e.407
PNP: 002e.8
PNP: 002e.108
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.d
PNP: 002e.f
PCI: 00:14.4 child on link 0 PCI: 06:01.0
PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
PCI: 00:14.4 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24
PCI: 00:14.4 resource base f9800000 size 900000 align 23 gran 20 limit fa0fffff flags 60080202 index 20
PCI: 06:01.0
PCI: 06:02.0
PCI: 06:03.0
PCI: 06:05.0
PCI: 06:05.0 resource base f9800000 size 800000 align 23 gran 23 limit f9ffffff flags 60000200 index 10
PCI: 06:05.0 resource base fa000000 size 20000 align 17 gran 17 limit fa01ffff flags 60000200 index 14
PCI: 06:05.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18
PCI: 06:05.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
PCI: 00:14.5
PCI: 00:14.5 resource base fa30c000 size 1000 align 12 gran 12 limit fa30cfff flags 60000200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit f7ffffff flags 60000200 index 94
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:19.0
PCI: 00:19.1
PCI: 00:19.2
PCI: 00:19.3
PCI: 00:19.4
PCI: 00:19.5
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 3348520 exit 0
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1043/8163
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1043/8163
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 cmd <- 00
PCI: 00:00.0 subsystem <- 1043/8163
PCI: 00:00.0 cmd <- 02
Initializing IOMMU
PCI: 00:02.0 bridge ctrl <- 0003
PCI: 00:02.0 cmd <- 07
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 00
PCI: 00:09.0 bridge ctrl <- 0003
PCI: 00:09.0 cmd <- 07
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 07
PCI: 00:0b.0 bridge ctrl <- 0003
PCI: 00:0b.0 cmd <- 00
PCI: 00:11.0 subsystem <- 1043/8163
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1043/8163
PCI: 00:12.0 cmd <- 02
PCI: 00:12.1 subsystem <- 1043/8163
PCI: 00:12.1 cmd <- 02
PCI: 00:12.2 subsystem <- 1043/8163
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1043/8163
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1043/8163
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1043/8163
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1043/8163
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1043/8163
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 1043/8163
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1043/8163
PCI: 00:14.3 cmd <- 0f
sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
PCI: 00:14.4 bridge ctrl <- 000b
PCI: 00:14.4 cmd <- 07
PCI: 00:14.5 subsystem <- 1043/8163
PCI: 00:14.5 cmd <- 02
PCI: 01:00.0 cmd <- 03
PCI: 01:00.1 cmd <- 02
PCI: 03:00.0 cmd <- 03
PCI: 04:00.0 cmd <- 03
PCI: 06:05.0 cmd <- 03
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 143827 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 1715 usecs
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
CPU1: stack_base 00141000, stack_end 00141ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f12
After Startup.
CPU: family 15, model 01, stepping 02
CPU2: stack_base 00140000, stack_end 00140ff8
nodeid = 00, coreid = 01
Asserting INIT.
Enabling cache
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 2.
After apic_write.
Initializing CPU #2
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f12
After Startup.
CPU3: stack_base 0013f000, stack_end 0013fff8
CPU: family 15, model 01, stepping 02
Asserting INIT.
Waiting for send to finish...
+nodeid = 00, coreid = 02
Deasserting INIT.
Waiting for send to finish...
+Enabling cache
#startup loops: 1.
Sending STARTUP #1 to 3.
CPU ID 0x80000001: 600f12
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
After apic_write.
Initializing CPU #3
MTRR: Physical address space:
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f12
After Startup.
CPU4: stack_base 0013e000, stack_end 0013eff8
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
Asserting INIT.
Waiting for send to finish...
+CPU: family 15, model 01, stepping 02
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
Deasserting INIT.
Waiting for send to finish...
+nodeid = 00, coreid = 03
#startup loops: 1.
Sending STARTUP #1 to 4.
After apic_write.
Enabling cache
Startup point 1.
Waiting for send to finish...
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
0x00000000c0000000 - 0x00000000e8000000 size 0x28000000 type 0
0x00000000e8000000 - 0x00000000f2000000 size 0x0a000000 type 1
0x00000000f2000000 - 0x0000000100000000 size 0x0e000000 type 0
0x0000000100000000 - 0x0000000440000000 size 0x340000000 type 6
After Startup.
CPU5: stack_base 0013d000, stack_end 0013dff8
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
Asserting INIT.
Waiting for send to finish...
+MTRR: default type WB/UC MTRR counts: 7/4.
MTRR: UC selected as default type.
Deasserting INIT.
MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6
Waiting for send to finish...
+MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6
MTRR: 2 base 0x00000000e8000000 mask 0x0000fffff8000000 type 1
MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffe000000 type 1
#startup loops: 1.
Sending STARTUP #1 to 5.
After apic_write.

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

Startup point 1.
Waiting for send to finish...
+Setting up local APIC...After Startup.
Initializing CPU #0
apic_id: 0x02 CPU: vendor AMD device 600f12
CPU: family 15, model 01, stepping 02
done.
nodeid = 00, coreid = 00
CPU model: AMD Opteron(tm) Processor 4238
Enabling cache
siblings = 05, Initializing CPU #5
Disabling SMM ASeg memory
CPU ID 0x80000001: 600f12
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
Setting up local APIC...CPU #2 initialized
apic_id: 0x03 done.
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
CPU model: AMD Opteron(tm) Processor 4238
CPU: vendor AMD device 600f12

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

siblings = 05, CPU: family 15, model 01, stepping 02
Disabling SMM ASeg memory
Setting up local APIC...CPU #3 initialized
apic_id: 0x00 done.
nodeid = 00, coreid = 05
CPU model: AMD Opteron(tm) Processor 4238
Initializing CPU #4
siblings = 05, CPU: vendor AMD device 600f12
Disabling SMM ASeg memory
CPU: family 15, model 01, stepping 02
CPU #0 initialized

MTRR check
CPU_CLUSTER: 0 init finished in 373831 usecs
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

nodeid = 00, coreid = 04
Setting up local APIC...PCI: 00:18.0 init ...
apic_id: 0x01 done.
PCI: 00:18.0 init finished in 9777 usecs
CPU model: AMD Opteron(tm) Processor 4238
PCI: 00:18.1 init ...
siblings = 05, PCI: 00:18.1 init finished in 5131 usecs
Enabling cache
Disabling SMM ASeg memory
PCI: 00:18.2 init ...
CPU #1 initialized
PCI: 00:18.2 init finished in 5155 usecs
Enabling cache
PCI: 00:18.3 init ...
NB: Function 3 Misc Control.. CPU ID 0x80000001: 600f12
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
done.
PCI: 00:18.3 init finished in 13858 usecs
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
PCI: 00:18.4 init ...
NB: Function 4 Link Control.. done.

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

PCI: 00:18.4 init finished in 40564 usecs
Setting up local APIC...PCI: 00:18.5 init ...
NB: Function 5 Northbridge Control.. apic_id: 0x04 done.
done.
CPU model: AMD Opteron(tm) Processor 4238
PCI: 00:18.5 init finished in 8826 usecs
siblings = 05, PCI: 00:00.0 init ...
pcie_init in sr5650_ht.c
Disabling SMM ASeg memory
IOAPIC: Initializing IOAPIC at 0xf2000000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x01
CPU #4 initialized
IOAPIC: Dumping registers

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

reg 0x0000: 0x01000000
Setting up local APIC... reg 0x0001: 0x001f8021
apic_id: 0x05 done.
reg 0x0002: 0x00000000
CPU model: AMD Opteron(tm) Processor 4238
IOAPIC: 32 interrupts
IOAPIC: Enabling interrupts on FSB
siblings = 05, IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
Disabling SMM ASeg memory
PCI: 00:00.0 init finished in 172314 usecs
CPU #5 initialized
PCI: 00:11.0 init ...
rev_id=15
sata_bar0=5020
sata_bar1=5040
sata_bar2=5028
sata_bar3=5044
sata_bar4=5000
sata_bar5=fa30d000
ide_bar0=5030
ide_bar1=5048
ide_bar2=5038
ide_bar3=504c
Maximum SATA port count supported by silicon: 4
SATA port 0 status = 23
drive detection done after 0 ms
Primary Master device is ready after 1 tries
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:11.0 init finished in 50642 usecs
PCI: 00:12.0 init ...
PCI: 00:12.0 init finished in 1819 usecs
PCI: 00:12.1 init ...
PCI: 00:12.1 init finished in 1818 usecs
PCI: 00:12.2 init ...
usb2_bar0=0xfa30e000
rpr 6.23, final dword=809e03c8
PCI: 00:12.2 init finished in 6004 usecs
PCI: 00:13.0 init ...
PCI: 00:13.0 init finished in 1819 usecs
PCI: 00:13.1 init ...
PCI: 00:13.1 init finished in 1818 usecs
PCI: 00:13.2 init ...
usb2_bar0=0xfa30f000
rpr 6.23, final dword=809e03c8
PCI: 00:13.2 init finished in 6005 usecs
PCI: 00:14.0 init ...
sm_init().
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: Dumping registers
reg 0x0000: 0x00000000
reg 0x0001: 0x00178021
reg 0x0002: 0x00000000
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
set power "on" after power fail
++++++++++no set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.0 init finished in 126155 usecs
PCI: 00:14.1 init ...
PCI: 00:14.1 init finished in 1795 usecs
PCI: 00:14.2 init ...
base = 0xfa304000
No codec!
PCI: 00:14.2 init finished in 7721 usecs
PCI: 00:14.3 init ...
lpc_init
PCI: 00:14.3 init finished in 2607 usecs
PCI: 00:14.4 init ...
PCI: 00:14.4 init finished in 1813 usecs
PCI: 00:14.5 init ...
PCI: 00:14.5 init finished in 1819 usecs
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 1792 usecs
PCI: 01:00.1 init ...
PCI: 01:00.1 init finished in 1792 usecs
PCI: 03:00.0 init ...
PCI: 03:00.0 init finished in 1792 usecs
PCI: 04:00.0 init ...
PCI: 04:00.0 init finished in 1791 usecs
smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
Set SMBUS controller to channel 1
Found 64 pin W83795G Nuvoton H/W Monitor
W83795G/ADG work in Thermal Cruise Mode
Fan CTFS(celsius) TTTI(celsius)
1 80 80
2 80 80
3 80 80
4 80 80
5 80 80
6 80 80
DTS1 current value: 1c
DTS2 current value: 0
DTS3 current value: 0
DTS4 current value: 0
DTS5 current value: 0
DTS6 current value: 0
DTS7 current value: 0
DTS8 current value: 0
Set SMBUS controller to channel 0
I2C: 01:2f init finished in 347909 usecs
PNP: 002e.2 init ...
PNP: 002e.2 init finished in 1712 usecs
PNP: 002e.3 init ...
PNP: 002e.3 init finished in 1714 usecs
PNP: 002e.5 init ...
w83667hg_a_init: Disable mouse controller.PNP: 002e.5 init finished in 4994 usecs
PNP: 002e.a init ...
set power on after power fail
PNP: 002e.a init finished in 4129 usecs
PNP: 002e.b init ...
PNP: 002e.b init finished in 1714 usecs
PCI: 06:05.0 init ...
ASpeed AST2050: initializing video device
ast_detect_chip: AST 1100 detected
ast_detect_chip: VGA not enabled on entry, requesting chip POST
ast_detect_chip: Analog VGA only
ast_driver_load: dram 12000000 0 32 00800000
ASpeed VGA text mode initialized
PCI: 06:05.0 init finished in 40728 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 0
PCI: 00:00.2: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 01:50: enabled 1
I2C: 01:51: enabled 1
I2C: 01:52: enabled 1
I2C: 01:53: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:2f: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.106: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 0
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.108: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 0
PNP: 002e.f: enabled 0
PCI: 00:14.4: enabled 1
PCI: 06:01.0: enabled 0
PCI: 06:02.0: enabled 0
PCI: 06:03.0: enabled 0
PCI: 06:05.0: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:19.0: enabled 0
PCI: 00:19.1: enabled 0
PCI: 00:19.2: enabled 0
PCI: 00:19.3: enabled 0
PCI: 00:19.4: enabled 0
PCI: 00:19.5: enabled 0
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
PCI: 01:00.0: enabled 1
PCI: 01:00.1: enabled 1
PCI: 03:00.0: enabled 1
PCI: 04:00.0: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 1545565 exit 0
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 3123 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
Writing IRQ routing tables to 0xf0000...done.
Writing IRQ routing tables to 0xbfcbe000...done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f069c
Wrote the mp table end at: bfcbd010 - bfcbd29c
MP table: 668 bytes.
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 2b000 size 2606
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at bfc99000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * FADT
pm_base: 0x0800
ACPI: added table 1/32, length now 40
ACPI: * SSDT
processor_brand=AMD Opteron(tm) Processor 4238
Pstates algorithm ...
Pstate_freq[0] = 3300MHz Pstate_power[0] = 17640mw
Pstate_latency[0] = 5us
Pstate_freq[1] = 3000MHz Pstate_power[1] = 14298mw
Pstate_latency[1] = 5us
Pstate_freq[2] = 2400MHz Pstate_power[2] = 9987mw
Pstate_latency[2] = 5us
Pstate_freq[3] = 1800MHz Pstate_power[3] = 7122mw
Pstate_latency[3] = 5us
Pstate_freq[4] = 1400MHz Pstate_power[4] = 4950mw
Pstate_latency[4] = 5us
PSS: 3300MHz power 17640 control 0x0 status 0x0
PSS: 3000MHz power 14298 control 0x1 status 0x1
PSS: 2400MHz power 9987 control 0x2 status 0x2
PSS: 1800MHz power 7122 control 0x3 status 0x3
PSS: 1400MHz power 4950 control 0x4 status 0x4
PSS: 3300MHz power 17640 control 0x0 status 0x0
PSS: 3000MHz power 14298 control 0x1 status 0x1
PSS: 2400MHz power 9987 control 0x2 status 0x2
PSS: 1800MHz power 7122 control 0x3 status 0x3
PSS: 1400MHz power 4950 control 0x4 status 0x4
PSS: 3300MHz power 17640 control 0x0 status 0x0
PSS: 3000MHz power 14298 control 0x1 status 0x1
PSS: 2400MHz power 9987 control 0x2 status 0x2
PSS: 1800MHz power 7122 control 0x3 status 0x3
PSS: 1400MHz power 4950 control 0x4 status 0x4
PSS: 3300MHz power 17640 control 0x0 status 0x0
PSS: 3000MHz power 14298 control 0x1 status 0x1
PSS: 2400MHz power 9987 control 0x2 status 0x2
PSS: 1800MHz power 7122 control 0x3 status 0x3
PSS: 1400MHz power 4950 control 0x4 status 0x4
PSS: 3300MHz power 17640 control 0x0 status 0x0
PSS: 3000MHz power 14298 control 0x1 status 0x1
PSS: 2400MHz power 9987 control 0x2 status 0x2
PSS: 1800MHz power 7122 control 0x3 status 0x3
PSS: 1400MHz power 4950 control 0x4 status 0x4
PSS: 3300MHz power 17640 control 0x0 status 0x0
PSS: 3000MHz power 14298 control 0x1 status 0x1
PSS: 2400MHz power 9987 control 0x2 status 0x2
PSS: 1800MHz power 7122 control 0x3 status 0x3
PSS: 1400MHz power 4950 control 0x4 status 0x4
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TCPA
TCPA log created at bfc89000
ACPI: added table 4/32, length now 52
ACPI: * MADT
ACPI: added table 5/32, length now 56
current = bfc9c850
ACPI: * SRAT at bfc9c850
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000
ACPI: added table 6/32, length now 60
ACPI: * SLIT at bfc9c958
ACPI: added table 7/32, length now 64
ACPI: * IVRS at bfc9c990
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0x40
ACPI: added table 8/32, length now 68
ACPI: * HPET
ACPI: added table 9/32, length now 72
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'pci10de,1187.rom'
CBFS: 'pci10de,1187.rom' not found.
PCI Option ROM loading disabled for PCI: 01:00.0
ACPI: done.
ACPI tables: 14976 bytes.
smbios_write_tables: bfc88000
Root Device (ASUS KCMA-D8)
CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
APIC: 00 (unknown)
DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
PCI: 00:00.0 (ATI SR5650)
PCI: 00:00.1 (ATI SR5650)
PCI: 00:00.2 (ATI SR5650)
PCI: 00:02.0 (ATI SR5650)
PCI: 00:03.0 (ATI SR5650)
PCI: 00:04.0 (ATI SR5650)
PCI: 00:05.0 (ATI SR5650)
PCI: 00:06.0 (ATI SR5650)
PCI: 00:07.0 (ATI SR5650)
PCI: 00:08.0 (ATI SR5650)
PCI: 00:09.0 (ATI SR5650)
PCI: 00:0a.0 (ATI SR5650)
PCI: 00:0b.0 (ATI SR5650)
PCI: 00:11.0 (ATI SP5100)
PCI: 00:12.0 (ATI SP5100)
PCI: 00:12.1 (ATI SP5100)
PCI: 00:12.2 (ATI SP5100)
PCI: 00:13.0 (ATI SP5100)
PCI: 00:13.1 (ATI SP5100)
PCI: 00:13.2 (ATI SP5100)
PCI: 00:14.0 (ATI SP5100)
I2C: 01:50 (unknown)
I2C: 01:51 (unknown)
I2C: 01:52 (unknown)
I2C: 01:53 (unknown)
I2C: 01:54 (unknown)
I2C: 01:55 (unknown)
I2C: 01:56 (unknown)
I2C: 01:57 (unknown)
I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
PCI: 00:14.1 (ATI SP5100)
PCI: 00:14.2 (ATI SP5100)
PCI: 00:14.3 (ATI SP5100)
PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
PNP: 002e.a (WINBOND W83667HG-A Super I/O)
PNP: 002e.b (WINBOND W83667HG-A Super I/O)
PNP: 002e.c (WINBOND W83667HG-A Super I/O)
PNP: 002e.d (WINBOND W83667HG-A Super I/O)
PNP: 002e.f (WINBOND W83667HG-A Super I/O)
PCI: 00:14.4 (ATI SP5100)
PCI: 06:01.0 (ATI SP5100)
PCI: 06:02.0 (ATI SP5100)
PCI: 06:03.0 (ATI SP5100)
PCI: 06:05.0 (ATI SP5100)
PCI: 00:14.5 (ATI SP5100)
PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
PCI: 01:00.0 (unknown)
PCI: 01:00.1 (unknown)
PCI: 03:00.0 (unknown)
PCI: 04:00.0 (unknown)
SMBIOS tables: 437 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5012
Writing coreboot table at 0xbfcbf000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000bffff: RESERVED
3. 00000000000c0000-00000000bfc87fff: RAM
4. 00000000bfc88000-00000000bfffffff: CONFIGURATION TABLES
5. 00000000c0000000-00000000cfffffff: RESERVED
6. 00000000fa300000-00000000fa303fff: RESERVED
7. 00000000feb00000-00000000feb00fff: RESERVED
8. 00000000fec00000-00000000fec00fff: RESERVED
9. 00000000fed00000-00000000fed00fff: RESERVED
10. 0000000100000000-000000043fffffff: RAM
Manufacturer: ef
SF: Detected W25Q16 with sector size 0x1000, total 0x200000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
FMAP: Found "FLASH" version 1.1 at 0.
FMAP: base = ffe00000 size = 200000 #areas = 3
Wrote coreboot table at: bfcbf000, 0x358 bytes, checksum 745
coreboot table: 880 bytes.
IMD ROOT 0. bffff000 00001000
IMD SMALL 1. bfffe000 00001000
CAR GLOBALS 2. bfff3000 0000a6c0
CONSOLE 3. bffd3000 00020000
TIME STAMP 4. bffd2000 00000400
AMDMEM INFO 5. bffc8000 000093fc
ACPI RESUME 6. bfcc7000 00301000
COREBOOT 7. bfcbf000 00008000
IRQ TABLE 8. bfcbe000 00001000
SMP TABLE 9. bfcbd000 00001000
ACPI 10. bfc99000 00024000
TCPA LOG 11. bfc89000 00010000
SMBIOS 12. bfc88000 00000800
IMD small region:
IMD ROOT 0. bfffec00 00000400
ROMSTAGE 1. bfffebe0 00000004
GDT 2. bfffe9e0 00000200
COREBOOTFWD 3. bfffe9a0 00000028
Writing AMD DCT configuration to Flash
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
Manufacturer: ef
SF: Detected W25Q16 with sector size 0x1000, total 0x200000
SF: Successfully erased 32768 bytes @ 0x38000
BS: BS_WRITE_TABLES times (us): entry 0 run 1355369 exit 0
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 55bc0 size 10ac7
Loading segment from ROM address 0xffe55cf8
code (compression=1)
New segment dstaddr 0xe04e0 memsize 0x1fb20 srcaddr 0xffe55d30 filesize 0x10a8f
Loading segment from ROM address 0xffe55d14
Entry Point 0x000fd258
Bounce Buffer at bfa77000, 2163680 bytes
Loading Segment: addr: 0x00000000000e04e0 memsz: 0x000000000001fb20 filesz: 0x0000000000010a8f
lb: [0x0000000000100000, 0x00000000002081f0)
Post relocation: addr: 0x00000000000e04e0 memsz: 0x000000000001fb20 filesz: 0x0000000000010a8f
using LZMA
[ 0x000e04e0, 00100000, 0x00100000) <- ffe55d30
dest 000e04e0, end 00100000, bouncebuffer bfa77000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 94397 exit 0
Jumping to boot code at 000fd258(bfcbf000)
CPU0: stack: 00142000 - 00143000, lowest used address 001429e0, stack used: 1568 bytes
entry = 0x000fd258
lb_start = 0x00100000
lb_size = 0x001081f0
buffer = 0xbfa77000
SeaBIOS (version rel-1.11.0-0-g63451fc)
BUILD: gcc: (coreboot toolchain v1.43 August 31st, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
SeaBIOS (version rel-1.11.0-0-g63451fc)
BUILD: gcc: (coreboot toolchain v1.43 August 31st, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
Found coreboot cbmem console @ bffd3000
Found mainboard ASUS KCMA-D8
Relocating init from 0x000e1b00 to 0xbfc3b320 (size 52288)
Found CBFS header at 0xffe00138
multiboot: eax=0, ebx=0
Found 32 PCI devices (max PCI bus is 06)
Copying SMBIOS entry point from 0xbfc88000 to 0x000f61e0
Copying ACPI RSDP from 0xbfc99000 to 0x000f61b0
Skipping MPTABLE copy due to large size (668 bytes)
Copying PIR from 0xbfcbe000 to 0x000f6180
Using pmtimer, ioport 0x820
Scan for VGA option rom
Turning on vga text mode console
SeaBIOS (version rel-1.11.0-0-g63451fc)
EHCI init on dev 00:12.2 (regs=0xfa30e020)
EHCI init on dev 00:13.2 (regs=0xfa30f020)
OHCI init on dev 00:12.0 (regs=0xfa308000)
OHCI init on dev 00:12.1 (regs=0xfa309000)
OHCI init on dev 00:13.0 (regs=0xfa30a000)
OHCI init on dev 00:13.1 (regs=0xfa30b000)
OHCI init on dev 00:14.5 (regs=0xfa30c000)
ATA controller 1 at 5020/5040/0 (irq 0 dev 88)
ATA controller 2 at 5028/5044/0 (irq 0 dev 88)
ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1)
ATA controller 4 at 170/374/0 (irq 15 dev a1)
Got ps2 nak (status=51)
Found 0 lpt ports
Found 2 serial ports
ata0-0: SAMSUNG SSD UM410 Series 2.5" 16GB ATA-7 Hard-Disk (15272 MiBytes)
Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
USB keyboard initialized
All threads complete.
Scan for option roms

Press ESC for boot menu.

Searching bootorder for: HALT
drive 0x000f60d0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=31277232
Space available for UMB: c0000-ed800, f5a00-f60d0
Returned 253952 bytes of ZoneHigh
e820 map has 10 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 00000000bfc86000 = 1 RAM
4: 00000000bfc86000 - 00000000d0000000 = 2 RESERVED
5: 00000000fa300000 - 00000000fa304000 = 2 RESERVED
6: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
7: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
8: 00000000fed00000 - 00000000fed01000 = 2 RESERVED
9: 0000000100000000 - 0000000440000000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
(3-3/3)