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Bug #151 » coreboot-4.6-2479-g8e4384d.cap

Log of commit 4.6-2479-g8e4384d (current master) - Patrick McDermott, 12/31/2017 05:22 AM

 


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0020
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de00 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x3806684c
FIDVID on BSP, APIC_id: 00
BSP fid = 0
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 0 as APIC ID for node 0, core 0
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
Wait for AP stage 1: ap_apicid = 1
readback = 1000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 2
readback = 2000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 3
readback = 3000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 4
readback = 4000014
common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 5
readback = 5000014
common_fid(packed) = 0
common_fid = 0
End FIDVIDMSR 0xc0010071 0x5aca009e 0x3806684c
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
...WARM RESET...


soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de00 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
...WARM RESET...


soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de00 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01stopped
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02stopped
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03stopped
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04stopped
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05stopped

fill_mem_ctrl() detected 1 nodes
raminit_amdmct()
raminit_amdmct begin:
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_preInitDCT
DIMMPresence: DIMMValid=4
DIMMPresence: DIMMPresent=4
DIMMPresence: RegDIMMPresent=4
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=4
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=4
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=4
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done

DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
mctAutoInitMCT_D: DIMMSetVoltage
Node 00 DIMM voltage set to index 01
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 5
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3ffffff BottomIO: c00000
Node: 00 base: 03 limit: 43fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0041
Lane 00 nibble 0 adjusted value (pre nibble): 0041
Lane 00 nibble 0 adjusted value (post nibble): 0041
Lane 01 nibble 0 raw readback: 0040
Lane 01 nibble 0 adjusted value (pre nibble): 0040
Lane 01 nibble 0 adjusted value (post nibble): 0040
Lane 02 nibble 0 raw readback: 003c
Lane 02 nibble 0 adjusted value (pre nibble): 003c
Lane 02 nibble 0 adjusted value (post nibble): 003c
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0041
Lane 06 nibble 0 adjusted value (pre nibble): 0041
Lane 06 nibble 0 adjusted value (post nibble): 0041
Lane 07 nibble 0 raw readback: 0043
Lane 07 nibble 0 adjusted value (pre nibble): 0043
Lane 07 nibble 0 adjusted value (post nibble): 0043
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0047
Lane 00 nibble 0 adjusted value (pre nibble): 0047
Lane 00 nibble 0 adjusted value (post nibble): 0047
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 0040
Lane 02 nibble 0 adjusted value (pre nibble): 0040
Lane 02 nibble 0 adjusted value (post nibble): 0040
Lane 03 nibble 0 raw readback: 003b
Lane 03 nibble 0 adjusted value (pre nibble): 003b
Lane 03 nibble 0 adjusted value (post nibble): 003b
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0046
Lane 06 nibble 0 adjusted value (pre nibble): 0046
Lane 06 nibble 0 adjusted value (post nibble): 0046
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0053
Lane 00 new seed: 0053
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 004a
Lane 02 new seed: 004a
Lane 03 scaled delay: 0043
Lane 03 new seed: 0043
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 0052
Lane 06 new seed: 0052
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0052
Lane 01 nibble 0 adjusted value (pre nibble): 0052
Lane 01 nibble 0 adjusted value (post nibble): 0052
Lane 02 nibble 0 raw readback: 004c
Lane 02 nibble 0 adjusted value (pre nibble): 004c
Lane 02 nibble 0 adjusted value (post nibble): 004c
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0042
Lane 04 nibble 0 adjusted value (pre nibble): 0042
Lane 04 nibble 0 adjusted value (post nibble): 0042
Lane 05 nibble 0 raw readback: 004b
Lane 05 nibble 0 adjusted value (pre nibble): 004b
Lane 05 nibble 0 adjusted value (post nibble): 004b
Lane 06 nibble 0 raw readback: 0054
Lane 06 nibble 0 adjusted value (pre nibble): 0054
Lane 06 nibble 0 adjusted value (post nibble): 0054
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003b
Lane 08 nibble 0 adjusted value (pre nibble): 003b
Lane 08 nibble 0 adjusted value (post nibble): 003b
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005e
Lane 01 new seed: 005e
Lane 02 scaled delay: 0057
Lane 02 new seed: 0057
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 004a
Lane 04 new seed: 004a
Lane 05 scaled delay: 0055
Lane 05 new seed: 0055
Lane 06 scaled delay: 0061
Lane 06 new seed: 0061
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0041
Lane 08 new seed: 0041
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005e
Lane 01 nibble 0 adjusted value (pre nibble): 005e
Lane 01 nibble 0 adjusted value (post nibble): 005e
Lane 02 nibble 0 raw readback: 0056
Lane 02 nibble 0 adjusted value (pre nibble): 0056
Lane 02 nibble 0 adjusted value (post nibble): 0056
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0053
Lane 05 nibble 0 adjusted value (pre nibble): 0053
Lane 05 nibble 0 adjusted value (post nibble): 0053
Lane 06 nibble 0 raw readback: 001f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0041
Lane 08 nibble 0 adjusted value (pre nibble): 0041
Lane 08 nibble 0 adjusted value (post nibble): 0041
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 24000
TrainDQSReceiverEnCyc: ErrStatus 24000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

DQSTiming_D: Restarting training on algorithm request
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0004
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
AutoCycTiming_D: Start
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2205
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0042
Lane 00 nibble 0 adjusted value (pre nibble): 0042
Lane 00 nibble 0 adjusted value (post nibble): 0042
Lane 01 nibble 0 raw readback: 0040
Lane 01 nibble 0 adjusted value (pre nibble): 0040
Lane 01 nibble 0 adjusted value (post nibble): 0040
Lane 02 nibble 0 raw readback: 003c
Lane 02 nibble 0 adjusted value (pre nibble): 003c
Lane 02 nibble 0 adjusted value (post nibble): 003c
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0041
Lane 06 nibble 0 adjusted value (pre nibble): 0041
Lane 06 nibble 0 adjusted value (post nibble): 0041
Lane 07 nibble 0 raw readback: 0044
Lane 07 nibble 0 adjusted value (pre nibble): 0044
Lane 07 nibble 0 adjusted value (post nibble): 0044
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0047
Lane 00 nibble 0 adjusted value (pre nibble): 0047
Lane 00 nibble 0 adjusted value (post nibble): 0047
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 003f
Lane 02 nibble 0 adjusted value (pre nibble): 003f
Lane 02 nibble 0 adjusted value (post nibble): 003f
Lane 03 nibble 0 raw readback: 003b
Lane 03 nibble 0 adjusted value (pre nibble): 003b
Lane 03 nibble 0 adjusted value (post nibble): 003b
Lane 04 nibble 0 raw readback: 0038
Lane 04 nibble 0 adjusted value (pre nibble): 0038
Lane 04 nibble 0 adjusted value (post nibble): 0038
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0046
Lane 06 nibble 0 adjusted value (pre nibble): 0046
Lane 06 nibble 0 adjusted value (post nibble): 0046
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0053
Lane 00 new seed: 0053
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 0049
Lane 02 new seed: 0049
Lane 03 scaled delay: 0043
Lane 03 new seed: 0043
Lane 04 scaled delay: 003f
Lane 04 new seed: 003f
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 0052
Lane 06 new seed: 0052
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0057
Lane 00 nibble 0 adjusted value (pre nibble): 0057
Lane 00 nibble 0 adjusted value (post nibble): 0057
Lane 01 nibble 0 raw readback: 0053
Lane 01 nibble 0 adjusted value (pre nibble): 0053
Lane 01 nibble 0 adjusted value (post nibble): 0053
Lane 02 nibble 0 raw readback: 004d
Lane 02 nibble 0 adjusted value (pre nibble): 004d
Lane 02 nibble 0 adjusted value (post nibble): 004d
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0042
Lane 04 nibble 0 adjusted value (pre nibble): 0042
Lane 04 nibble 0 adjusted value (post nibble): 0042
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0054
Lane 06 nibble 0 adjusted value (pre nibble): 0054
Lane 06 nibble 0 adjusted value (post nibble): 0054
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003c
Lane 08 nibble 0 adjusted value (pre nibble): 003c
Lane 08 nibble 0 adjusted value (post nibble): 003c
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0064
Lane 00 new seed: 0064
Lane 01 scaled delay: 005f
Lane 01 new seed: 005f
Lane 02 scaled delay: 0058
Lane 02 new seed: 0058
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 004a
Lane 04 new seed: 004a
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 0061
Lane 06 new seed: 0061
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0043
Lane 08 new seed: 0043
Lane 00 nibble 0 raw readback: 0021
Lane 00 nibble 0 adjusted value (pre nibble): 0061
Lane 00 nibble 0 adjusted value (post nibble): 0061
Lane 01 nibble 0 raw readback: 005d
Lane 01 nibble 0 adjusted value (pre nibble): 005d
Lane 01 nibble 0 adjusted value (post nibble): 005d
Lane 02 nibble 0 raw readback: 0055
Lane 02 nibble 0 adjusted value (pre nibble): 0055
Lane 02 nibble 0 adjusted value (post nibble): 0055
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0052
Lane 05 nibble 0 adjusted value (pre nibble): 0052
Lane 05 nibble 0 adjusted value (post nibble): 0052
Lane 06 nibble 0 raw readback: 001e
Lane 06 nibble 0 adjusted value (pre nibble): 005e
Lane 06 nibble 0 adjusted value (post nibble): 005e
Lane 07 nibble 0 raw readback: 0024
Lane 07 nibble 0 adjusted value (pre nibble): 0064
Lane 07 nibble 0 adjusted value (post nibble): 0064
Lane 08 nibble 0 raw readback: 0040
Lane 08 nibble 0 adjusted value (pre nibble): 0040
Lane 08 nibble 0 adjusted value (post nibble): 0040
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted
TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 44000
TrainDQSReceiverEnCyc: ErrStatus 44000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

DIMM training FAILED! Restarting system...soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de00 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01stopped
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02stopped
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03stopped
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04stopped
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05stopped

fill_mem_ctrl() detected 1 nodes
raminit_amdmct()
raminit_amdmct begin:
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_preInitDCT
DIMMPresence: DIMMValid=4
DIMMPresence: DIMMPresent=4
DIMMPresence: RegDIMMPresent=4
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=4
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=4
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=4
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done

DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
mctAutoInitMCT_D: DIMMSetVoltage
Node 00 DIMM voltage set to index 01
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 5
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3ffffff BottomIO: c00000
Node: 00 base: 03 limit: 43fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0042
Lane 00 nibble 0 adjusted value (pre nibble): 0042
Lane 00 nibble 0 adjusted value (post nibble): 0042
Lane 01 nibble 0 raw readback: 0040
Lane 01 nibble 0 adjusted value (pre nibble): 0040
Lane 01 nibble 0 adjusted value (post nibble): 0040
Lane 02 nibble 0 raw readback: 003b
Lane 02 nibble 0 adjusted value (pre nibble): 003b
Lane 02 nibble 0 adjusted value (post nibble): 003b
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0041
Lane 06 nibble 0 adjusted value (pre nibble): 0041
Lane 06 nibble 0 adjusted value (post nibble): 0041
Lane 07 nibble 0 raw readback: 0044
Lane 07 nibble 0 adjusted value (pre nibble): 0044
Lane 07 nibble 0 adjusted value (post nibble): 0044
Lane 08 nibble 0 raw readback: 0030
Lane 08 nibble 0 adjusted value (pre nibble): 0030
Lane 08 nibble 0 adjusted value (post nibble): 0030
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0047
Lane 00 nibble 0 adjusted value (pre nibble): 0047
Lane 00 nibble 0 adjusted value (post nibble): 0047
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 0040
Lane 02 nibble 0 adjusted value (pre nibble): 0040
Lane 02 nibble 0 adjusted value (post nibble): 0040
Lane 03 nibble 0 raw readback: 003b
Lane 03 nibble 0 adjusted value (pre nibble): 003b
Lane 03 nibble 0 adjusted value (post nibble): 003b
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0046
Lane 06 nibble 0 adjusted value (pre nibble): 0046
Lane 06 nibble 0 adjusted value (post nibble): 0046
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0053
Lane 00 new seed: 0053
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 004a
Lane 02 new seed: 004a
Lane 03 scaled delay: 0043
Lane 03 new seed: 0043
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 0052
Lane 06 new seed: 0052
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0053
Lane 01 nibble 0 adjusted value (pre nibble): 0053
Lane 01 nibble 0 adjusted value (post nibble): 0053
Lane 02 nibble 0 raw readback: 004c
Lane 02 nibble 0 adjusted value (pre nibble): 004c
Lane 02 nibble 0 adjusted value (post nibble): 004c
Lane 03 nibble 0 raw readback: 0046
Lane 03 nibble 0 adjusted value (pre nibble): 0046
Lane 03 nibble 0 adjusted value (post nibble): 0046
Lane 04 nibble 0 raw readback: 0042
Lane 04 nibble 0 adjusted value (pre nibble): 0042
Lane 04 nibble 0 adjusted value (post nibble): 0042
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0054
Lane 06 nibble 0 adjusted value (pre nibble): 0054
Lane 06 nibble 0 adjusted value (post nibble): 0054
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003c
Lane 08 nibble 0 adjusted value (pre nibble): 003c
Lane 08 nibble 0 adjusted value (post nibble): 003c
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005f
Lane 01 new seed: 005f
Lane 02 scaled delay: 0057
Lane 02 new seed: 0057
Lane 03 scaled delay: 004f
Lane 03 new seed: 004f
Lane 04 scaled delay: 004a
Lane 04 new seed: 004a
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 0061
Lane 06 new seed: 0061
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0043
Lane 08 new seed: 0043
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005e
Lane 01 nibble 0 adjusted value (pre nibble): 005e
Lane 01 nibble 0 adjusted value (post nibble): 005e
Lane 02 nibble 0 raw readback: 0056
Lane 02 nibble 0 adjusted value (pre nibble): 0056
Lane 02 nibble 0 adjusted value (post nibble): 0056
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0053
Lane 05 nibble 0 adjusted value (pre nibble): 0053
Lane 05 nibble 0 adjusted value (post nibble): 0053
Lane 06 nibble 0 raw readback: 001f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0041
Lane 08 nibble 0 adjusted value (pre nibble): 0041
Lane 08 nibble 0 adjusted value (post nibble): 0041
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 24000
TrainDQSReceiverEnCyc: ErrStatus 24000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

DQSTiming_D: Restarting training on algorithm request
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0004
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
AutoCycTiming_D: Start
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2205
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0041
Lane 00 nibble 0 adjusted value (pre nibble): 0041
Lane 00 nibble 0 adjusted value (post nibble): 0041
Lane 01 nibble 0 raw readback: 0040
Lane 01 nibble 0 adjusted value (pre nibble): 0040
Lane 01 nibble 0 adjusted value (post nibble): 0040
Lane 02 nibble 0 raw readback: 003b
Lane 02 nibble 0 adjusted value (pre nibble): 003b
Lane 02 nibble 0 adjusted value (post nibble): 003b
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0040
Lane 06 nibble 0 adjusted value (pre nibble): 0040
Lane 06 nibble 0 adjusted value (post nibble): 0040
Lane 07 nibble 0 raw readback: 0043
Lane 07 nibble 0 adjusted value (pre nibble): 0043
Lane 07 nibble 0 adjusted value (post nibble): 0043
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0048
Lane 00 nibble 0 adjusted value (pre nibble): 0048
Lane 00 nibble 0 adjusted value (post nibble): 0048
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 0040
Lane 02 nibble 0 adjusted value (pre nibble): 0040
Lane 02 nibble 0 adjusted value (post nibble): 0040
Lane 03 nibble 0 raw readback: 003c
Lane 03 nibble 0 adjusted value (pre nibble): 003c
Lane 03 nibble 0 adjusted value (post nibble): 003c
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0046
Lane 06 nibble 0 adjusted value (pre nibble): 0046
Lane 06 nibble 0 adjusted value (post nibble): 0046
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0055
Lane 00 new seed: 0055
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 004a
Lane 02 new seed: 004a
Lane 03 scaled delay: 0045
Lane 03 new seed: 0045
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 0052
Lane 06 new seed: 0052
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0052
Lane 01 nibble 0 adjusted value (pre nibble): 0052
Lane 01 nibble 0 adjusted value (post nibble): 0052
Lane 02 nibble 0 raw readback: 004b
Lane 02 nibble 0 adjusted value (pre nibble): 004b
Lane 02 nibble 0 adjusted value (post nibble): 004b
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0041
Lane 04 nibble 0 adjusted value (pre nibble): 0041
Lane 04 nibble 0 adjusted value (post nibble): 0041
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0053
Lane 06 nibble 0 adjusted value (pre nibble): 0053
Lane 06 nibble 0 adjusted value (post nibble): 0053
Lane 07 nibble 0 raw readback: 0058
Lane 07 nibble 0 adjusted value (pre nibble): 0058
Lane 07 nibble 0 adjusted value (post nibble): 0058
Lane 08 nibble 0 raw readback: 003b
Lane 08 nibble 0 adjusted value (pre nibble): 003b
Lane 08 nibble 0 adjusted value (post nibble): 003b
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005e
Lane 01 new seed: 005e
Lane 02 scaled delay: 0055
Lane 02 new seed: 0055
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 0049
Lane 04 new seed: 0049
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 005f
Lane 06 new seed: 005f
Lane 07 scaled delay: 0066
Lane 07 new seed: 0066
Lane 08 scaled delay: 0041
Lane 08 new seed: 0041
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005d
Lane 01 nibble 0 adjusted value (pre nibble): 005d
Lane 01 nibble 0 adjusted value (post nibble): 005d
Lane 02 nibble 0 raw readback: 0055
Lane 02 nibble 0 adjusted value (pre nibble): 0055
Lane 02 nibble 0 adjusted value (post nibble): 0055
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0053
Lane 05 nibble 0 adjusted value (pre nibble): 0053
Lane 05 nibble 0 adjusted value (post nibble): 0053
Lane 06 nibble 0 raw readback: 005f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0041
Lane 08 nibble 0 adjusted value (pre nibble): 0041
Lane 08 nibble 0 adjusted value (post nibble): 0041
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted
TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 44000
TrainDQSReceiverEnCyc: ErrStatus 44000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

DIMM training FAILED! Restarting system...soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de00 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01stopped
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02stopped
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03stopped
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04stopped
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05stopped

fill_mem_ctrl() detected 1 nodes
raminit_amdmct()
raminit_amdmct begin:
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_preInitDCT
DIMMPresence: DIMMValid=4
DIMMPresence: DIMMPresent=4
DIMMPresence: RegDIMMPresent=4
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=4
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=4
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=4
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done

DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
mctAutoInitMCT_D: DIMMSetVoltage
Node 00 DIMM voltage set to index 01
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 5
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3ffffff BottomIO: c00000
Node: 00 base: 03 limit: 43fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0042
Lane 00 nibble 0 adjusted value (pre nibble): 0042
Lane 00 nibble 0 adjusted value (post nibble): 0042
Lane 01 nibble 0 raw readback: 0040
Lane 01 nibble 0 adjusted value (pre nibble): 0040
Lane 01 nibble 0 adjusted value (post nibble): 0040
Lane 02 nibble 0 raw readback: 003c
Lane 02 nibble 0 adjusted value (pre nibble): 003c
Lane 02 nibble 0 adjusted value (post nibble): 003c
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0041
Lane 06 nibble 0 adjusted value (pre nibble): 0041
Lane 06 nibble 0 adjusted value (post nibble): 0041
Lane 07 nibble 0 raw readback: 0043
Lane 07 nibble 0 adjusted value (pre nibble): 0043
Lane 07 nibble 0 adjusted value (post nibble): 0043
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0048
Lane 00 nibble 0 adjusted value (pre nibble): 0048
Lane 00 nibble 0 adjusted value (post nibble): 0048
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 0040
Lane 02 nibble 0 adjusted value (pre nibble): 0040
Lane 02 nibble 0 adjusted value (post nibble): 0040
Lane 03 nibble 0 raw readback: 003b
Lane 03 nibble 0 adjusted value (pre nibble): 003b
Lane 03 nibble 0 adjusted value (post nibble): 003b
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0046
Lane 06 nibble 0 adjusted value (pre nibble): 0046
Lane 06 nibble 0 adjusted value (post nibble): 0046
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0055
Lane 00 new seed: 0055
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 004a
Lane 02 new seed: 004a
Lane 03 scaled delay: 0043
Lane 03 new seed: 0043
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 0052
Lane 06 new seed: 0052
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0052
Lane 01 nibble 0 adjusted value (pre nibble): 0052
Lane 01 nibble 0 adjusted value (post nibble): 0052
Lane 02 nibble 0 raw readback: 004c
Lane 02 nibble 0 adjusted value (pre nibble): 004c
Lane 02 nibble 0 adjusted value (post nibble): 004c
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0041
Lane 04 nibble 0 adjusted value (pre nibble): 0041
Lane 04 nibble 0 adjusted value (post nibble): 0041
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0054
Lane 06 nibble 0 adjusted value (pre nibble): 0054
Lane 06 nibble 0 adjusted value (post nibble): 0054
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003b
Lane 08 nibble 0 adjusted value (pre nibble): 003b
Lane 08 nibble 0 adjusted value (post nibble): 003b
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005e
Lane 01 new seed: 005e
Lane 02 scaled delay: 0057
Lane 02 new seed: 0057
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 0049
Lane 04 new seed: 0049
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 0061
Lane 06 new seed: 0061
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0041
Lane 08 new seed: 0041
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005d
Lane 01 nibble 0 adjusted value (pre nibble): 005d
Lane 01 nibble 0 adjusted value (post nibble): 005d
Lane 02 nibble 0 raw readback: 0055
Lane 02 nibble 0 adjusted value (pre nibble): 0055
Lane 02 nibble 0 adjusted value (post nibble): 0055
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0053
Lane 05 nibble 0 adjusted value (pre nibble): 0053
Lane 05 nibble 0 adjusted value (post nibble): 0053
Lane 06 nibble 0 raw readback: 001f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0041
Lane 08 nibble 0 adjusted value (pre nibble): 0041
Lane 08 nibble 0 adjusted value (post nibble): 0041
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 24000
TrainDQSReceiverEnCyc: ErrStatus 24000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

DQSTiming_D: Restarting training on algorithm request
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0004
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
AutoCycTiming_D: Start
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2205
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0041
Lane 00 nibble 0 adjusted value (pre nibble): 0041
Lane 00 nibble 0 adjusted value (post nibble): 0041
Lane 01 nibble 0 raw readback: 003f
Lane 01 nibble 0 adjusted value (pre nibble): 003f
Lane 01 nibble 0 adjusted value (post nibble): 003f
Lane 02 nibble 0 raw readback: 003b
Lane 02 nibble 0 adjusted value (pre nibble): 003b
Lane 02 nibble 0 adjusted value (post nibble): 003b
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0040
Lane 06 nibble 0 adjusted value (pre nibble): 0040
Lane 06 nibble 0 adjusted value (post nibble): 0040
Lane 07 nibble 0 raw readback: 0043
Lane 07 nibble 0 adjusted value (pre nibble): 0043
Lane 07 nibble 0 adjusted value (post nibble): 0043
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0048
Lane 00 nibble 0 adjusted value (pre nibble): 0048
Lane 00 nibble 0 adjusted value (post nibble): 0048
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 0040
Lane 02 nibble 0 adjusted value (pre nibble): 0040
Lane 02 nibble 0 adjusted value (post nibble): 0040
Lane 03 nibble 0 raw readback: 003b
Lane 03 nibble 0 adjusted value (pre nibble): 003b
Lane 03 nibble 0 adjusted value (post nibble): 003b
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0047
Lane 06 nibble 0 adjusted value (pre nibble): 0047
Lane 06 nibble 0 adjusted value (post nibble): 0047
Lane 07 nibble 0 raw readback: 004a
Lane 07 nibble 0 adjusted value (pre nibble): 004a
Lane 07 nibble 0 adjusted value (post nibble): 004a
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0055
Lane 00 new seed: 0055
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 004a
Lane 02 new seed: 004a
Lane 03 scaled delay: 0043
Lane 03 new seed: 0043
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 0053
Lane 06 new seed: 0053
Lane 07 scaled delay: 0057
Lane 07 new seed: 0057
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0053
Lane 01 nibble 0 adjusted value (pre nibble): 0053
Lane 01 nibble 0 adjusted value (post nibble): 0053
Lane 02 nibble 0 raw readback: 004c
Lane 02 nibble 0 adjusted value (pre nibble): 004c
Lane 02 nibble 0 adjusted value (post nibble): 004c
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0041
Lane 04 nibble 0 adjusted value (pre nibble): 0041
Lane 04 nibble 0 adjusted value (post nibble): 0041
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0054
Lane 06 nibble 0 adjusted value (pre nibble): 0054
Lane 06 nibble 0 adjusted value (post nibble): 0054
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003b
Lane 08 nibble 0 adjusted value (pre nibble): 003b
Lane 08 nibble 0 adjusted value (post nibble): 003b
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005f
Lane 01 new seed: 005f
Lane 02 scaled delay: 0057
Lane 02 new seed: 0057
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 0049
Lane 04 new seed: 0049
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 0061
Lane 06 new seed: 0061
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0041
Lane 08 new seed: 0041
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005e
Lane 01 nibble 0 adjusted value (pre nibble): 005e
Lane 01 nibble 0 adjusted value (post nibble): 005e
Lane 02 nibble 0 raw readback: 0055
Lane 02 nibble 0 adjusted value (pre nibble): 0055
Lane 02 nibble 0 adjusted value (post nibble): 0055
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0052
Lane 05 nibble 0 adjusted value (pre nibble): 0052
Lane 05 nibble 0 adjusted value (post nibble): 0052
Lane 06 nibble 0 raw readback: 001f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0041
Lane 08 nibble 0 adjusted value (pre nibble): 0041
Lane 08 nibble 0 adjusted value (post nibble): 0041
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted
TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 44000
TrainDQSReceiverEnCyc: ErrStatus 44000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done

DIMM training FAILED! Restarting system...soft_reset() called!


coreboot-4.6-2479-g8e4384d Mon Dec 25 14:44:35 UTC 2017 romstage starting...
Initial stack pointer: 000dffc8
CPU APICID 00 start flag set
BSP Family_Model: 00600f12
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset 666c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset 2de00 size 1ec4
[microcode] patch id to apply = 0x0600063d
[microcode] updated to patch id = 0x0600063d success
cpuSetAMDMSR done
Enter amd_ht_init
Forcing HT links to isochronous mode due to enabled IOMMU
Exit amd_ht_init
amd_ht_fixup
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f21
F3xD8: 03000016
F3xDC: 05475634
core0 started:
sr5650_early_setup()
get_cpu_rev EAX=0x600f12.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
Enabling IOMMU
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 05 pass 1
Start other core - nodeid: 00 cores: 05
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started


Begin FIDVID MSR 0xc0010071 0x5aca009e 0x38023411
End FIDVIDMSR 0xc0010071 0x5aca009e 0x38023411
sr5650_htinit: Node 0 Link 2, HT freq=e.
sr5650_htinit: HT3 mode
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01stopped
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02stopped
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03stopped
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04stopped
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05stopped

fill_mem_ctrl() detected 1 nodes
raminit_amdmct()
raminit_amdmct begin:
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_preInitDCT
DIMMPresence: DIMMValid=4
DIMMPresence: DIMMPresent=4
DIMMPresence: RegDIMMPresent=4
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=4
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=4
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=4
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done

DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fec0 size 10000
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
mctAutoInitMCT_D: DIMMSetVoltage
Node 00 DIMM voltage set to index 01
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 5
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3ffffff BottomIO: c00000
Node: 00 base: 03 limit: 43fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 003e
Lane 01 initial seed: 003e
Lane 02 initial seed: 003e
Lane 03 initial seed: 003e
Lane 04 initial seed: 003e
Lane 05 initial seed: 003e
Lane 06 initial seed: 003e
Lane 07 initial seed: 003e
Lane 08 initial seed: 003e
Lane 00 nibble 0 raw readback: 0041
Lane 00 nibble 0 adjusted value (pre nibble): 0041
Lane 00 nibble 0 adjusted value (post nibble): 0041
Lane 01 nibble 0 raw readback: 003f
Lane 01 nibble 0 adjusted value (pre nibble): 003f
Lane 01 nibble 0 adjusted value (post nibble): 003f
Lane 02 nibble 0 raw readback: 003c
Lane 02 nibble 0 adjusted value (pre nibble): 003c
Lane 02 nibble 0 adjusted value (post nibble): 003c
Lane 03 nibble 0 raw readback: 0037
Lane 03 nibble 0 adjusted value (pre nibble): 0037
Lane 03 nibble 0 adjusted value (post nibble): 0037
Lane 04 nibble 0 raw readback: 0035
Lane 04 nibble 0 adjusted value (pre nibble): 0035
Lane 04 nibble 0 adjusted value (post nibble): 0035
Lane 05 nibble 0 raw readback: 003a
Lane 05 nibble 0 adjusted value (pre nibble): 003a
Lane 05 nibble 0 adjusted value (post nibble): 003a
Lane 06 nibble 0 raw readback: 0040
Lane 06 nibble 0 adjusted value (pre nibble): 0040
Lane 06 nibble 0 adjusted value (post nibble): 0040
Lane 07 nibble 0 raw readback: 0043
Lane 07 nibble 0 adjusted value (pre nibble): 0043
Lane 07 nibble 0 adjusted value (post nibble): 0043
Lane 08 nibble 0 raw readback: 0031
Lane 08 nibble 0 adjusted value (pre nibble): 0031
Lane 08 nibble 0 adjusted value (post nibble): 0031
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601558
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0044
Lane 00 new seed: 0044
Lane 01 scaled delay: 0044
Lane 01 new seed: 0044
Lane 02 scaled delay: 0044
Lane 02 new seed: 0044
Lane 03 scaled delay: 0044
Lane 03 new seed: 0044
Lane 04 scaled delay: 0044
Lane 04 new seed: 0044
Lane 05 scaled delay: 0044
Lane 05 new seed: 0044
Lane 06 scaled delay: 0044
Lane 06 new seed: 0044
Lane 07 scaled delay: 0044
Lane 07 new seed: 0044
Lane 08 scaled delay: 0044
Lane 08 new seed: 0044
Lane 00 nibble 0 raw readback: 0048
Lane 00 nibble 0 adjusted value (pre nibble): 0048
Lane 00 nibble 0 adjusted value (post nibble): 0048
Lane 01 nibble 0 raw readback: 0045
Lane 01 nibble 0 adjusted value (pre nibble): 0045
Lane 01 nibble 0 adjusted value (post nibble): 0045
Lane 02 nibble 0 raw readback: 0041
Lane 02 nibble 0 adjusted value (pre nibble): 0041
Lane 02 nibble 0 adjusted value (post nibble): 0041
Lane 03 nibble 0 raw readback: 003b
Lane 03 nibble 0 adjusted value (pre nibble): 003b
Lane 03 nibble 0 adjusted value (post nibble): 003b
Lane 04 nibble 0 raw readback: 0039
Lane 04 nibble 0 adjusted value (pre nibble): 0039
Lane 04 nibble 0 adjusted value (post nibble): 0039
Lane 05 nibble 0 raw readback: 0040
Lane 05 nibble 0 adjusted value (pre nibble): 0040
Lane 05 nibble 0 adjusted value (post nibble): 0040
Lane 06 nibble 0 raw readback: 0047
Lane 06 nibble 0 adjusted value (pre nibble): 0047
Lane 06 nibble 0 adjusted value (post nibble): 0047
Lane 07 nibble 0 raw readback: 004b
Lane 07 nibble 0 adjusted value (pre nibble): 004b
Lane 07 nibble 0 adjusted value (post nibble): 004b
Lane 08 nibble 0 raw readback: 0035
Lane 08 nibble 0 adjusted value (pre nibble): 0035
Lane 08 nibble 0 adjusted value (post nibble): 0035
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601958
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0055
Lane 00 new seed: 0055
Lane 01 scaled delay: 0051
Lane 01 new seed: 0051
Lane 02 scaled delay: 004b
Lane 02 new seed: 004b
Lane 03 scaled delay: 0043
Lane 03 new seed: 0043
Lane 04 scaled delay: 0041
Lane 04 new seed: 0041
Lane 05 scaled delay: 004a
Lane 05 new seed: 004a
Lane 06 scaled delay: 0053
Lane 06 new seed: 0053
Lane 07 scaled delay: 0059
Lane 07 new seed: 0059
Lane 08 scaled delay: 003b
Lane 08 new seed: 003b
Lane 00 nibble 0 raw readback: 0056
Lane 00 nibble 0 adjusted value (pre nibble): 0056
Lane 00 nibble 0 adjusted value (post nibble): 0056
Lane 01 nibble 0 raw readback: 0053
Lane 01 nibble 0 adjusted value (pre nibble): 0053
Lane 01 nibble 0 adjusted value (post nibble): 0053
Lane 02 nibble 0 raw readback: 004c
Lane 02 nibble 0 adjusted value (pre nibble): 004c
Lane 02 nibble 0 adjusted value (post nibble): 004c
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 0042
Lane 04 nibble 0 adjusted value (pre nibble): 0042
Lane 04 nibble 0 adjusted value (post nibble): 0042
Lane 05 nibble 0 raw readback: 004a
Lane 05 nibble 0 adjusted value (pre nibble): 004a
Lane 05 nibble 0 adjusted value (post nibble): 004a
Lane 06 nibble 0 raw readback: 0054
Lane 06 nibble 0 adjusted value (pre nibble): 0054
Lane 06 nibble 0 adjusted value (post nibble): 0054
Lane 07 nibble 0 raw readback: 0059
Lane 07 nibble 0 adjusted value (pre nibble): 0059
Lane 07 nibble 0 adjusted value (post nibble): 0059
Lane 08 nibble 0 raw readback: 003c
Lane 08 nibble 0 adjusted value (pre nibble): 003c
Lane 08 nibble 0 adjusted value (post nibble): 003c
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 0
phyAssistedMemFnceTraining: done training node 0 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 00000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b58
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0063
Lane 00 new seed: 0063
Lane 01 scaled delay: 005f
Lane 01 new seed: 005f
Lane 02 scaled delay: 0057
Lane 02 new seed: 0057
Lane 03 scaled delay: 004e
Lane 03 new seed: 004e
Lane 04 scaled delay: 004a
Lane 04 new seed: 004a
Lane 05 scaled delay: 0054
Lane 05 new seed: 0054
Lane 06 scaled delay: 0061
Lane 06 new seed: 0061
Lane 07 scaled delay: 0067
Lane 07 new seed: 0067
Lane 08 scaled delay: 0043
Lane 08 new seed: 0043
Lane 00 nibble 0 raw readback: 0022
Lane 00 nibble 0 adjusted value (pre nibble): 0062
Lane 00 nibble 0 adjusted value (post nibble): 0062
Lane 01 nibble 0 raw readback: 005d
Lane 01 nibble 0 adjusted value (pre nibble): 005d
Lane 01 nibble 0 adjusted value (post nibble): 005d
Lane 02 nibble 0 raw readback: 0055
Lane 02 nibble 0 adjusted value (pre nibble): 0055
Lane 02 nibble 0 adjusted value (post nibble): 0055
Lane 03 nibble 0 raw readback: 004d
Lane 03 nibble 0 adjusted value (pre nibble): 004d
Lane 03 nibble 0 adjusted value (post nibble): 004d
Lane 04 nibble 0 raw readback: 0048
Lane 04 nibble 0 adjusted value (pre nibble): 0048
Lane 04 nibble 0 adjusted value (post nibble): 0048
Lane 05 nibble 0 raw readback: 0053
Lane 05 nibble 0 adjusted value (pre nibble): 0053
Lane 05 nibble 0 adjusted value (post nibble): 0053
Lane 06 nibble 0 raw readback: 001f
Lane 06 nibble 0 adjusted value (pre nibble): 005f
Lane 06 nibble 0 adjusted value (post nibble): 005f
Lane 07 nibble 0 raw readback: 0025
Lane 07 nibble 0 adjusted value (pre nibble): 0065
Lane 07 nibble 0 adjusted value (post nibble): 0065
Lane 08 nibble 0 raw readback: 0041
Lane 08 nibble 0 adjusted value (pre nibble): 0041
Lane 08 nibble 0 adjusted value (post nibble): 0041
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

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