MD Matt DeVillier
- Login: matt.devillier
- Email: matt.devillier@gmail.com
- Registered on: 07/23/2016
- Last sign in: 12/12/2025
Issues
| open | closed | Total | |
|---|---|---|---|
| Assigned issues | 0 | 2 | 2 |
| Reported issues | 2 | 4 | 6 |
Projects
| Project | Roles | Registered on |
|---|---|---|
| coreboot | Manager, Developer | 06/07/2017 |
| flashrom | Developer | 12/13/2024 |
Activity
12/10/2025
- MD 05:06 PM coreboot Bug #619: Lenovo T480s headphone jack detection is inconsistent - fix for T480 can be applied.
- fix pushed: https://review.coreboot.org/c/coreboot/+/90450
12/09/2025
- MD 11:19 PM coreboot Bug #619: Lenovo T480s headphone jack detection is inconsistent - fix for T480 can be applied.
- curious - any reason you didn't just apply the change and push the fix yourself?
11/18/2025
- MD 12:03 AM coreboot Bug #617: Missing safeguard: CBFS_SIZE greater than BIOS region in the IFD
- gaspar ilom wrote in #note-4:
> cat ./build/x86/coreboot-25.09/EOL_w541-maximized/fmap.fmd
> ...
there's something odd going on here, since the generated FMAP should have the IFD, ME, and GBE regions listed if you are including those b...
10/18/2025
- MD 09:50 PM coreboot Bug #612: coreboot blocks PCIe root port: reg_script_run_step / P.m CAP (Baytrail)
> After searching for `reg_script_run` I edited line 182 and 186 `dev->enabled = 0;` to `dev->enabled = 1;`. Now in the OS the 4 Rootports 1c.0-3 are listed with `lspci` and miniPCIe 1c.2 intel wifi works again and is correctly listed ...- MD 04:18 PM coreboot Bug #612: coreboot blocks PCIe root port: reg_script_run_step / P.m CAP (Baytrail)
- Walter Sonius wrote in #note-3:
> Thanks for the comprehensive report, a fraction can be understood where Bus 01 claims a unlimited big space while it overlaps with part of Bus 00 already claimed MMIO space.
> ...
for some reason Linux... - MD 12:16 AM coreboot Bug #612: coreboot blocks PCIe root port: reg_script_run_step / P.m CAP (Baytrail)
- Walter Sonius wrote in #note-1:
> Current Baytrail missing MMIO window below 4GB [patch](https://review.coreboot.org/c/coreboot/+/89589) has a contradicting effect on the ZBOX because it disables the only working (mini)PCIe rootport so ... - MD 02:05 AM coreboot Bug #611 (Resolved): I2C Controllers fail to initialize under Win11 with top-down allocation on pre-FSP 2.0 platforms
10/16/2025
- MD 05:38 PM coreboot Bug #611 (In Progress): I2C Controllers fail to initialize under Win11 with top-down allocation on pre-FSP 2.0 platforms
- issue was coreboot's missing ACPI MMIO windows for a few platforms. patches pushed to resolve the issue:
https://review.coreboot.org/c/coreboot/+/89588
https://review.coreboot.org/c/coreboot/+/89589
https://review.coreboot.org/c/cor...
10/13/2025
- MD 10:16 PM coreboot Bug #611: I2C Controllers fail to initialize under Win11 with top-down allocation on pre-FSP 2.0 platforms
- I think I've found the issue actually: pre-Skylake Intel platforms all define their MMIO ranges statically in ASL, and have a single window defined. That works fine for bottom-up allocation, but not for top-down, where there are two Wind...
- MD 05:17 PM coreboot Bug #611: I2C Controllers fail to initialize under Win11 with top-down allocation on pre-FSP 2.0 platforms
- Walter Sonius wrote in #note-3:
> Related patch: [CB:89464](https://review.coreboot.org/c/coreboot/+/89464) device/Kconfig: Disable top-down resource allocation for pre-FSP 2.0
> ...
I would use:
```
CONFIG_EDK2_CBMEM_LOGGING=y
CONF...