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Support #534

Updated by Mahesh Kilumu 8 months ago

Hi, With respect to the Alderlake-P RVP platform designed Custom Board. 
 i have been trying to implement the Ethernet(LAN) on my Custom Board. on RVP intel team used GBE PHY but on my custom board we have used the External Realtek RTL8111H controller over PCIe Root port7 for Ethernet.  

 Below are the configuration details: 
 1) Devicetree.cb:  
  device ref pcie_rp7 on end 
                  # Enable PCH PCIE RP 7 using CLK 6 
                  register "pch_pcie_rp[PCH_RP(7)]" = "{ 
                 .clk_src = 6, 
                 .clk_req = 6, 
                 .flags = PCIE_CLK_LAN 
         }" 

 
 2) gpio.c: 
         /* 19: PCIE SRCCLKREQ6- same as RVP */ 
         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), 
         /* 2: GPD_2_LAN_WAKE_N- same as RVP*/ 
         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),     
         /* 21 : LAN_ISOLATE# -New Implementation */ 
         PAD_CFG_GPO(GPP_A21, 1, DEEP), 

 from the logs observed that, 
 Root port got enabled ->> [SPEW ]    PCI: 00:00:1c.6: enabled 1 

 But observed the few Error & warnings in the log with respect to the above configuration 
 [WARN ]    Missing root port clock structure definition 
 [ERROR]    PCI: 00:00:1c.6 missing read_resources 

 full log details :  
 https://pastebin.com/zWcsEZvL

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