Issue Tracker: Issueshttps://ticket.coreboot.org/https://ticket.coreboot.org/themes/PurpleMine2-2.16.2/favicon/favicon.ico?12024-03-01T21:31:08ZIssue Tracker
Redmine coreboot - Bug #528 (New): Building `emulation/qemu-i440fx` with `CONFIG_CBFS_VERIFICATION=y` failshttps://ticket.coreboot.org/issues/5282024-03-01T21:31:08ZPaul Menzelpmenzel+ticket.coreboot@molgen.mpg.de
<p>Building a coreboot image for <code>emulation/qemu-i440fx</code> with <code>CONFIG_CBFS_VERIFICATION=y</code> fails.</p>
<pre><code>$ git log --oneline --no-decorate -1
ff2d863515 drivers/intel/gma: Allow SPARK function with side effects
$ make savedefconfig
$ more defconfig
CONFIG_ANY_TOOLCHAIN=y
# CONFIG_SEPARATE_ROMSTAGE is not set
CONFIG_TIMESTAMPS_ON_CONSOLE=y
# CONFIG_USE_BLOBS is not set
CONFIG_NO_POST=y
CONFIG_USE_EXP_X86_64_SUPPORT=y
# CONFIG_PCI_ALLOW_BUS_MASTER is not set
CONFIG_CBFS_VERIFICATION=y
CONFIG_CONSOLE_SERIAL_921600=y
# CONFIG_CONSOLE_QEMU_DEBUGCON is not set
CONFIG_PAYLOAD_FILO=y
CONFIG_FILO_HEAD=y
CONFIG_FILO_USE_AUTOBOOT=y
CONFIG_FILO_AUTOBOOT_FILE="hda1:/vmlinuz initrd=hda1:/initrd.img root=/dev/sda1 ro quiet"
$ make -j4
[…]
CC ramstage/arch/x86/boot.o
CC ramstage/arch/x86/breakpoint.o
LINK cbfs/fallback/postcar.debug
LINK cbfs/fallback/bootblock.debug
x86_64-linux-gnu-ld.bfd: warning: build/postcar/mainboard/emulation/qemu-i440fx/exit_car.o: missing .note.GNU-stack section implies executable stack
x86_64-linux-gnu-ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
x86_64-linux-gnu-ld.bfd: warning: build/cbfs/fallback/postcar.debug has a LOAD segment with RWX permissions
HOSTCC cbfstool/ifittool (link)
HOSTCC cbfstool/ifwitool (link)
HOSTCC cbfstool/cse_fpt (link)
x86_64-linux-gnu-ld.bfd: warning: build/bootblock/cpu/x86/reset16.o: missing .note.GNU-stack section implies executable stack
x86_64-linux-gnu-ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
x86_64-linux-gnu-ld.bfd: warning: build/cbfs/fallback/bootblock.debug has a LOAD segment with RWX permissions
x86_64-linux-gnu-ld.bfd: build/bootblock/cpu/qemu-x86/cache_as_ram_bootblock.o: in function `cache_as_ram':
/dev/shm/coreboot/src/cpu/qemu-x86/cache_as_ram_bootblock.S:46:(.init+0x1f): undefined reference to `walkcbfs_asm'
/dev/shm/coreboot/src/cpu/qemu-x86/cache_as_ram_bootblock.S:46:(.init+0x1f): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `walkcbfs_asm'
make: *** [src/arch/x86/Makefile.mk:101: build/cbfs/fallback/bootblock.debug] Fehler 1
make: *** Es wird auf noch nicht beendete Prozesse gewartet....
</code></pre> coreboot - Bug #527 (New): Can't compile coreboot on Arch Linuxhttps://ticket.coreboot.org/issues/5272024-02-23T13:44:57Znaixin Lv
<p>I want to compile coreboot for my Gigabyte GA-H61M-DS2 mainboard, but I only found a short guide for this board at this site: <a href="https://www.iot-tech.dev/full.php?ar=166" class="external">https://www.iot-tech.dev/full.php?ar=166</a><br>
After downloaded the coreboot git repository, It gave me this error:</p>
<pre><code class="shell syntaxhl" data-language="shell">/home/zhongli/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/console/vtxprintf.o: <span class="k">in function</span> <span class="sb">`</span>number<span class="s1">':
/home/zhongli/coreboot/src/console/vtxprintf.c:63:(.text.number+0x12b): undefined reference to `__udivmoddi4'</span>
/home/zhongli/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/lib/gcc.o: <span class="k">in function</span> <span class="sb">`</span>__wrap___divdi3<span class="s1">':
/home/zhongli/coreboot/src/lib/gcc.c:19:(.text.__wrap___divdi3+0x1): undefined reference to `__divdi3'</span>
/home/zhongli/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/lib/gcc.o: <span class="k">in function</span> <span class="sb">`</span>__wrap___udivdi3<span class="s1">':
/home/zhongli/coreboot/src/lib/gcc.c:20:(.text.__wrap___udivdi3+0x1): undefined reference to `__udivdi3'</span>
make: <span class="k">***</span> <span class="o">[</span>src/arch/x86/Makefile.mk:191: build/cbfs/fallback/romstage.debug] Error 1
</code></pre>
<p>And I'll put my config file on here.<br>
Any help ?</p>
coreboot - Bug #506 (New): Apollolake/Geminilake boards fail to boot OS when CPU microcode includ...https://ticket.coreboot.org/issues/5062023-08-30T17:56:27ZMatt DeVilliermatt.devillier@gmail.com
<p>Apollolake/Geminilake (APL/GLK) based devices are unique in that they have a special firmware region called IFWI, which contains the coreboot bootbock and CPU microcode, among other things. As part of building an image for an APL/GLK-based device, an existing IFWI binary must be supplied in order to be modified with coreboot's bootblock. The CPU microcode however is not updated, as the region size is fixed, and current tooling (util/cbfstool/ifwitool) does not have the ability to resize it. </p>
<p>When the default coreboot Kconfig option <code>CPU_MICROCODE_CBFS_DEFAULT_BINS</code> for CPU microcode is selected, coreboot will include a microcode update in CBFS which is (much) newer than that in the IFWI, and apply it in ramstage. This causes any OS to fail to boot: Linux hangs, and Windows BSODs with an <code>UNSUPPORTED CPU</code> error. The only workaround is to include an external CPU microcode binary which matches the one in IFWI (ie, use both the IFWI and microcode extracted from the original vendor firmware image). Not including any microcode update has not been tested, and may also be an option.</p>
<p>There have been a few patches submitted to work around this (CB:65680, CB:64863), but the former requires external, non-public tooling, and the latter fails if the new microcode update is larger than the existing IFWI region.</p>
<p>Possible areas to investigate are adding resizing capability to ifwitool, and constructing an IFWI from scratch (vs copying/modifying the existing one)</p>
coreboot - Bug #325 (New): Asus P5QL-EM: NVIDIA card in PCIe X1 port not workinghttps://ticket.coreboot.org/issues/3252021-12-03T12:44:53ZFrancois Ollonoisollonois@gmx.net
<p>When using my nvidia geforce GT 710 in PCIe X1 slot the screen is not working after graphic driver is loaded. With nomodeset parameter it works but without driver I can't start Xorg.<br>
The same card in X16 slot works, but I want to use the X16 port on this board for a nvme adapter card. <br>
I discussed the problem with nouveau project and they consider some sort of DMA problem and found some differences between vendor firmware and coreboot that may cause the problems. <br>
They also mention some kernel parameters to work around this problem but even with this parameters the screen flickers when using Xorg.<br>
With original vendor firmware the card works in X1 port. <br>
I use this card:<br>
<a href="https://www.asus.com/Motherboards-Components/Graphics-Cards/ASUS/GT710-4H-SL-2GD5/" class="external">https://www.asus.com/Motherboards-Components/Graphics-Cards/ASUS/GT710-4H-SL-2GD5/</a></p>
<p>Here is the link to the nouveau ticket.<br>
<a href="https://gitlab.freedesktop.org/drm/nouveau/-/issues/132" class="external">https://gitlab.freedesktop.org/drm/nouveau/-/issues/132</a></p>
<p>I will also add the kernel log and lcpci output and the cbmem output.<br>
And here are some information about the differences:</p>
<pre><code>Coreboot:
Latency: 0, Cache Line Size: 64 bytes
Capabilities: [100 v1] Virtual Channel
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Vendor:
Latency: 0, Cache Line Size: 32 bytes
Capabilities: [100 v1] Virtual Channel
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
</code></pre>
<p>The host bridge also has SERR+ on coreboot vs SERR- on vendor.</p>
<p>And the root ports actually have a lot of differences, including stuff like</p>
<pre><code>Coreboot:
Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s (ok), Width x0 (downgraded)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Vendor:
Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s (ok), Width x0 (downgraded)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #0, PowerLimit 10.000W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
Changed: MRL- PresDet- LinkState-
</code></pre> coreboot - Bug #285 (New): Asus A88XM-E: xHCI USB ports only with USB 1.x speedhttps://ticket.coreboot.org/issues/2852020-10-19T09:56:21ZPaul Menzelpmenzel+ticket.coreboot@molgen.mpg.de
<p><a href="https://review.coreboot.org/c/coreboot/+/46365" class="external">Description from Balázs</a>:</p>
<blockquote>
<p>AFAIR, the USB3 ports were really problematic.<br>
Most of the time it was really slow, somewhere around USB 1.x speed.<br>
The only way to have the ports properly working to reset the motherboard with the coreboot bios chip in, while the factory bios was loaded. And this way somehow the old fw remain in the controller and the ports were fast as they should be.</p>
</blockquote>
<p>So, first thing to check the xHC firmware version used by the vendor firmware. <a href="https://review.coreboot.org/plugins/gitiles/blobs/+/1aff9c32eb15fc0e9da2f389f9b77e06d6fd3a21/southbridge/amd/hudson/Release_Hudson2XHC.txt" class="external">coreboot uses version 1.0.0.48.</a></p>
coreboot - Bug #279 (New): All hp snb_ivb_laptops: Windows 10 & 7 BSODhttps://ticket.coreboot.org/issues/2792020-08-17T16:12:30ZBabble BonesBabbleBones@protonmail.com
<p>All HP laptops seem to blue screen due to some ACPI issue. Hoping to hear from Iru if is aware of what's missing.</p>
coreboot - Bug #268 (New): Building Chrome EC within coreboot requires libftdi for no good reasonhttps://ticket.coreboot.org/issues/2682020-07-06T06:36:46ZPaul Menzelpmenzel+ticket.coreboot@molgen.mpg.de
<pre><code>$ uname -m
ppc64le
$ make crossgcc CPUS=100
[…]
Welcome to the coreboot cross toolchain builder v157851fdbb (2020-05-29)
[…]
$ make what-jenkins-does
[…]
GOOGLE_SAMUS build FAILED after 73s!
Log excerpt:
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:66: undefined reference to `ftdi_get_error_string'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:71: undefined reference to `ftdi_set_baudrate'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:79: undefined reference to `ftdi_setdtr'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:119: undefined reference to `ftdi_write_data'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:128: undefined reference to `ftdi_read_data'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:156: undefined reference to `ftdi_usb_close'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:157: undefined reference to `ftdi_deinit'
/usr/bin/ld: /dev/shm/coreboot/3rdparty/chromeec/util/ec_uartd.c:73: undefined reference to `ftdi_get_error_string'
collect2: error: ld returned 1 exit status
</code></pre> coreboot - Bug #251 (New): Add SD card detect GPIO in jslrvp devicetreehttps://ticket.coreboot.org/issues/2512020-01-09T06:05:32ZAamir Bohraaamir.bohra@intel.com
<p>The SD card detect GPIO currently needs to be added once the jsl gpio driver code is merged.<br>
This bug tracks its implementation.</p>
coreboot - Bug #244 (New): Bootblock size inflated by over 1000% https://ticket.coreboot.org/issues/2442019-12-01T15:59:56ZPatrik Tesarikmail@patrik-tesarik.de
<p>Hello everyone,</p>
<p>I just tried to build a new coreboot.rom for my Thinkpad X220. </p>
<p>The build fails because the payload (tianocore) does not fit into the (standard) CBFS (1MB) anymore. </p>
<p>It turns out: The bootblock size increased from < 5KB to over 60 KB in the latest master build. <br>
Tianocore has roughly the same size, a little less actually. <br>
In the last build the empty space was around 3KB. If bootblock size hadn't increased by that much, it would've been a fit. </p>
<p>Unfortunatly I have no knowledge about how the bootblock (size) is affected by or build in coreboot. I did not find any specific documentation on this regard in docs.coreboot.org. </p>
<p>I'd really appreciate information/hints about how I can tackle this issue myself or how I can provide you with information needed to investigate this behavior. </p>
coreboot - Bug #239 (New): Build fails: No rule to make target pxe rom, but file existshttps://ticket.coreboot.org/issues/2392019-10-23T23:45:51ZIan Kellingiank@fsf.org
<p>.config has: </p>
<p>CONFIG_PXE_ROM=y<br>
CONFIG_PXE_ROM_FILE="/path/to/808610d3.rom"</p>
<p>running make fails with:</p>
<p>make: *** No rule to make target '"/path/to/808610d3.rom"', needed by 'build/coreboot.pre'. Stop.</p>
<p>Menuconfig says it should be an existing rom file path, which it is.</p>
<p>This is on commit 7bdedcdc338e5043f9670790a4333260b63087aa which is master as of today.</p>
coreboot - Bug #221 (New): ASUS KCMA-D8 doesn't POST reliably when CMOS is completely cleared of ...https://ticket.coreboot.org/issues/2212019-07-19T11:26:28ZSean Rhoneespionage724@posteo.net
<p>I noticed that if I flash Coreboot, and wipe the CMOS out completely (remove the battery and power for a bit), sometimes my system won't POST. Might work the first time, might take a reset or two, and worst-case it took 5 resets in a row for it to POST.</p>
<p>If I boot the ASUS vendor BIOS, remove the BIOS chip, and replace it with a Coreboot chip, it seemingly POSTs fine consistently.</p>
<p>For Coreboot, I'm using the CMOS for NVRAM, and also the option that loads defaults every boot.</p>
coreboot - Bug #165 (New): [ga-g41m-es2l] [coreboot 4.7] [grub] GRUB payload (launched from seab...https://ticket.coreboot.org/issues/1652018-05-05T13:56:21ZAnonymous
<p>Hello,</p>
<p>[ga-g41m-es2l] [grub] GRUB halts when trying to load linux kernel</p>
<p>I'm trying to use GRUB2 payload launched from seabios. (To make sure it works before using it as main payload)<br>
The GRUB2 payload I included in my rom is using vesafb [1][2], it loads fine from seabios but once it tries to load the first menuentry, it halts and I'm forced to reset to boot from seabios again. The keyboard doesn't respond at all as well on GRUB (USB)<br>
So I'm trying to figure out why it isn't working.<br>
The coreboot rom I'm using is 4.7-fd470f7163709c1022ee6185134a2387812774ec with :</p>
<ul>
<li>NGI</li>
<li>Linear FB</li>
<li>Seabios 1.11.0-0-g63451fc (seabios master = same issue)</li>
</ul>
<p>Is GRUB2 payload able to be launched from seabios on this board ? Or does it have to be launched as main payload ?</p>
<p>included : </p>
<ul>
<li>cbmem log (-> after a reset to seabios when grub halts)</li>
<li>nvramtool settings</li>
<li>cbfstools "print"</li>
<li>grub.cfg (extracted from libreboot rom)</li>
</ul>
<p>[1] I extracted it from a libreboot rom I was using with success previously<br>
[2] I also compiled a fresh GRUB2 payload from 2.02 release, the issue is exactly the same.</p>
<hr>
<p>Strangely, if using the exact same grub payload with coreboot 4.6-db508565d2483394b709654c57533e55eebace51 with :</p>
<ul>
<li>NGI</li>
<li>Linear FB</li>
<li>Seabios 1.10.2-0-g5f4c7b1</li>
</ul>
<p>Then GRUB2 payload works fine ! It loads my 4.9.97 kernel without issue except this little error with my keyboard (not sure why) :</p>
<p>[ 0.508007] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver<br>
[ 0.508552] ehci-pci: EHCI PCI platform driver<br>
[ 0.508737] SCSI subsystem initialized<br>
[ 0.508926] ehci-pci 0000:00:1d.7: EHCI Host Controller<br>
[ 0.508938] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 1<br>
[ 0.508967] ehci-pci 0000:00:1d.7: debug port 1<br>
[ 0.511097] i8042: Failed to disable AUX port, but continuing anyway... Is this a SiS?<br>
[ 0.511101] i8042: If AUX port is really absent please use the 'i8042.noaux' option<br>
[ 0.511777] mpt3sas version 13.100.00.00 loaded<br>
[ 0.513408] ehci-pci 0000:00:1d.7: can't setup: -110<br>
[ 0.513475] ehci-pci 0000:00:1d.7: USB bus 1 deregistered<br>
[ 0.513508] xhci_hcd 0000:02:00.0: xHCI Host Controller<br>
[ 0.513515] xhci_hcd 0000:02:00.0: new USB bus registered, assigned bus number 1<br>
[ 0.513590] ehci-pci 0000:00:1d.7: init 0000:00:1d.7 fail, -110<br>
[ 0.513616] ehci-pci: probe of 0000:00:1d.7 failed with error -110</p>
<p>Thanks for your help</p>
coreboot - Bug #105 (New): Add timeouts to nehalem raminithttps://ticket.coreboot.org/issues/1052017-04-01T09:06:05ZAni Changanichang@protonmail.ch
<p>I drafted a patch copying from EC init. Two questions:<br>
1) timeout = 0x7ff; how much time is it? micros? millis? ... ?<br>
2) what about the read32/write32 after the loops? In the case the ME isn't there ... have those to be skipped? (ie: return before read/write)</p>
<p>regards</p>
coreboot - Bug #101 (New): Asus M2V fails to boot to payloadhttps://ticket.coreboot.org/issues/1012017-03-15T15:41:04ZPaul Menzelpmenzel+ticket.coreboot@molgen.mpg.de
<p>A coreboot image built from commit 7f37418 (AGESA f14: Fix infinite loop) with the attached config does not get to the payload stage.</p>
<pre><code>$ build/cbfstool build/coreboot.rom print
Name Offset Type Size
cbfs master header 0x0 cbfs header 32
cpu_microcode_blob.bin 0x80 microcode 6144
fallback/ramstage 0x1900 stage 58951
fallback/romstage 0xff80 stage 49980
config 0x1c340 raw 351
revision 0x1c500 raw 570
cmos_layout.bin 0x1c780 cmos_layout 1392
fallback/dsdt.aml 0x1cd40 raw 3000
img/nvramcui 0x1d940 payload 148104
img/memtest 0x41c00 payload 180268
fallback/payload 0x6dc80 payload 59680
(empty) 0x7c600 null 12824
bootblock 0x7f840 bootblock 1656
$ sudo ~/src/seabios/scripts/readserial.py /dev/ttyUSB0 1200
======= Wed Mar 15 17:09:19 2017 (adjust=8333.3us)
00.000: <fe>
00.484:
00.483: coreboot-4.5-1291-g7f37418 Wed Mar 15 13:11:50 UTC 2017 romstage starting...
00.653: m2v_bus_init
00.654: it8712f gpio init...
00.654: it8712f gpio: 25=00
00.655: it8712f gpio: 28=00
00.655: it8712f gpio: 29=40
00.656: it8712f gpio: 2a=00
00.656: it8712f gpio: 2c=1d
00.657: it8712f gpio: 62=0a
00.657: it8712f gpio: 63=20
00.658: it8712f gpio: b8=00
00.659: it8712f gpio: c0=00
00.659: it8712f gpio: c3=00
00.660: it8712f gpio: c4=c0
00.660: it8712f gpio: c8=00
00.661: it8712f gpio: cb=00
00.661: it8712f gpio: cc=c0
00.662: it8712f gpio: Setting DDR2 voltage to 1.80V
00.662: now booting...
00.664: Enabling routing table for node 0 done.
00.666: Enabling UP settings
00.666: coherent_ht_finalize
00.667: done
00.668: core0 started:
00.670: now booting... All core 0 started
00.670: started ap apicid:
00.671: SBLink=00
00.673: NC node|link=00
00.676: 00entering optimize_link_incoherent_ht
00.677: sysinfo->link_pair_num=0x1
00.678: entering ht_optimize_link
00.679: pos=0x8a, unfiltered freq_cap=0x8075
00.679: pos=0x8a, filtered freq_cap=0x75
00.680: pos=0x6e, unfiltered freq_cap=0x75
00.680: pos=0x6e, filtered freq_cap=0x75
00.680: freq_cap1=0x75, freq_cap2=0x75
00.681: dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
00.681: dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
00.681: width_cap1=0x11, width_cap2=0x11
00.681: dev1 input ln_width1=0x4, ln_width2=0x4
00.682: dev1 input width=0x1
00.682: dev1 output ln_width1=0x4, ln_width2=0x4
00.683: dev1 input|output width=0x11
00.683: old dev1 input|output width=0x11
00.683: dev2 input|output width=0x11
00.684: old dev2 input|output width=0x11
00.684: after ht_optimize_link for link pair 0, reset_needed=0x1
00.685: after optimize_link_read_pointers_chain, reset_needed=0x1
00.685: 01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
00.691: 01ht reset -
00.692: soft reset
00.869:
00.869:
00.869: coreboot-4.5-1291-g7f37418 Wed Mar 15 13:11:50 UTC 2017 romstage starting...
01.011: m2v_bus_init
01.012: it8712f gpio init...
01.012: it8712f gpio: 25=00
01.013: it8712f gpio: 28=00
01.013: it8712f gpio: 29=40
01.014: it8712f gpio: 2a=00
01.014: it8712f gpio: 2c=1d
01.015: it8712f gpio: 62=0a
01.016: it8712f gpio: 63=20
01.016: it8712f gpio: b8=00
01.017: it8712f gpio: c0=00
01.017: it8712f gpio: c3=00
01.018: it8712f gpio: c4=c0
01.018: it8712f gpio: c8=00
01.019: it8712f gpio: cb=00
01.020: it8712f gpio: cc=c0
01.020: it8712f gpio: Setting DDR2 voltage to 1.80V
01.020: now booting...
01.023: Enabling routing table for node 0 done.
01.024: Enabling UP settings
01.024: coherent_ht_finalize
01.025: done
01.026: core0 started:
01.028: now booting... All core 0 started
01.028: started ap apicid:
01.030: SBLink=00
01.031: NC node|link=00
01.034: 00entering optimize_link_incoherent_ht
01.035: sysinfo->link_pair_num=0x1
01.036: entering ht_optimize_link
01.037: pos=0x8a, unfiltered freq_cap=0x8075
01.037: pos=0x8a, filtered freq_cap=0x75
01.038: pos=0x6e, unfiltered freq_cap=0x75
01.038: pos=0x6e, filtered freq_cap=0x75
01.038: freq_cap1=0x75, freq_cap2=0x75
01.039: dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
01.039: dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
01.039: width_cap1=0x11, width_cap2=0x11
01.040: dev1 input ln_width1=0x4, ln_width2=0x4
01.040: dev1 input width=0x1
01.041: dev1 output ln_width1=0x4, ln_width2=0x4
01.041: dev1 input|output width=0x11
01.041: old dev1 input|output width=0x11
01.042: dev2 input|output width=0x11
01.042: old dev2 input|output width=0x11
01.043: after ht_optimize_link for link pair 0, reset_needed=0x0
01.043: after optimize_link_read_pointers_chain, reset_needed=0x0
01.043: 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
01.049: 00after enable_fid_change
01.193: Current fid_cur: 0x2, fid_max: 0xc
01.194: Requested fid_new: 0xc
01.195: FidVid table step fidvid: 0xc
01.327: R<ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff><ff>
</code></pre> coreboot - Bug #92 (New): Asus KGPE-D16 does not reboot out of some payloadhttps://ticket.coreboot.org/issues/922017-01-31T17:09:47ZPaul Menzelpmenzel+ticket.coreboot@molgen.mpg.de
<p>Starting the payloads nvramcui, coreinfo, and Memtest86+ from SeaBIOS, and quitting them, the system should reboot. In my experience the system does not come back up. Nothing is written to the serial console.</p>
<pre><code># This image was built using coreboot 4.5-917-g545edca
CONFIG_ANY_TOOLCHAIN=y
CONFIG_USE_OPTION_TABLE=y
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_USE_BLOBS=y
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_KGPE_D16=y
CONFIG_NO_POST=y
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x40000
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
CONFIG_PAYLOAD_GRUB2=y
CONFIG_GRUB2_EXTRA_MODULES="boottime"
CONFIG_GRUB2_INCLUDE_RUNTIME_CONFIG_FILE=y
CONFIG_COREINFO_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_MASTER=y
CONFIG_NVRAMCUI_SECONDARY_PAYLOAD=y
CONFIG_TINT_SECONDARY_PAYLOAD=y
</code></pre>