Issue Tracker: Issueshttps://ticket.coreboot.org/https://ticket.coreboot.org/themes/PurpleMine2-2.16.2/favicon/favicon.ico?12024-02-05T03:40:27ZIssue Tracker
Redmine flashrom - Bug #525 (New): Potential clash when custom get_flash_region() called in erase_writehttps://ticket.coreboot.org/issues/5252024-02-05T03:40:27ZAnastasia Klimchuk
<p><code>erase_write</code> in erasure_layout.c makes a call to <code>get_flash_region()</code>. This call happens after erase layout is calculated, however <code>get_flash_region()</code> can potentially return smaller region.</p>
<p>Issue needs research (and fix if needed).</p>
<p>Originally reported by Vincent Fazio, copying the report below:</p>
<pre><code>As part of looking over #1 and #2, I developed some slight concerns about the loop on line 314 which is separate from
this patchset. I don't know if it warrants an issue and further discussion, and I haven't spelunked into the erase function
selection logic, but the concern I have there is we've already pre-calculated what erase functions we're using but
`get_flash_region` could return a region with a shorter end range, meaning the selected erase block fn could erase part
of the next region. So if we had a 32k erase block fn, it seems like if region.end forces the length of the erasable region
to 4k, we don't actually select a 4k erase function and instead continue to use a 32k function. If the next region is write
protected it seems like we'd have verification errors.
I think this currently only affects masters that have get_region defined, so `opaque_master_ich_hwseq` is at risk here.
This may have been less of a risk with the legacy path because, from what I remember, it always used the smallest working
erase block function, however the new path adjusts the function used based on the amount of changed data and coalesces blocks
when possible (I think).
</code></pre> flashrom - Bug #520 (New): Factor out verification from erase pathhttps://ticket.coreboot.org/issues/5202023-12-19T15:59:01ZVincent Fazio
<p>Currently, <code>flashrom_image_erase</code> differs from <code>flashrom_image_write</code> in how it performs its verification.</p>
<p>When writes are completed, verification occurs <u>afterwards</u> per the verify flags specified in the <code>flashctx</code> argument.</p>
<pre><code class="C syntaxhl" data-language="C"> <span class="cm">/* Verify only if we actually changed something. */</span>
<span class="k">if</span> <span class="p">(</span><span class="n">verify</span> <span class="o">&&</span> <span class="o">!</span><span class="n">all_skipped</span><span class="p">)</span> <span class="p">{</span>
<span class="n">msg_cinfo</span><span class="p">(</span><span class="s">"Verifying flash... "</span><span class="p">);</span>
<span class="cm">/* Work around chips which need some time to calm down. */</span>
<span class="n">programmer_delay</span><span class="p">(</span><span class="n">flashctx</span><span class="p">,</span> <span class="mi">1000</span><span class="o">*</span><span class="mi">1000</span><span class="p">);</span>
<span class="k">if</span> <span class="p">(</span><span class="n">verify_all</span><span class="p">)</span>
<span class="n">combine_image_by_layout</span><span class="p">(</span><span class="n">flashctx</span><span class="p">,</span> <span class="n">newcontents</span><span class="p">,</span> <span class="n">oldcontents</span><span class="p">);</span>
<span class="n">ret</span> <span class="o">=</span> <span class="n">verify_by_layout</span><span class="p">(</span><span class="n">flashctx</span><span class="p">,</span> <span class="n">verify_layout</span><span class="p">,</span> <span class="n">curcontents</span><span class="p">,</span> <span class="n">newcontents</span><span class="p">);</span>
</code></pre>
<p>For the erase path, there is no post-operation verification. Instead, <code>check_erased_range</code> is called regardless of verify flags, performing verification even if the user doesn't request it and imposing a performance penalty.</p>
coreboot - Bug #505 (New): Intel Harcuvar CRB Denverton_NS ะก3000. Only 15 cores of a 16 core proc...https://ticket.coreboot.org/issues/5052023-08-22T08:08:42ZDmitry Ponamorev
<p>Found a bug with the definition of not all processor cores of the Intel(R) Atom(TM) CPU C3958 processor in operating systems.<br>
The Debian or Ubuntu operating system defines only 15 cores. The problem concerns exactly the 16th core processor. <br>
For processors with fewer cores, the number of cores is determined correctly. <br>
The problem was found in coreboot version 4.14 and later. Version coreboot 4.11 did not have this problem.<br>
Most likely this is due to incorrect initialization of apic_id. (apic_id 0) </p>
<p>An example of the initialization output of the processor cores is below:</p>
<p>Will perform SMM setup.<br>
CPU: Intel(R) Atom(TM) CPU C3958 @ 2.00GHz.<br>
AP: slot 1 apic_id 6, MCU rev: 0x00000034<br>
AP: slot 13 apic_id 1e, MCU rev: 0x00000034<br>
AP: slot 6 apic_id a, MCU rev: 0x00000034<br>
AP: slot 14 apic_id e, MCU rev: 0x00000034<br>
AP: slot 5 apic_id 4, MCU rev: 0x00000034<br>
AP: slot 2 apic_id 10, MCU rev: 0x00000034<br>
AP: slot 4 apic_id 14, MCU rev: 0x00000034<br>
AP: slot 11 apic_id 1c, MCU rev: 0x00000034<br>
AP: slot 15 apic_id 8, MCU rev: 0x00000034<br>
AP: slot 8 apic_id 16, MCU rev: 0x00000034<br>
AP: slot 10 apic_id c, MCU rev: 0x00000034<br>
AP: slot 3 apic_id 1a, MCU rev: 0x00000034<br>
AP: slot 9 apic_id 2, MCU rev: 0x00000034<br>
AP: slot 7 apic_id 12, MCU rev: 0x00000034<br>
AP: slot 12 apic_id 18, MCU rev: 0x00000034<br>
smm_place_entry_code: smbase 7ffe8400, stack_top 7fe08000<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffec000, cpu = 0<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe9000, cpu = 12<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe8800, cpu = 14<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe9c00, cpu = 9<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe8400, cpu = 15<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffeb800, cpu = 2<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe9400, cpu = 11<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe8c00, cpu = 13<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffea000, cpu = 8<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffeb400, cpu = 3<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffeb000, cpu = 4<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffea400, cpu = 7<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffe9800, cpu = 10<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffebc00, cpu = 1<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffea800, cpu = 6<br>
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffeac00, cpu = 5<br>
Initializing CPU #0<br>
Turbo is unavailable<br>
CPU #0 initialized<br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: FAQ in the wiki doesn't work (Closed)" href="https://ticket.coreboot.org/issues/8">#8</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: Use of CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is a mess (Closed)" href="https://ticket.coreboot.org/issues/12">#12</a><br>
Initializing CPU <a class="issue tracker-2 status-5 priority-2 priority-default closed" title="Feature: printout lenovo ec power cause register (Closed)" href="https://ticket.coreboot.org/issues/14">#14</a><br>
Initializing CPU <a class="issue tracker-2 status-5 priority-2 priority-default closed" title="Feature: Documentation for coreboot's public interface (Closed)" href="https://ticket.coreboot.org/issues/4">#4</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed behind-schedule" title="Bug: gerrit+github oauth has a wrong redirection url (Closed)" href="https://ticket.coreboot.org/issues/9">#9</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: nvramtool fails to extract CMOS layout from CBMEM (Closed)" href="https://ticket.coreboot.org/issues/10">#10</a><br>
Initializing CPU #1<br>
Initializing CPU <a class="issue tracker-1 status-2 priority-2 priority-default overdue behind-schedule" title="Bug: board-status uploads incorrect reports if config not found (In Progress)" href="https://ticket.coreboot.org/issues/15">#15</a><br>
Initializing CPU <a class="issue tracker-2 status-5 priority-2 priority-default closed" title="Feature: gnawty support based on acer cb3-111 (Closed)" href="https://ticket.coreboot.org/issues/7">#7</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: race condition concerning amdfwtool in the build system (Closed)" href="https://ticket.coreboot.org/issues/11">#11</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed behind-schedule" title="Bug: The build system isn't helpful when util/xcompile/xcompile fails because of missing dependencies. (Closed)" href="https://ticket.coreboot.org/issues/3">#3</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: x201: broken on git master (Closed)" href="https://ticket.coreboot.org/issues/2">#2</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: allow creating new wiki accounts (Closed)" href="https://ticket.coreboot.org/issues/13">#13</a><br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: channel test fails on a Samsung DDR3L 8G memory with IVB processor (Closed)" href="https://ticket.coreboot.org/issues/6">#6</a><br>
CPU <a class="issue tracker-2 status-5 priority-2 priority-default closed" title="Feature: gnawty support based on acer cb3-111 (Closed)" href="https://ticket.coreboot.org/issues/7">#7</a> initialized<br>
CPU <a class="issue tracker-2 status-5 priority-2 priority-default closed" title="Feature: printout lenovo ec power cause register (Closed)" href="https://ticket.coreboot.org/issues/14">#14</a> initialized<br>
CPU <a class="issue tracker-1 status-2 priority-2 priority-default overdue behind-schedule" title="Bug: board-status uploads incorrect reports if config not found (In Progress)" href="https://ticket.coreboot.org/issues/15">#15</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: x201: broken on git master (Closed)" href="https://ticket.coreboot.org/issues/2">#2</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: channel test fails on a Samsung DDR3L 8G memory with IVB processor (Closed)" href="https://ticket.coreboot.org/issues/6">#6</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: Use of CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is a mess (Closed)" href="https://ticket.coreboot.org/issues/12">#12</a> initialized<br>
Initializing CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: x201: power on when plugging powerplug into (Closed)" href="https://ticket.coreboot.org/issues/5">#5</a><br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed behind-schedule" title="Bug: The build system isn't helpful when util/xcompile/xcompile fails because of missing dependencies. (Closed)" href="https://ticket.coreboot.org/issues/3">#3</a> initialized<br>
CPU #1 initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: nvramtool fails to extract CMOS layout from CBMEM (Closed)" href="https://ticket.coreboot.org/issues/10">#10</a> initialized<br>
CPU <a class="issue tracker-2 status-5 priority-2 priority-default closed" title="Feature: Documentation for coreboot's public interface (Closed)" href="https://ticket.coreboot.org/issues/4">#4</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: race condition concerning amdfwtool in the build system (Closed)" href="https://ticket.coreboot.org/issues/11">#11</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: x201: power on when plugging powerplug into (Closed)" href="https://ticket.coreboot.org/issues/5">#5</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed behind-schedule" title="Bug: gerrit+github oauth has a wrong redirection url (Closed)" href="https://ticket.coreboot.org/issues/9">#9</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: FAQ in the wiki doesn't work (Closed)" href="https://ticket.coreboot.org/issues/8">#8</a> initialized<br>
CPU <a class="issue tracker-1 status-5 priority-2 priority-default closed" title="Bug: allow creating new wiki accounts (Closed)" href="https://ticket.coreboot.org/issues/13">#13</a> initialized</p>
flashrom - Bug #502 (New): Erase and Write problem with a SST25VF512.https://ticket.coreboot.org/issues/5022023-08-03T10:38:22ZGianni Lerro
<p>Hi<br>
I want to flash new firmware to a SST25VF512 but neither erase nor write works, reading current firmware works.</p>
<p>The programmer I used is this one CH341A Mini Programmer (<a href="https://www.onetransistor.eu/2017/08/ch341a-mini-programmer-schematic.html" class="external">https://www.onetransistor.eu/2017/08/ch341a-mini-programmer-schematic.html</a>), mine has a CH341B (<a href="https://www.wch-ic.com/products/CH341.html?" class="external">https://www.wch-ic.com/products/CH341.html?</a>) that can work without the external clock using the internal one.</p>
<p>With this, MIT Licensed, windows program AS Programmer (<a href="https://github.com/nofeletru/UsbAsp-flash" class="external">https://github.com/nofeletru/UsbAsp-flash</a>) everything works, reading, writing, deleting, enabling and disabling write protection.</p>
<p>My OS is Debian GNU/Linux Testing</p>
<p>Thanks</p>
flashrom - Bug #498 (New): DediProg SF600Plus unable to flash W25Q512JV chiphttps://ticket.coreboot.org/issues/4982023-06-29T12:32:53ZVojtech Vesely
<p>I am working on adding support for chip Winbond W25Q512JV-FIM, which should be quite similar to existing W25Q512JV. Writing to the chip is a problem, reading is fine.</p>
<pre><code>$ ./flashrom -p dediprog -w random.bin
flashrom 1.4.0-devel (git:v1.2-1310-g1ee04cd5) on Linux 6.3.9-arch1-1 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Using dediprog id SF000000.
Found Generic flash chip "unknown SPI chip (REMS)" (0 kB, SPI) on dediprog.
===
This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE
This flash part has status UNTESTED for operations: WP
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to flashrom@flashrom.org if any of the above operations
work correctly for you with this flash chip. Please include the flashrom log
file for all operations you tested (see the man page for details), and mention
which mainboard or programmer you tested in the subject line.
Thanks for your help!
Error: Image size (67108864 B) doesn't match the expected size (0 B)!
</code></pre>
<p>This problem does not appear in <code>v1.3</code>, only in <code>master</code> branch.</p>
<p>Used hardware:</p>
<ul>
<li>Programmer: DediProg SF600Plus, Firmware version : 7.3.08, Hardware version : 2.3</li>
<li>Chip: W25Q512JV-FIM</li>
</ul>
coreboot - Bug #449 (In Progress): ThinkPad T440p fail to start, continous beeping & LED blinkinghttps://ticket.coreboot.org/issues/4492023-01-14T20:02:28ZCrazy Foxcrazyfox.ua@gmail.com
<p>Hi, Team<br>
Being corebooted before and works fine on 4.17.</p>
<p>After flashing 4.18 my t440p wont startup (black screen, constant beeping & LED blinking). I've tried and retried different nconfigs but result is the same. I know that it is lack of information, but I need to recover the laptop first to grab some logs from it.</p>
<p>Log from FT232H's debug is attached, the rest of info (defconfig, flashrom command etc. will upload soon)</p>
flashrom - Bug #390 (New): Libflashrom progress goes backwards for erase and write operationshttps://ticket.coreboot.org/issues/3902022-06-16T22:52:11ZAnastasia Klimchuk
<p>When flashrom runs with <code>--progress</code> argument in the command line, it shows % progress for all operations. % is working nicely for read and verify operations. <br>
However for erase and write operations % starts with 0, goes up and then goes backwards to 0 again. By its nature, % progress should not go backwards.</p>
<p>Bug can be reproduced with dummyflasher.</p>
<p>Small repro case with just erase:</p>
<p>$ ./flashrom -p dummy:emulate=W25Q128FV -E --progress<br>
flashrom v1.2-759-gcba5de5 on Linux 5.16.18-1rodete2-amd64 (x86_64)<br>
flashrom is free software, get the source code at <a href="https://flashrom.org" class="external">https://flashrom.org</a></p>
<p>Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).<br>
Found Winbond flash chip "W25Q128.V" (16384 kB, SPI) on dummy.</p>
<p>Erasing and writing flash chip... [READ] 100% complete... [READ] 0% complete... <br>
Erase/write done.</p>
<p>Longer repro case where you can see that read and verify works, but erase and write do not:</p>
<p>$ ./flashrom -p dummy:emulate=W25Q128FV,image=/tmp/rom -w /tmp/16m_rand.bin --progress<br>
flashrom v1.2-763-gb10d55049 on Linux 5.18.1-arch1-1 (x86_64)<br>
flashrom is free software, get the source code at <a href="https://flashrom.org" class="external">https://flashrom.org</a></p>
<p>Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).<br>
Found Winbond flash chip "W25Q128.V" (16384 kB, SPI) on dummy.</p>
<p>Reading old flash chip contents... [READ] 0% complete... [READ] 1% complete... [READ] 2% complete... [READ] 3% complete... [READ] 4% complete... [READ] 5% complete... [READ] 6% complete... [READ] 7% complete... [READ] 8% complete... [READ] 9% complete... [READ] 10% complete... [READ] 11% complete... [READ] 12% complete... [READ] 13% complete... [READ] 14% complete... [READ] 15% complete... [READ] 16% complete... [READ] 17% complete... [READ] 18% complete... [READ] 19% complete... [READ] 20% complete... [READ] 21% complete... [READ] 22% complete... [READ] 23% complete... [READ] 24% complete... [READ] 25% complete... [READ] 26% complete... [READ] 27% complete... [READ] 28% complete... [READ] 29% complete... [READ] 30% complete... [READ] 31% complete... [READ] 32% complete... [READ] 33% complete... [READ] 34% complete... [READ] 35% complete... [READ] 36% complete... [READ] 37% complete... [READ] 38% complete... [READ] 39% complete... [READ] 40% complete... [READ] 41% complete... [READ] 42% complete... [READ] 43% complete... [READ] 44% complete... [READ] 45% complete... [READ] 46% complete... [READ] 47% complete... [READ] 48% complete... [READ] 49% complete... [READ] 50% complete... [READ] 51% complete... [READ] 52% complete... [READ] 53% complete... [READ] 54% complete... [READ] 55% complete... [READ] 56% complete... [READ] 57% complete... [READ] 58% complete... [READ] 59% complete... [READ] 60% complete... [READ] 61% complete... [READ] 62% complete... [READ] 63% complete... [READ] 64% complete... [READ] 65% complete... [READ] 66% complete... [READ] 67% complete... [READ] 68% complete... [READ] 69% complete... [READ] 70% complete... [READ] 71% complete... [READ] 72% complete... [READ] 73% complete... [READ] 74% complete... [READ] 75% complete... [READ] 76% complete... [READ] 77% complete... [READ] 78% complete... [READ] 79% complete... [READ] 80% complete... [READ] 81% complete... [READ] 82% complete... [READ] 83% complete... [READ] 84% complete... [READ] 85% complete... [READ] 86% complete... [READ] 87% complete... [READ] 88% complete... [READ] 89% complete... [READ] 90% complete... [READ] 91% complete... [READ] 92% complete... [READ] 93% complete... [READ] 94% complete... [READ] 95% complete... [READ] 96% complete... [READ] 97% complete... [READ] 98% complete... [READ] 99% complete... [READ] 100% complete... done.<br>
Erasing and writing flash chip... [WRITE] 6% complete... [READ] 0% complete... [WRITE] 0% complete... Erase/write done.<br>
Verifying flash... [READ] 1% complete... [READ] 2% complete... [READ] 3% complete... [READ] 4% complete... [READ] 5% complete... [READ] 6% complete... [READ] 7% complete... [READ] 8% complete... [READ] 9% complete... [READ] 10% complete... [READ] 11% complete... [READ] 12% complete... [READ] 13% complete... [READ] 14% complete... [READ] 15% complete... [READ] 16% complete... [READ] 17% complete... [READ] 18% complete... [READ] 19% complete... [READ] 20% complete... [READ] 21% complete... [READ] 22% complete... [READ] 23% complete... [READ] 24% complete... [READ] 25% complete... [READ] 26% complete... [READ] 27% complete... [READ] 28% complete... [READ] 29% complete... [READ] 30% complete... [READ] 31% complete... [READ] 32% complete... [READ] 33% complete... [READ] 34% complete... [READ] 35% complete... [READ] 36% complete... [READ] 37% complete... [READ] 38% complete... [READ] 39% complete... [READ] 40% complete... [READ] 41% complete... [READ] 42% complete... [READ] 43% complete... [READ] 44% complete... [READ] 45% complete... [READ] 46% complete... [READ] 47% complete... [READ] 48% complete... [READ] 49% complete... [READ] 50% complete... [READ] 51% complete... [READ] 52% complete... [READ] 53% complete... [READ] 54% complete... [READ] 55% complete... [READ] 56% complete... [READ] 57% complete... [READ] 58% complete... [READ] 59% complete... [READ] 60% complete... [READ] 61% complete... [READ] 62% complete... [READ] 63% complete... [READ] 64% complete... [READ] 65% complete... [READ] 66% complete... [READ] 67% complete... [READ] 68% complete... [READ] 69% complete... [READ] 70% complete... [READ] 71% complete... [READ] 72% complete... [READ] 73% complete... [READ] 74% complete... [READ] 75% complete... [READ] 76% complete... [READ] 77% complete... [READ] 78% complete... [READ] 79% complete... [READ] 80% complete... [READ] 81% complete... [READ] 82% complete... [READ] 83% complete... [READ] 84% complete... [READ] 85% complete... [READ] 86% complete... [READ] 87% complete... [READ] 88% complete... [READ] 89% complete... [READ] 90% complete... [READ] 91% complete... [READ] 92% complete... [READ] 93% complete... [READ] 94% complete... [READ] 95% complete... [READ] 96% complete... [READ] 97% complete... [READ] 98% complete... [READ] 99% complete... [READ] 100% complete... VERIFIED.</p>
flashrom - Bug #381 (In Progress): libflashrom API should be versioned before a releasehttps://ticket.coreboot.org/issues/3812022-05-13T02:37:54ZEdward .
<p>The libflashrom API was never quite finalised and in order to avoid being stuck in the future we should at least add a API versioning mechanism before doing a flashrom release.</p>
<p>This way in future a compat layer can be derived for a user while allowing us the flexibility to fundamentally change the API for the better. While unfortunate, it is what it is and a version field is generally a good idea regardless.</p>
<p>There are two types of versioning mechanisms required, one for runtime and the other for build/link-time.</p>
flashrom - Bug #374 (Response Needed): -x option filters only spaces when converting region names...https://ticket.coreboot.org/issues/3742022-04-28T01:27:32ZAnastasia Klimchuk
<p>Also check that manpage is updated</p>
<p>Relevant patch:<br>
<a href="https://review.coreboot.org/c/flashrom/+/52450" class="external">https://review.coreboot.org/c/flashrom/+/52450</a><br>
Manpage update here <a href="https://review.coreboot.org/c/flashrom/+/52892" class="external">https://review.coreboot.org/c/flashrom/+/52892</a></p>
flashrom - Bug #370 (New): Fix sb600spihttps://ticket.coreboot.org/issues/3702022-04-28T01:10:01ZAnastasia Klimchuk
<p>Original patch is linked<br>
Specific questions:<br>
1) API violations<br>
2) Soft bricks machines with >16MiB flash<br>
3) Blocking other cleanup work</p>
coreboot - Bug #309 (New): crossgcc: Handle missing tarballs in download stephttps://ticket.coreboot.org/issues/3092021-05-29T13:43:44ZPatrick Georgipgeorgi@google.com
<p>We keep a copy of the tarballs used by crossgcc in coreboot releases in <a href="https://coreboot.org/releases/crossgcc-sources/" class="external">https://coreboot.org/releases/crossgcc-sources/</a>, so we should fall back if a download failed.</p>
coreboot - Bug #279 (New): All hp snb_ivb_laptops: Windows 10 & 7 BSODhttps://ticket.coreboot.org/issues/2792020-08-17T16:12:30ZBabble BonesBabbleBones@protonmail.com
<p>All HP laptops seem to blue screen due to some ACPI issue. Hoping to hear from Iru if is aware of what's missing.</p>
coreboot - Bug #259 (New): T440p: Tianocore unable to boot Windows 10 (MACHINE_CHECK_EXCEPTION)https://ticket.coreboot.org/issues/2592020-06-09T18:20:28ZCrazy Foxcrazyfox.ua@gmail.com
<p>Hi, Team!</p>
<p>I've successfully corebooted my T440p (without dGPU) - Debian 10 works fine, but unable to boot into Windows 10 - getting BSOD with Stop Code: <code>MACHINE_CHECK_EXCEPTION</code><br>
The same exception appears even trying to boot from Windows usb installation media.</p>
<p>Tried different config options, tried coreboot master and v4.11/v4.12 tags with the same result</p>
<p>There is some info about my setup:</p>
<pre><code>$ git rev-parse HEAD
342a8c3b2bc0845638e852af01f3054256a8446c
</code></pre><pre><code>$ sudo hwinfo --cpu --short
cpu:
Intel(R) Core(TM) i7-4800MQ CPU @ 2.70GHz, 800 MHz
</code></pre><pre><code>$ cat defconfig
CONFIG_LOCALVERSION="GLETA1WW (2.55)"
CONFIG_USE_OPTION_TABLE=y
CONFIG_TIMESTAMPS_ON_CONSOLE=y
CONFIG_FW_CONFIG=y
CONFIG_FW_CONFIG_SOURCE_CBFS=y
CONFIG_VENDOR_LENOVO=y
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_CBFS_SIZE=0x200000
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="20AWS0VK00"
CONFIG_HAVE_IFD_BIN=y
CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
CONFIG_CONSOLE_POST=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_HAVE_MRC=y
CONFIG_MRC_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mrc.bin"
CONFIG_PCIEXP_CLK_PM=y
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
CONFIG_H8_SUPPORT_BT_ON_WIFI=y
CONFIG_HAVE_ME_BIN=y
CONFIG_CHECK_ME=y
CONFIG_USE_ME_CLEANER=y
CONFIG_HAVE_GBE_BIN=y
CONFIG_ELOG=y
CONFIG_USBDEBUG=y
CONFIG_USBDEBUG_DONGLE_FTDI_FT232H=y
CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
CONFIG_DRIVERS_PS2_KEYBOARD=y
CONFIG_DEBUG_TPM=y
CONFIG_TPM_RDRESP_NEED_DELAY=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_PAYLOAD_TIANOCORE=y
</code></pre> coreboot - Bug #251 (New): Add SD card detect GPIO in jslrvp devicetreehttps://ticket.coreboot.org/issues/2512020-01-09T06:05:32ZAamir Bohraaamir.bohra@intel.com
<p>The SD card detect GPIO currently needs to be added once the jsl gpio driver code is merged.<br>
This bug tracks its implementation.</p>
coreboot - Bug #66 (New): rmodule_copy_payload() does not initialize unused memoryhttps://ticket.coreboot.org/issues/662016-08-16T16:38:33ZTrammell Hudsonhudson@trmm.net
<p>If module->payload_size != rmodule_memory_size(module), the excess memory remains uninitialized in rmodule_copy_payload(). This prevents reproducible TPM measurements of the unpacked modules and could possibly lead to runtime bugs or security vulnerabilities.</p>