diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 122b8ac..f95a291 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1753,24 +1753,45 @@ static const struct ram_training *get_cached_training(void)
 }
 #endif
 
-/* FIXME: add timeout.  */
+/* FIXME: timeout added to workaround the lack of ME in the case it has been removed with me_cleaner. Testing needed. */
 static void wait_heci_ready(void)
 {
-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8));	// = 0x8000000c
+	int timeout;
+
+	timeout = 0x7ff;
+	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8) && --timeout) { // = 0x8000000c
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk(BIOS_SPEW, ".");
+	}
+	if (!timeout) {
+		printk(BIOS_DEBUG, "Timeout while waiting for ME init!\n");
+		// return -1;
+	}
 	write32((DEFAULT_HECIBAR + 0x4),
 		(read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
 }
 
-/* FIXME: add timeout.  */
+/* FIXME: timeout added to workaround the lack of ME in the case it has been removed with me_cleaner. Testing needed. */
 static void wait_heci_cb_avail(int len)
 {
+	int timeout;
+
 	union {
 		struct mei_csr csr;
 		u32 raw;
 	} csr;
 
-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8));
-
+	timeout = 0x7ff;
+	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8) && --timeout)  {
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk(BIOS_SPEW, ".");
+	};
+	if (!timeout) {
+		printk(BIOS_DEBUG, "Timeout while waiting for ME init!\n");
+		// return -1;
+	}
 	do
 		csr.raw = read32(DEFAULT_HECIBAR + 0x4);
 	while (len >